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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
9 *
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
14 */
15
16enum fields {
17 RS = 0x001,
18 RT = 0x002,
19 RD = 0x004,
20 RE = 0x008,
21 SIMM = 0x010,
22 UIMM = 0x020,
23 BIMM = 0x040,
24 JIMM = 0x080,
25 FUNC = 0x100,
26 SET = 0x200,
27 SCIMM = 0x400
28};
29
30#define OP_MASK 0x3f
31#define OP_SH 26
32#define RD_MASK 0x1f
33#define RD_SH 11
34#define RE_MASK 0x1f
35#define RE_SH 6
36#define IMM_MASK 0xffff
37#define IMM_SH 0
38#define JIMM_MASK 0x3ffffff
39#define JIMM_SH 0
40#define FUNC_MASK 0x3f
41#define FUNC_SH 0
42#define SET_MASK 0x7
43#define SET_SH 0
44
45enum opcode {
46 insn_invalid,
47 insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
48 insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
49 insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
50 insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
51 insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
52 insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ldx,
53 insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0,
54 insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,
55 insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
56 insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor,
57 insn_xori,
58};
59
60struct insn {
61 enum opcode opcode;
62 u32 match;
63 enum fields fields;
64};
65
66static inline u32 build_rs(u32 arg)
67{
68 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
69
70 return (arg & RS_MASK) << RS_SH;
71}
72
73static inline u32 build_rt(u32 arg)
74{
75 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
76
77 return (arg & RT_MASK) << RT_SH;
78}
79
80static inline u32 build_rd(u32 arg)
81{
82 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
83
84 return (arg & RD_MASK) << RD_SH;
85}
86
87static inline u32 build_re(u32 arg)
88{
89 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
90
91 return (arg & RE_MASK) << RE_SH;
92}
93
94static inline u32 build_simm(s32 arg)
95{
96 WARN(arg > 0x7fff || arg < -0x8000,
97 KERN_WARNING "Micro-assembler field overflow\n");
98
99 return arg & 0xffff;
100}
101
102static inline u32 build_uimm(u32 arg)
103{
104 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
105
106 return arg & IMM_MASK;
107}
108
109static inline u32 build_scimm(u32 arg)
110{
111 WARN(arg & ~SCIMM_MASK,
112 KERN_WARNING "Micro-assembler field overflow\n");
113
114 return (arg & SCIMM_MASK) << SCIMM_SH;
115}
116
117static inline u32 build_func(u32 arg)
118{
119 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
120
121 return arg & FUNC_MASK;
122}
123
124static inline u32 build_set(u32 arg)
125{
126 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
127
128 return arg & SET_MASK;
129}
130
131static void build_insn(u32 **buf, enum opcode opc, ...);
132
133#define I_u1u2u3(op) \
134Ip_u1u2u3(op) \
135{ \
136 build_insn(buf, insn##op, a, b, c); \
137} \
138UASM_EXPORT_SYMBOL(uasm_i##op);
139
140#define I_u2u1u3(op) \
141Ip_u2u1u3(op) \
142{ \
143 build_insn(buf, insn##op, b, a, c); \
144} \
145UASM_EXPORT_SYMBOL(uasm_i##op);
146
147#define I_u3u1u2(op) \
148Ip_u3u1u2(op) \
149{ \
150 build_insn(buf, insn##op, b, c, a); \
151} \
152UASM_EXPORT_SYMBOL(uasm_i##op);
153
154#define I_u1u2s3(op) \
155Ip_u1u2s3(op) \
156{ \
157 build_insn(buf, insn##op, a, b, c); \
158} \
159UASM_EXPORT_SYMBOL(uasm_i##op);
160
161#define I_u2s3u1(op) \
162Ip_u2s3u1(op) \
163{ \
164 build_insn(buf, insn##op, c, a, b); \
165} \
166UASM_EXPORT_SYMBOL(uasm_i##op);
167
168#define I_u2u1s3(op) \
169Ip_u2u1s3(op) \
170{ \
171 build_insn(buf, insn##op, b, a, c); \
172} \
173UASM_EXPORT_SYMBOL(uasm_i##op);
174
175#define I_u2u1msbu3(op) \
176Ip_u2u1msbu3(op) \
177{ \
178 build_insn(buf, insn##op, b, a, c+d-1, c); \
179} \
180UASM_EXPORT_SYMBOL(uasm_i##op);
181
182#define I_u2u1msb32u3(op) \
183Ip_u2u1msbu3(op) \
184{ \
185 build_insn(buf, insn##op, b, a, c+d-33, c); \
186} \
187UASM_EXPORT_SYMBOL(uasm_i##op);
188
189#define I_u2u1msbdu3(op) \
190Ip_u2u1msbu3(op) \
191{ \
192 build_insn(buf, insn##op, b, a, d-1, c); \
193} \
194UASM_EXPORT_SYMBOL(uasm_i##op);
195
196#define I_u1u2(op) \
197Ip_u1u2(op) \
198{ \
199 build_insn(buf, insn##op, a, b); \
200} \
201UASM_EXPORT_SYMBOL(uasm_i##op);
202
203#define I_u1s2(op) \
204Ip_u1s2(op) \
205{ \
206 build_insn(buf, insn##op, a, b); \
207} \
208UASM_EXPORT_SYMBOL(uasm_i##op);
209
210#define I_u1(op) \
211Ip_u1(op) \
212{ \
213 build_insn(buf, insn##op, a); \
214} \
215UASM_EXPORT_SYMBOL(uasm_i##op);
216
217#define I_0(op) \
218Ip_0(op) \
219{ \
220 build_insn(buf, insn##op); \
221} \
222UASM_EXPORT_SYMBOL(uasm_i##op);
223
224I_u2u1s3(_addiu)
225I_u3u1u2(_addu)
226I_u2u1u3(_andi)
227I_u3u1u2(_and)
228I_u1u2s3(_beq)
229I_u1u2s3(_beql)
230I_u1s2(_bgez)
231I_u1s2(_bgezl)
232I_u1s2(_bltz)
233I_u1s2(_bltzl)
234I_u1u2s3(_bne)
235I_u2s3u1(_cache)
236I_u1u2u3(_dmfc0)
237I_u1u2u3(_dmtc0)
238I_u2u1s3(_daddiu)
239I_u3u1u2(_daddu)
240I_u2u1u3(_dsll)
241I_u2u1u3(_dsll32)
242I_u2u1u3(_dsra)
243I_u2u1u3(_dsrl)
244I_u2u1u3(_dsrl32)
245I_u2u1u3(_drotr)
246I_u2u1u3(_drotr32)
247I_u3u1u2(_dsubu)
248I_0(_eret)
249I_u2u1msbdu3(_ext)
250I_u2u1msbu3(_ins)
251I_u1(_j)
252I_u1(_jal)
253I_u1(_jr)
254I_u2s3u1(_ld)
255I_u2s3u1(_ll)
256I_u2s3u1(_lld)
257I_u1s2(_lui)
258I_u2s3u1(_lw)
259I_u1u2u3(_mfc0)
260I_u1u2u3(_mtc0)
261I_u2u1u3(_ori)
262I_u3u1u2(_or)
263I_0(_rfe)
264I_u2s3u1(_sc)
265I_u2s3u1(_scd)
266I_u2s3u1(_sd)
267I_u2u1u3(_sll)
268I_u2u1u3(_sra)
269I_u2u1u3(_srl)
270I_u2u1u3(_rotr)
271I_u3u1u2(_subu)
272I_u2s3u1(_sw)
273I_0(_tlbp)
274I_0(_tlbr)
275I_0(_tlbwi)
276I_0(_tlbwr)
277I_u3u1u2(_xor)
278I_u2u1u3(_xori)
279I_u2u1msbu3(_dins);
280I_u2u1msb32u3(_dinsm);
281I_u1(_syscall);
282I_u1u2s3(_bbit0);
283I_u1u2s3(_bbit1);
284I_u3u1u2(_lwx)
285I_u3u1u2(_ldx)
286
287#ifdef CONFIG_CPU_CAVIUM_OCTEON
288#include <asm/octeon/octeon.h>
289void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
290 unsigned int c)
291{
292 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
293 /*
294 * As per erratum Core-14449, replace prefetches 0-4,
295 * 6-24 with 'pref 28'.
296 */
297 build_insn(buf, insn_pref, c, 28, b);
298 else
299 build_insn(buf, insn_pref, c, a, b);
300}
301UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
302#else
303I_u2s3u1(_pref)
304#endif
305
306/* Handle labels. */
307void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid)
308{
309 (*lab)->addr = addr;
310 (*lab)->lab = lid;
311 (*lab)++;
312}
313UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));
314
315int ISAFUNC(uasm_in_compat_space_p)(long addr)
316{
317 /* Is this address in 32bit compat space? */
318#ifdef CONFIG_64BIT
319 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
320#else
321 return 1;
322#endif
323}
324UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));
325
326static int uasm_rel_highest(long val)
327{
328#ifdef CONFIG_64BIT
329 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
330#else
331 return 0;
332#endif
333}
334
335static int uasm_rel_higher(long val)
336{
337#ifdef CONFIG_64BIT
338 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
339#else
340 return 0;
341#endif
342}
343
344int ISAFUNC(uasm_rel_hi)(long val)
345{
346 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
347}
348UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));
349
350int ISAFUNC(uasm_rel_lo)(long val)
351{
352 return ((val & 0xffff) ^ 0x8000) - 0x8000;
353}
354UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));
355
356void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
357{
358 if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
359 ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
360 if (uasm_rel_higher(addr))
361 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
362 if (ISAFUNC(uasm_rel_hi(addr))) {
363 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
364 ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
365 ISAFUNC(uasm_rel_hi)(addr));
366 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
367 } else
368 ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
369 } else
370 ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
371}
372UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));
373
374void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
375{
376 ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
377 if (ISAFUNC(uasm_rel_lo(addr))) {
378 if (!ISAFUNC(uasm_in_compat_space_p)(addr))
379 ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
380 ISAFUNC(uasm_rel_lo(addr)));
381 else
382 ISAFUNC(uasm_i_addiu)(buf, rs, rs,
383 ISAFUNC(uasm_rel_lo(addr)));
384 }
385}
386UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));
387
388/* Handle relocations. */
389void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
390{
391 (*rel)->addr = addr;
392 (*rel)->type = R_MIPS_PC16;
393 (*rel)->lab = lid;
394 (*rel)++;
395}
396UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));
397
398static inline void __resolve_relocs(struct uasm_reloc *rel,
399 struct uasm_label *lab);
400
401void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
402 struct uasm_label *lab)
403{
404 struct uasm_label *l;
405
406 for (; rel->lab != UASM_LABEL_INVALID; rel++)
407 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
408 if (rel->lab == l->lab)
409 __resolve_relocs(rel, l);
410}
411UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));
412
413void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end,
414 long off)
415{
416 for (; rel->lab != UASM_LABEL_INVALID; rel++)
417 if (rel->addr >= first && rel->addr < end)
418 rel->addr += off;
419}
420UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));
421
422void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end,
423 long off)
424{
425 for (; lab->lab != UASM_LABEL_INVALID; lab++)
426 if (lab->addr >= first && lab->addr < end)
427 lab->addr += off;
428}
429UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));
430
431void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab,
432 u32 *first, u32 *end, u32 *target)
433{
434 long off = (long)(target - first);
435
436 memcpy(target, first, (end - first) * sizeof(u32));
437
438 ISAFUNC(uasm_move_relocs(rel, first, end, off));
439 ISAFUNC(uasm_move_labels(lab, first, end, off));
440}
441UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));
442
443int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
444{
445 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
446 if (rel->addr == addr
447 && (rel->type == R_MIPS_PC16
448 || rel->type == R_MIPS_26))
449 return 1;
450 }
451
452 return 0;
453}
454UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));
455
456/* Convenience functions for labeled branches. */
457void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
458 int lid)
459{
460 uasm_r_mips_pc16(r, *p, lid);
461 ISAFUNC(uasm_i_bltz)(p, reg, 0);
462}
463UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));
464
465void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
466{
467 uasm_r_mips_pc16(r, *p, lid);
468 ISAFUNC(uasm_i_b)(p, 0);
469}
470UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
471
472void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
473 int lid)
474{
475 uasm_r_mips_pc16(r, *p, lid);
476 ISAFUNC(uasm_i_beqz)(p, reg, 0);
477}
478UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));
479
480void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
481 int lid)
482{
483 uasm_r_mips_pc16(r, *p, lid);
484 ISAFUNC(uasm_i_beqzl)(p, reg, 0);
485}
486UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));
487
488void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1,
489 unsigned int reg2, int lid)
490{
491 uasm_r_mips_pc16(r, *p, lid);
492 ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
493}
494UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));
495
496void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
497 int lid)
498{
499 uasm_r_mips_pc16(r, *p, lid);
500 ISAFUNC(uasm_i_bnez)(p, reg, 0);
501}
502UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));
503
504void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
505 int lid)
506{
507 uasm_r_mips_pc16(r, *p, lid);
508 ISAFUNC(uasm_i_bgezl)(p, reg, 0);
509}
510UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));
511
512void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
513 int lid)
514{
515 uasm_r_mips_pc16(r, *p, lid);
516 ISAFUNC(uasm_i_bgez)(p, reg, 0);
517}
518UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));
519
520void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg,
521 unsigned int bit, int lid)
522{
523 uasm_r_mips_pc16(r, *p, lid);
524 ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
525}
526UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));
527
528void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg,
529 unsigned int bit, int lid)
530{
531 uasm_r_mips_pc16(r, *p, lid);
532 ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
533}
534UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
9 *
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
14 */
15
16enum fields {
17 RS = 0x001,
18 RT = 0x002,
19 RD = 0x004,
20 RE = 0x008,
21 SIMM = 0x010,
22 UIMM = 0x020,
23 BIMM = 0x040,
24 JIMM = 0x080,
25 FUNC = 0x100,
26 SET = 0x200,
27 SCIMM = 0x400,
28 SIMM9 = 0x800,
29};
30
31#define OP_MASK 0x3f
32#define OP_SH 26
33#define RD_MASK 0x1f
34#define RD_SH 11
35#define RE_MASK 0x1f
36#define RE_SH 6
37#define IMM_MASK 0xffff
38#define IMM_SH 0
39#define JIMM_MASK 0x3ffffff
40#define JIMM_SH 0
41#define FUNC_MASK 0x3f
42#define FUNC_SH 0
43#define SET_MASK 0x7
44#define SET_SH 0
45#define SIMM9_SH 7
46#define SIMM9_MASK 0x1ff
47
48enum opcode {
49 insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
50 insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez,
51 insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1,
52 insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu,
53 insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu, insn_dmfc0,
54 insn_dmtc0, insn_dmultu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd,
55 insn_dsll, insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav,
56 insn_dsrl, insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext,
57 insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu,
58 insn_ld, insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu,
59 insn_ll, insn_lld, insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0,
60 insn_mfhc0, insn_mfhi, insn_mflo, insn_movn, insn_movz, insn_mtc0,
61 insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_nor,
62 insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb,
63 insn_sc, insn_scd, insn_sd, insn_sh, insn_sll, insn_sllv,
64 insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srl,
65 insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp,
66 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor,
67 insn_xori, insn_yield,
68 insn_invalid /* insn_invalid must be last */
69};
70
71struct insn {
72 u32 match;
73 enum fields fields;
74};
75
76static inline u32 build_rs(u32 arg)
77{
78 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
79
80 return (arg & RS_MASK) << RS_SH;
81}
82
83static inline u32 build_rt(u32 arg)
84{
85 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
86
87 return (arg & RT_MASK) << RT_SH;
88}
89
90static inline u32 build_rd(u32 arg)
91{
92 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
93
94 return (arg & RD_MASK) << RD_SH;
95}
96
97static inline u32 build_re(u32 arg)
98{
99 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
100
101 return (arg & RE_MASK) << RE_SH;
102}
103
104static inline u32 build_simm(s32 arg)
105{
106 WARN(arg > 0x7fff || arg < -0x8000,
107 KERN_WARNING "Micro-assembler field overflow\n");
108
109 return arg & 0xffff;
110}
111
112static inline u32 build_uimm(u32 arg)
113{
114 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
115
116 return arg & IMM_MASK;
117}
118
119static inline u32 build_scimm(u32 arg)
120{
121 WARN(arg & ~SCIMM_MASK,
122 KERN_WARNING "Micro-assembler field overflow\n");
123
124 return (arg & SCIMM_MASK) << SCIMM_SH;
125}
126
127static inline u32 build_scimm9(s32 arg)
128{
129 WARN((arg > 0xff || arg < -0x100),
130 KERN_WARNING "Micro-assembler field overflow\n");
131
132 return (arg & SIMM9_MASK) << SIMM9_SH;
133}
134
135static inline u32 build_func(u32 arg)
136{
137 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
138
139 return arg & FUNC_MASK;
140}
141
142static inline u32 build_set(u32 arg)
143{
144 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
145
146 return arg & SET_MASK;
147}
148
149static void build_insn(u32 **buf, enum opcode opc, ...);
150
151#define I_u1u2u3(op) \
152Ip_u1u2u3(op) \
153{ \
154 build_insn(buf, insn##op, a, b, c); \
155} \
156UASM_EXPORT_SYMBOL(uasm_i##op);
157
158#define I_s3s1s2(op) \
159Ip_s3s1s2(op) \
160{ \
161 build_insn(buf, insn##op, b, c, a); \
162} \
163UASM_EXPORT_SYMBOL(uasm_i##op);
164
165#define I_u2u1u3(op) \
166Ip_u2u1u3(op) \
167{ \
168 build_insn(buf, insn##op, b, a, c); \
169} \
170UASM_EXPORT_SYMBOL(uasm_i##op);
171
172#define I_u3u2u1(op) \
173Ip_u3u2u1(op) \
174{ \
175 build_insn(buf, insn##op, c, b, a); \
176} \
177UASM_EXPORT_SYMBOL(uasm_i##op);
178
179#define I_u3u1u2(op) \
180Ip_u3u1u2(op) \
181{ \
182 build_insn(buf, insn##op, b, c, a); \
183} \
184UASM_EXPORT_SYMBOL(uasm_i##op);
185
186#define I_u1u2s3(op) \
187Ip_u1u2s3(op) \
188{ \
189 build_insn(buf, insn##op, a, b, c); \
190} \
191UASM_EXPORT_SYMBOL(uasm_i##op);
192
193#define I_u2s3u1(op) \
194Ip_u2s3u1(op) \
195{ \
196 build_insn(buf, insn##op, c, a, b); \
197} \
198UASM_EXPORT_SYMBOL(uasm_i##op);
199
200#define I_u2u1s3(op) \
201Ip_u2u1s3(op) \
202{ \
203 build_insn(buf, insn##op, b, a, c); \
204} \
205UASM_EXPORT_SYMBOL(uasm_i##op);
206
207#define I_u2u1msbu3(op) \
208Ip_u2u1msbu3(op) \
209{ \
210 build_insn(buf, insn##op, b, a, c+d-1, c); \
211} \
212UASM_EXPORT_SYMBOL(uasm_i##op);
213
214#define I_u2u1msb32u3(op) \
215Ip_u2u1msbu3(op) \
216{ \
217 build_insn(buf, insn##op, b, a, c+d-33, c); \
218} \
219UASM_EXPORT_SYMBOL(uasm_i##op);
220
221#define I_u2u1msb32msb3(op) \
222Ip_u2u1msbu3(op) \
223{ \
224 build_insn(buf, insn##op, b, a, c+d-33, c-32); \
225} \
226UASM_EXPORT_SYMBOL(uasm_i##op);
227
228#define I_u2u1msbdu3(op) \
229Ip_u2u1msbu3(op) \
230{ \
231 build_insn(buf, insn##op, b, a, d-1, c); \
232} \
233UASM_EXPORT_SYMBOL(uasm_i##op);
234
235#define I_u1u2(op) \
236Ip_u1u2(op) \
237{ \
238 build_insn(buf, insn##op, a, b); \
239} \
240UASM_EXPORT_SYMBOL(uasm_i##op);
241
242#define I_u2u1(op) \
243Ip_u1u2(op) \
244{ \
245 build_insn(buf, insn##op, b, a); \
246} \
247UASM_EXPORT_SYMBOL(uasm_i##op);
248
249#define I_u1s2(op) \
250Ip_u1s2(op) \
251{ \
252 build_insn(buf, insn##op, a, b); \
253} \
254UASM_EXPORT_SYMBOL(uasm_i##op);
255
256#define I_u1(op) \
257Ip_u1(op) \
258{ \
259 build_insn(buf, insn##op, a); \
260} \
261UASM_EXPORT_SYMBOL(uasm_i##op);
262
263#define I_0(op) \
264Ip_0(op) \
265{ \
266 build_insn(buf, insn##op); \
267} \
268UASM_EXPORT_SYMBOL(uasm_i##op);
269
270I_u2u1s3(_addiu)
271I_u3u1u2(_addu)
272I_u2u1u3(_andi)
273I_u3u1u2(_and)
274I_u1u2s3(_beq)
275I_u1u2s3(_beql)
276I_u1s2(_bgez)
277I_u1s2(_bgezl)
278I_u1s2(_bgtz)
279I_u1s2(_blez)
280I_u1s2(_bltz)
281I_u1s2(_bltzl)
282I_u1u2s3(_bne)
283I_u1(_break)
284I_u2s3u1(_cache)
285I_u1u2(_cfc1)
286I_u2u1(_cfcmsa)
287I_u1u2(_ctc1)
288I_u2u1(_ctcmsa)
289I_u1u2(_ddivu)
290I_u1u2u3(_dmfc0)
291I_u1u2u3(_dmtc0)
292I_u1u2(_dmultu)
293I_u2u1s3(_daddiu)
294I_u3u1u2(_daddu)
295I_u1(_di);
296I_u1u2(_divu)
297I_u2u1(_dsbh);
298I_u2u1(_dshd);
299I_u2u1u3(_dsll)
300I_u2u1u3(_dsll32)
301I_u3u2u1(_dsllv)
302I_u2u1u3(_dsra)
303I_u2u1u3(_dsra32)
304I_u3u2u1(_dsrav)
305I_u2u1u3(_dsrl)
306I_u2u1u3(_dsrl32)
307I_u3u2u1(_dsrlv)
308I_u2u1u3(_drotr)
309I_u2u1u3(_drotr32)
310I_u3u1u2(_dsubu)
311I_0(_eret)
312I_u2u1msbdu3(_ext)
313I_u2u1msbu3(_ins)
314I_u1(_j)
315I_u1(_jal)
316I_u2u1(_jalr)
317I_u1(_jr)
318I_u2s3u1(_lb)
319I_u2s3u1(_lbu)
320I_u2s3u1(_ld)
321I_u2s3u1(_lh)
322I_u2s3u1(_lhu)
323I_u2s3u1(_ll)
324I_u2s3u1(_lld)
325I_u1s2(_lui)
326I_u2s3u1(_lw)
327I_u2s3u1(_lwu)
328I_u1u2u3(_mfc0)
329I_u1u2u3(_mfhc0)
330I_u3u1u2(_movn)
331I_u3u1u2(_movz)
332I_u1(_mfhi)
333I_u1(_mflo)
334I_u1u2u3(_mtc0)
335I_u1u2u3(_mthc0)
336I_u1(_mthi)
337I_u1(_mtlo)
338I_u3u1u2(_mul)
339I_u1u2(_multu)
340I_u3u1u2(_nor)
341I_u3u1u2(_or)
342I_u2u1u3(_ori)
343I_0(_rfe)
344I_u2s3u1(_sb)
345I_u2s3u1(_sc)
346I_u2s3u1(_scd)
347I_u2s3u1(_sd)
348I_u2s3u1(_sh)
349I_u2u1u3(_sll)
350I_u3u2u1(_sllv)
351I_s3s1s2(_slt)
352I_u2u1s3(_slti)
353I_u2u1s3(_sltiu)
354I_u3u1u2(_sltu)
355I_u2u1u3(_sra)
356I_u2u1u3(_srl)
357I_u3u2u1(_srlv)
358I_u2u1u3(_rotr)
359I_u3u1u2(_subu)
360I_u2s3u1(_sw)
361I_u1(_sync)
362I_0(_tlbp)
363I_0(_tlbr)
364I_0(_tlbwi)
365I_0(_tlbwr)
366I_u1(_wait);
367I_u2u1(_wsbh)
368I_u3u1u2(_xor)
369I_u2u1u3(_xori)
370I_u2u1(_yield)
371I_u2u1msbu3(_dins);
372I_u2u1msb32u3(_dinsm);
373I_u2u1msb32msb3(_dinsu);
374I_u1(_syscall);
375I_u1u2s3(_bbit0);
376I_u1u2s3(_bbit1);
377I_u3u1u2(_lwx)
378I_u3u1u2(_ldx)
379I_u1u2(_ldpte)
380I_u2u1u3(_lddir)
381
382#ifdef CONFIG_CPU_CAVIUM_OCTEON
383#include <asm/octeon/octeon.h>
384void uasm_i_pref(u32 **buf, unsigned int a, signed int b,
385 unsigned int c)
386{
387 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5)
388 /*
389 * As per erratum Core-14449, replace prefetches 0-4,
390 * 6-24 with 'pref 28'.
391 */
392 build_insn(buf, insn_pref, c, 28, b);
393 else
394 build_insn(buf, insn_pref, c, a, b);
395}
396UASM_EXPORT_SYMBOL(uasm_i_pref);
397#else
398I_u2s3u1(_pref)
399#endif
400
401/* Handle labels. */
402void uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
403{
404 (*lab)->addr = addr;
405 (*lab)->lab = lid;
406 (*lab)++;
407}
408UASM_EXPORT_SYMBOL(uasm_build_label);
409
410int uasm_in_compat_space_p(long addr)
411{
412 /* Is this address in 32bit compat space? */
413 return addr == (int)addr;
414}
415UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
416
417static int uasm_rel_highest(long val)
418{
419#ifdef CONFIG_64BIT
420 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
421#else
422 return 0;
423#endif
424}
425
426static int uasm_rel_higher(long val)
427{
428#ifdef CONFIG_64BIT
429 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
430#else
431 return 0;
432#endif
433}
434
435int uasm_rel_hi(long val)
436{
437 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
438}
439UASM_EXPORT_SYMBOL(uasm_rel_hi);
440
441int uasm_rel_lo(long val)
442{
443 return ((val & 0xffff) ^ 0x8000) - 0x8000;
444}
445UASM_EXPORT_SYMBOL(uasm_rel_lo);
446
447void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
448{
449 if (!uasm_in_compat_space_p(addr)) {
450 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
451 if (uasm_rel_higher(addr))
452 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
453 if (uasm_rel_hi(addr)) {
454 uasm_i_dsll(buf, rs, rs, 16);
455 uasm_i_daddiu(buf, rs, rs,
456 uasm_rel_hi(addr));
457 uasm_i_dsll(buf, rs, rs, 16);
458 } else
459 uasm_i_dsll32(buf, rs, rs, 0);
460 } else
461 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
462}
463UASM_EXPORT_SYMBOL(UASM_i_LA_mostly);
464
465void UASM_i_LA(u32 **buf, unsigned int rs, long addr)
466{
467 UASM_i_LA_mostly(buf, rs, addr);
468 if (uasm_rel_lo(addr)) {
469 if (!uasm_in_compat_space_p(addr))
470 uasm_i_daddiu(buf, rs, rs,
471 uasm_rel_lo(addr));
472 else
473 uasm_i_addiu(buf, rs, rs,
474 uasm_rel_lo(addr));
475 }
476}
477UASM_EXPORT_SYMBOL(UASM_i_LA);
478
479/* Handle relocations. */
480void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
481{
482 (*rel)->addr = addr;
483 (*rel)->type = R_MIPS_PC16;
484 (*rel)->lab = lid;
485 (*rel)++;
486}
487UASM_EXPORT_SYMBOL(uasm_r_mips_pc16);
488
489static inline void __resolve_relocs(struct uasm_reloc *rel,
490 struct uasm_label *lab);
491
492void uasm_resolve_relocs(struct uasm_reloc *rel,
493 struct uasm_label *lab)
494{
495 struct uasm_label *l;
496
497 for (; rel->lab != UASM_LABEL_INVALID; rel++)
498 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
499 if (rel->lab == l->lab)
500 __resolve_relocs(rel, l);
501}
502UASM_EXPORT_SYMBOL(uasm_resolve_relocs);
503
504void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end,
505 long off)
506{
507 for (; rel->lab != UASM_LABEL_INVALID; rel++)
508 if (rel->addr >= first && rel->addr < end)
509 rel->addr += off;
510}
511UASM_EXPORT_SYMBOL(uasm_move_relocs);
512
513void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end,
514 long off)
515{
516 for (; lab->lab != UASM_LABEL_INVALID; lab++)
517 if (lab->addr >= first && lab->addr < end)
518 lab->addr += off;
519}
520UASM_EXPORT_SYMBOL(uasm_move_labels);
521
522void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
523 u32 *first, u32 *end, u32 *target)
524{
525 long off = (long)(target - first);
526
527 memcpy(target, first, (end - first) * sizeof(u32));
528
529 uasm_move_relocs(rel, first, end, off);
530 uasm_move_labels(lab, first, end, off);
531}
532UASM_EXPORT_SYMBOL(uasm_copy_handler);
533
534int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
535{
536 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
537 if (rel->addr == addr
538 && (rel->type == R_MIPS_PC16
539 || rel->type == R_MIPS_26))
540 return 1;
541 }
542
543 return 0;
544}
545UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay);
546
547/* Convenience functions for labeled branches. */
548void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg,
549 int lid)
550{
551 uasm_r_mips_pc16(r, *p, lid);
552 uasm_i_bltz(p, reg, 0);
553}
554UASM_EXPORT_SYMBOL(uasm_il_bltz);
555
556void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
557{
558 uasm_r_mips_pc16(r, *p, lid);
559 uasm_i_b(p, 0);
560}
561UASM_EXPORT_SYMBOL(uasm_il_b);
562
563void uasm_il_beq(u32 **p, struct uasm_reloc **r, unsigned int r1,
564 unsigned int r2, int lid)
565{
566 uasm_r_mips_pc16(r, *p, lid);
567 uasm_i_beq(p, r1, r2, 0);
568}
569UASM_EXPORT_SYMBOL(uasm_il_beq);
570
571void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg,
572 int lid)
573{
574 uasm_r_mips_pc16(r, *p, lid);
575 uasm_i_beqz(p, reg, 0);
576}
577UASM_EXPORT_SYMBOL(uasm_il_beqz);
578
579void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg,
580 int lid)
581{
582 uasm_r_mips_pc16(r, *p, lid);
583 uasm_i_beqzl(p, reg, 0);
584}
585UASM_EXPORT_SYMBOL(uasm_il_beqzl);
586
587void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
588 unsigned int reg2, int lid)
589{
590 uasm_r_mips_pc16(r, *p, lid);
591 uasm_i_bne(p, reg1, reg2, 0);
592}
593UASM_EXPORT_SYMBOL(uasm_il_bne);
594
595void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg,
596 int lid)
597{
598 uasm_r_mips_pc16(r, *p, lid);
599 uasm_i_bnez(p, reg, 0);
600}
601UASM_EXPORT_SYMBOL(uasm_il_bnez);
602
603void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg,
604 int lid)
605{
606 uasm_r_mips_pc16(r, *p, lid);
607 uasm_i_bgezl(p, reg, 0);
608}
609UASM_EXPORT_SYMBOL(uasm_il_bgezl);
610
611void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg,
612 int lid)
613{
614 uasm_r_mips_pc16(r, *p, lid);
615 uasm_i_bgez(p, reg, 0);
616}
617UASM_EXPORT_SYMBOL(uasm_il_bgez);
618
619void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
620 unsigned int bit, int lid)
621{
622 uasm_r_mips_pc16(r, *p, lid);
623 uasm_i_bbit0(p, reg, bit, 0);
624}
625UASM_EXPORT_SYMBOL(uasm_il_bbit0);
626
627void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
628 unsigned int bit, int lid)
629{
630 uasm_r_mips_pc16(r, *p, lid);
631 uasm_i_bbit1(p, reg, bit, 0);
632}
633UASM_EXPORT_SYMBOL(uasm_il_bbit1);