1/*
  2 *  This program is free software; you can redistribute it and/or modify it
  3 *  under the terms of the GNU General Public License version 2 as published
  4 *  by the Free Software Foundation.
  5 *
  6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  7 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
  8 */
  9
 10#include <linux/interrupt.h>
 11#include <linux/ioport.h>
 12#include <linux/sched.h>
 13#include <linux/irqdomain.h>
 14#include <linux/of_platform.h>
 15#include <linux/of_address.h>
 16#include <linux/of_irq.h>
 17
 18#include <asm/bootinfo.h>
 19#include <asm/irq_cpu.h>
 20
 21#include <lantiq_soc.h>
 22#include <irq.h>
 23
 24/* register definitions - internal irqs */
 25#define LTQ_ICU_IM0_ISR		0x0000
 26#define LTQ_ICU_IM0_IER		0x0008
 27#define LTQ_ICU_IM0_IOSR	0x0010
 28#define LTQ_ICU_IM0_IRSR	0x0018
 29#define LTQ_ICU_IM0_IMR		0x0020
 30#define LTQ_ICU_IM1_ISR		0x0028
 31#define LTQ_ICU_OFFSET		(LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
 32
 33/* register definitions - external irqs */
 34#define LTQ_EIU_EXIN_C		0x0000
 35#define LTQ_EIU_EXIN_INIC	0x0004
 36#define LTQ_EIU_EXIN_INC	0x0008
 37#define LTQ_EIU_EXIN_INEN	0x000C
 38
 39/* number of external interrupts */
 40#define MAX_EIU			6
 41
 42/* the performance counter */
 43#define LTQ_PERF_IRQ		(INT_NUM_IM4_IRL0 + 31)
 44
 45/*
 46 * irqs generated by devices attached to the EBU need to be acked in
 47 * a special manner
 48 */
 49#define LTQ_ICU_EBU_IRQ		22
 50
 51#define ltq_icu_w32(m, x, y)	ltq_w32((x), ltq_icu_membase[m] + (y))
 52#define ltq_icu_r32(m, x)	ltq_r32(ltq_icu_membase[m] + (x))
 53
 54#define ltq_eiu_w32(x, y)	ltq_w32((x), ltq_eiu_membase + (y))
 55#define ltq_eiu_r32(x)		ltq_r32(ltq_eiu_membase + (x))
 56
 57/* our 2 ipi interrupts for VSMP */
 58#define MIPS_CPU_IPI_RESCHED_IRQ	0
 59#define MIPS_CPU_IPI_CALL_IRQ		1
 60
 61/* we have a cascade of 8 irqs */
 62#define MIPS_CPU_IRQ_CASCADE		8
 63
 64#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
 65int gic_present;
 66#endif
 67
 68static int exin_avail;
 69static struct resource ltq_eiu_irq[MAX_EIU];
 70static void __iomem *ltq_icu_membase[MAX_IM];
 71static void __iomem *ltq_eiu_membase;
 72static struct irq_domain *ltq_domain;
 
 73
 74int ltq_eiu_get_irq(int exin)
 75{
 76	if (exin < exin_avail)
 77		return ltq_eiu_irq[exin].start;
 78	return -1;
 79}
 80
 81void ltq_disable_irq(struct irq_data *d)
 82{
 83	u32 ier = LTQ_ICU_IM0_IER;
 84	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
 85	int im = offset / INT_NUM_IM_OFFSET;
 86
 87	offset %= INT_NUM_IM_OFFSET;
 88	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
 89}
 90
 91void ltq_mask_and_ack_irq(struct irq_data *d)
 92{
 93	u32 ier = LTQ_ICU_IM0_IER;
 94	u32 isr = LTQ_ICU_IM0_ISR;
 95	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
 96	int im = offset / INT_NUM_IM_OFFSET;
 97
 98	offset %= INT_NUM_IM_OFFSET;
 99	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
100	ltq_icu_w32(im, BIT(offset), isr);
101}
102
103static void ltq_ack_irq(struct irq_data *d)
104{
105	u32 isr = LTQ_ICU_IM0_ISR;
106	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
107	int im = offset / INT_NUM_IM_OFFSET;
108
109	offset %= INT_NUM_IM_OFFSET;
110	ltq_icu_w32(im, BIT(offset), isr);
111}
112
113void ltq_enable_irq(struct irq_data *d)
114{
115	u32 ier = LTQ_ICU_IM0_IER;
116	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
117	int im = offset / INT_NUM_IM_OFFSET;
118
119	offset %= INT_NUM_IM_OFFSET;
120	ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
121}
122
123static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
124{
125	int i;
126
127	for (i = 0; i < MAX_EIU; i++) {
128		if (d->hwirq == ltq_eiu_irq[i].start) {
129			int val = 0;
130			int edge = 0;
131
132			switch (type) {
133			case IRQF_TRIGGER_NONE:
134				break;
135			case IRQF_TRIGGER_RISING:
136				val = 1;
137				edge = 1;
138				break;
139			case IRQF_TRIGGER_FALLING:
140				val = 2;
141				edge = 1;
142				break;
143			case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
144				val = 3;
145				edge = 1;
146				break;
147			case IRQF_TRIGGER_HIGH:
148				val = 5;
149				break;
150			case IRQF_TRIGGER_LOW:
151				val = 6;
152				break;
153			default:
154				pr_err("invalid type %d for irq %ld\n",
155					type, d->hwirq);
156				return -EINVAL;
157			}
158
159			if (edge)
160				irq_set_handler(d->hwirq, handle_edge_irq);
161
162			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
163				(val << (i * 4)), LTQ_EIU_EXIN_C);
164		}
165	}
166
167	return 0;
168}
169
170static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
171{
172	int i;
173
174	ltq_enable_irq(d);
175	for (i = 0; i < MAX_EIU; i++) {
176		if (d->hwirq == ltq_eiu_irq[i].start) {
177			/* by default we are low level triggered */
178			ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
179			/* clear all pending */
180			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
181				LTQ_EIU_EXIN_INC);
182			/* enable */
183			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
184				LTQ_EIU_EXIN_INEN);
185			break;
186		}
187	}
188
189	return 0;
190}
191
192static void ltq_shutdown_eiu_irq(struct irq_data *d)
193{
194	int i;
195
196	ltq_disable_irq(d);
197	for (i = 0; i < MAX_EIU; i++) {
198		if (d->hwirq == ltq_eiu_irq[i].start) {
199			/* disable */
200			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
201				LTQ_EIU_EXIN_INEN);
202			break;
203		}
204	}
205}
206
207static struct irq_chip ltq_irq_type = {
208	"icu",
209	.irq_enable = ltq_enable_irq,
210	.irq_disable = ltq_disable_irq,
211	.irq_unmask = ltq_enable_irq,
212	.irq_ack = ltq_ack_irq,
213	.irq_mask = ltq_disable_irq,
214	.irq_mask_ack = ltq_mask_and_ack_irq,
215};
216
217static struct irq_chip ltq_eiu_type = {
218	"eiu",
219	.irq_startup = ltq_startup_eiu_irq,
220	.irq_shutdown = ltq_shutdown_eiu_irq,
221	.irq_enable = ltq_enable_irq,
222	.irq_disable = ltq_disable_irq,
223	.irq_unmask = ltq_enable_irq,
224	.irq_ack = ltq_ack_irq,
225	.irq_mask = ltq_disable_irq,
226	.irq_mask_ack = ltq_mask_and_ack_irq,
227	.irq_set_type = ltq_eiu_settype,
228};
229
230static void ltq_hw_irqdispatch(int module)
231{
232	u32 irq;
233
234	irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
235	if (irq == 0)
236		return;
237
238	/*
239	 * silicon bug causes only the msb set to 1 to be valid. all
240	 * other bits might be bogus
241	 */
242	irq = __fls(irq);
243	do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
244
245	/* if this is a EBU irq, we need to ack it or get a deadlock */
246	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
247		ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
248			LTQ_EBU_PCC_ISTAT);
249}
250
251#define DEFINE_HWx_IRQDISPATCH(x)					\
252	static void ltq_hw ## x ## _irqdispatch(void)			\
253	{								\
254		ltq_hw_irqdispatch(x);					\
255	}
256DEFINE_HWx_IRQDISPATCH(0)
257DEFINE_HWx_IRQDISPATCH(1)
258DEFINE_HWx_IRQDISPATCH(2)
259DEFINE_HWx_IRQDISPATCH(3)
260DEFINE_HWx_IRQDISPATCH(4)
261
262#if MIPS_CPU_TIMER_IRQ == 7
263static void ltq_hw5_irqdispatch(void)
264{
265	do_IRQ(MIPS_CPU_TIMER_IRQ);
266}
267#else
268DEFINE_HWx_IRQDISPATCH(5)
269#endif
270
271#ifdef CONFIG_MIPS_MT_SMP
272void __init arch_init_ipiirq(int irq, struct irqaction *action)
273{
274	setup_irq(irq, action);
275	irq_set_handler(irq, handle_percpu_irq);
276}
277
278static void ltq_sw0_irqdispatch(void)
279{
280	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
281}
282
283static void ltq_sw1_irqdispatch(void)
284{
285	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
286}
287static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
288{
289	scheduler_ipi();
290	return IRQ_HANDLED;
291}
292
293static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
294{
295	smp_call_function_interrupt();
296	return IRQ_HANDLED;
297}
298
299static struct irqaction irq_resched = {
300	.handler	= ipi_resched_interrupt,
301	.flags		= IRQF_PERCPU,
302	.name		= "IPI_resched"
303};
304
305static struct irqaction irq_call = {
306	.handler	= ipi_call_interrupt,
307	.flags		= IRQF_PERCPU,
308	.name		= "IPI_call"
309};
310#endif
311
312asmlinkage void plat_irq_dispatch(void)
313{
314	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
315	unsigned int i;
316
317	if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
318		do_IRQ(MIPS_CPU_TIMER_IRQ);
319		goto out;
320	} else {
321		for (i = 0; i < MAX_IM; i++) {
322			if (pending & (CAUSEF_IP2 << i)) {
323				ltq_hw_irqdispatch(i);
324				goto out;
325			}
326		}
327	}
328	pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
329
330out:
331	return;
 
 
 
 
332}
333
334static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
335{
336	struct irq_chip *chip = &ltq_irq_type;
337	int i;
338
339	if (hw < MIPS_CPU_IRQ_CASCADE)
340		return 0;
341
342	for (i = 0; i < exin_avail; i++)
343		if (hw == ltq_eiu_irq[i].start)
344			chip = &ltq_eiu_type;
345
346	irq_set_chip_and_handler(hw, chip, handle_level_irq);
347
348	return 0;
349}
350
351static const struct irq_domain_ops irq_domain_ops = {
352	.xlate = irq_domain_xlate_onetwocell,
353	.map = icu_map,
354};
355
356static struct irqaction cascade = {
357	.handler = no_action,
358	.name = "cascade",
359};
360
361int __init icu_of_init(struct device_node *node, struct device_node *parent)
362{
363	struct device_node *eiu_node;
364	struct resource res;
365	int i, ret;
366
367	for (i = 0; i < MAX_IM; i++) {
368		if (of_address_to_resource(node, i, &res))
369			panic("Failed to get icu memory range");
370
371		if (request_mem_region(res.start, resource_size(&res),
372					res.name) < 0)
373			pr_err("Failed to request icu memory");
374
375		ltq_icu_membase[i] = ioremap_nocache(res.start,
376					resource_size(&res));
377		if (!ltq_icu_membase[i])
378			panic("Failed to remap icu memory");
379	}
380
381	/* the external interrupts are optional and xway only */
382	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
383	if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
384		/* find out how many external irq sources we have */
385		exin_avail = of_irq_count(eiu_node);
386
387		if (exin_avail > MAX_EIU)
388			exin_avail = MAX_EIU;
389
390		ret = of_irq_to_resource_table(eiu_node,
391						ltq_eiu_irq, exin_avail);
392		if (ret != exin_avail)
393			panic("failed to load external irq resources");
394
395		if (request_mem_region(res.start, resource_size(&res),
396							res.name) < 0)
397			pr_err("Failed to request eiu memory");
398
399		ltq_eiu_membase = ioremap_nocache(res.start,
400							resource_size(&res));
401		if (!ltq_eiu_membase)
402			panic("Failed to remap eiu memory");
403	}
404
405	/* turn off all irqs by default */
406	for (i = 0; i < MAX_IM; i++) {
407		/* make sure all irqs are turned off by default */
408		ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
409		/* clear all possibly pending interrupts */
410		ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
411	}
412
413	mips_cpu_irq_init();
414
415	for (i = 0; i < MAX_IM; i++)
416		setup_irq(i + 2, &cascade);
417
418	if (cpu_has_vint) {
419		pr_info("Setting up vectored interrupts\n");
420		set_vi_handler(2, ltq_hw0_irqdispatch);
421		set_vi_handler(3, ltq_hw1_irqdispatch);
422		set_vi_handler(4, ltq_hw2_irqdispatch);
423		set_vi_handler(5, ltq_hw3_irqdispatch);
424		set_vi_handler(6, ltq_hw4_irqdispatch);
425		set_vi_handler(7, ltq_hw5_irqdispatch);
426	}
427
428	ltq_domain = irq_domain_add_linear(node,
429		(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
430		&irq_domain_ops, 0);
431
432#if defined(CONFIG_MIPS_MT_SMP)
433	if (cpu_has_vint) {
434		pr_info("Setting up IPI vectored interrupts\n");
435		set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
436		set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
437	}
438	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
439		&irq_resched);
440	arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
441#endif
442
443#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
444	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
445		IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
446#else
447	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
448		IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
449#endif
450
451	/* tell oprofile which irq to use */
452	cp0_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
453
454	/*
455	 * if the timer irq is not one of the mips irqs we need to
456	 * create a mapping
457	 */
458	if (MIPS_CPU_TIMER_IRQ != 7)
459		irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
460
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
461	return 0;
462}
 
 
 
 
 
 
463
464unsigned int get_c0_compare_int(void)
465{
466	return MIPS_CPU_TIMER_IRQ;
467}
468
469static struct of_device_id __initdata of_irq_ids[] = {
470	{ .compatible = "lantiq,icu", .data = icu_of_init },
471	{},
472};
473
474void __init arch_init_irq(void)
475{
476	of_irq_init(of_irq_ids);
477}

  1/*
  2 *  This program is free software; you can redistribute it and/or modify it
  3 *  under the terms of the GNU General Public License version 2 as published
  4 *  by the Free Software Foundation.
  5 *
  6 * Copyright (C) 2010 John Crispin <john@phrozen.org>
  7 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
  8 */
  9
 10#include <linux/interrupt.h>
 11#include <linux/ioport.h>
 12#include <linux/sched.h>
 13#include <linux/irqdomain.h>
 14#include <linux/of_platform.h>
 15#include <linux/of_address.h>
 16#include <linux/of_irq.h>
 17
 18#include <asm/bootinfo.h>
 19#include <asm/irq_cpu.h>
 20
 21#include <lantiq_soc.h>
 22#include <irq.h>
 23
 24/* register definitions - internal irqs */
 25#define LTQ_ICU_IM0_ISR		0x0000
 26#define LTQ_ICU_IM0_IER		0x0008
 27#define LTQ_ICU_IM0_IOSR	0x0010
 28#define LTQ_ICU_IM0_IRSR	0x0018
 29#define LTQ_ICU_IM0_IMR		0x0020
 30#define LTQ_ICU_IM1_ISR		0x0028
 31#define LTQ_ICU_OFFSET		(LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
 32
 33/* register definitions - external irqs */
 34#define LTQ_EIU_EXIN_C		0x0000
 35#define LTQ_EIU_EXIN_INIC	0x0004
 36#define LTQ_EIU_EXIN_INC	0x0008
 37#define LTQ_EIU_EXIN_INEN	0x000C
 38
 39/* number of external interrupts */
 40#define MAX_EIU			6
 41
 42/* the performance counter */
 43#define LTQ_PERF_IRQ		(INT_NUM_IM4_IRL0 + 31)
 44
 45/*
 46 * irqs generated by devices attached to the EBU need to be acked in
 47 * a special manner
 48 */
 49#define LTQ_ICU_EBU_IRQ		22
 50
 51#define ltq_icu_w32(m, x, y)	ltq_w32((x), ltq_icu_membase[m] + (y))
 52#define ltq_icu_r32(m, x)	ltq_r32(ltq_icu_membase[m] + (x))
 53
 54#define ltq_eiu_w32(x, y)	ltq_w32((x), ltq_eiu_membase + (y))
 55#define ltq_eiu_r32(x)		ltq_r32(ltq_eiu_membase + (x))
 56
 57/* our 2 ipi interrupts for VSMP */
 58#define MIPS_CPU_IPI_RESCHED_IRQ	0
 59#define MIPS_CPU_IPI_CALL_IRQ		1
 60
 61/* we have a cascade of 8 irqs */
 62#define MIPS_CPU_IRQ_CASCADE		8
 63
 
 
 
 
 64static int exin_avail;
 65static u32 ltq_eiu_irq[MAX_EIU];
 66static void __iomem *ltq_icu_membase[MAX_IM];
 67static void __iomem *ltq_eiu_membase;
 68static struct irq_domain *ltq_domain;
 69static int ltq_perfcount_irq;
 70
 71int ltq_eiu_get_irq(int exin)
 72{
 73	if (exin < exin_avail)
 74		return ltq_eiu_irq[exin];
 75	return -1;
 76}
 77
 78void ltq_disable_irq(struct irq_data *d)
 79{
 80	u32 ier = LTQ_ICU_IM0_IER;
 81	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
 82	int im = offset / INT_NUM_IM_OFFSET;
 83
 84	offset %= INT_NUM_IM_OFFSET;
 85	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
 86}
 87
 88void ltq_mask_and_ack_irq(struct irq_data *d)
 89{
 90	u32 ier = LTQ_ICU_IM0_IER;
 91	u32 isr = LTQ_ICU_IM0_ISR;
 92	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
 93	int im = offset / INT_NUM_IM_OFFSET;
 94
 95	offset %= INT_NUM_IM_OFFSET;
 96	ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
 97	ltq_icu_w32(im, BIT(offset), isr);
 98}
 99
100static void ltq_ack_irq(struct irq_data *d)
101{
102	u32 isr = LTQ_ICU_IM0_ISR;
103	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
104	int im = offset / INT_NUM_IM_OFFSET;
105
106	offset %= INT_NUM_IM_OFFSET;
107	ltq_icu_w32(im, BIT(offset), isr);
108}
109
110void ltq_enable_irq(struct irq_data *d)
111{
112	u32 ier = LTQ_ICU_IM0_IER;
113	int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
114	int im = offset / INT_NUM_IM_OFFSET;
115
116	offset %= INT_NUM_IM_OFFSET;
117	ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
118}
119
120static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
121{
122	int i;
123
124	for (i = 0; i < exin_avail; i++) {
125		if (d->hwirq == ltq_eiu_irq[i]) {
126			int val = 0;
127			int edge = 0;
128
129			switch (type) {
130			case IRQF_TRIGGER_NONE:
131				break;
132			case IRQF_TRIGGER_RISING:
133				val = 1;
134				edge = 1;
135				break;
136			case IRQF_TRIGGER_FALLING:
137				val = 2;
138				edge = 1;
139				break;
140			case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
141				val = 3;
142				edge = 1;
143				break;
144			case IRQF_TRIGGER_HIGH:
145				val = 5;
146				break;
147			case IRQF_TRIGGER_LOW:
148				val = 6;
149				break;
150			default:
151				pr_err("invalid type %d for irq %ld\n",
152					type, d->hwirq);
153				return -EINVAL;
154			}
155
156			if (edge)
157				irq_set_handler(d->hwirq, handle_edge_irq);
158
159			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
160				(val << (i * 4)), LTQ_EIU_EXIN_C);
161		}
162	}
163
164	return 0;
165}
166
167static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
168{
169	int i;
170
171	ltq_enable_irq(d);
172	for (i = 0; i < exin_avail; i++) {
173		if (d->hwirq == ltq_eiu_irq[i]) {
174			/* by default we are low level triggered */
175			ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
176			/* clear all pending */
177			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
178				LTQ_EIU_EXIN_INC);
179			/* enable */
180			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
181				LTQ_EIU_EXIN_INEN);
182			break;
183		}
184	}
185
186	return 0;
187}
188
189static void ltq_shutdown_eiu_irq(struct irq_data *d)
190{
191	int i;
192
193	ltq_disable_irq(d);
194	for (i = 0; i < exin_avail; i++) {
195		if (d->hwirq == ltq_eiu_irq[i]) {
196			/* disable */
197			ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
198				LTQ_EIU_EXIN_INEN);
199			break;
200		}
201	}
202}
203
204static struct irq_chip ltq_irq_type = {
205	.name = "icu",
206	.irq_enable = ltq_enable_irq,
207	.irq_disable = ltq_disable_irq,
208	.irq_unmask = ltq_enable_irq,
209	.irq_ack = ltq_ack_irq,
210	.irq_mask = ltq_disable_irq,
211	.irq_mask_ack = ltq_mask_and_ack_irq,
212};
213
214static struct irq_chip ltq_eiu_type = {
215	.name = "eiu",
216	.irq_startup = ltq_startup_eiu_irq,
217	.irq_shutdown = ltq_shutdown_eiu_irq,
218	.irq_enable = ltq_enable_irq,
219	.irq_disable = ltq_disable_irq,
220	.irq_unmask = ltq_enable_irq,
221	.irq_ack = ltq_ack_irq,
222	.irq_mask = ltq_disable_irq,
223	.irq_mask_ack = ltq_mask_and_ack_irq,
224	.irq_set_type = ltq_eiu_settype,
225};
226
227static void ltq_hw_irqdispatch(int module)
228{
229	u32 irq;
230
231	irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
232	if (irq == 0)
233		return;
234
235	/*
236	 * silicon bug causes only the msb set to 1 to be valid. all
237	 * other bits might be bogus
238	 */
239	irq = __fls(irq);
240	do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
241
242	/* if this is a EBU irq, we need to ack it or get a deadlock */
243	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
244		ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
245			LTQ_EBU_PCC_ISTAT);
246}
247
248#define DEFINE_HWx_IRQDISPATCH(x)					\
249	static void ltq_hw ## x ## _irqdispatch(void)			\
250	{								\
251		ltq_hw_irqdispatch(x);					\
252	}
253DEFINE_HWx_IRQDISPATCH(0)
254DEFINE_HWx_IRQDISPATCH(1)
255DEFINE_HWx_IRQDISPATCH(2)
256DEFINE_HWx_IRQDISPATCH(3)
257DEFINE_HWx_IRQDISPATCH(4)
258
259#if MIPS_CPU_TIMER_IRQ == 7
260static void ltq_hw5_irqdispatch(void)
261{
262	do_IRQ(MIPS_CPU_TIMER_IRQ);
263}
264#else
265DEFINE_HWx_IRQDISPATCH(5)
266#endif
267
268static void ltq_hw_irq_handler(struct irq_desc *desc)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
269{
270	ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
 
271}
272
 
 
 
 
 
 
 
 
 
 
 
 
 
273asmlinkage void plat_irq_dispatch(void)
274{
275	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
276	int irq;
277
278	if (!pending) {
279		spurious_interrupt();
280		return;
 
 
 
 
 
 
 
281	}
 
282
283	pending >>= CAUSEB_IP;
284	while (pending) {
285		irq = fls(pending) - 1;
286		do_IRQ(MIPS_CPU_IRQ_BASE + irq);
287		pending &= ~BIT(irq);
288	}
289}
290
291static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
292{
293	struct irq_chip *chip = &ltq_irq_type;
294	int i;
295
296	if (hw < MIPS_CPU_IRQ_CASCADE)
297		return 0;
298
299	for (i = 0; i < exin_avail; i++)
300		if (hw == ltq_eiu_irq[i])
301			chip = &ltq_eiu_type;
302
303	irq_set_chip_and_handler(irq, chip, handle_level_irq);
304
305	return 0;
306}
307
308static const struct irq_domain_ops irq_domain_ops = {
309	.xlate = irq_domain_xlate_onetwocell,
310	.map = icu_map,
311};
312
 
 
 
 
 
313int __init icu_of_init(struct device_node *node, struct device_node *parent)
314{
315	struct device_node *eiu_node;
316	struct resource res;
317	int i, ret;
318
319	for (i = 0; i < MAX_IM; i++) {
320		if (of_address_to_resource(node, i, &res))
321			panic("Failed to get icu memory range");
322
323		if (!request_mem_region(res.start, resource_size(&res),
324					res.name))
325			pr_err("Failed to request icu memory");
326
327		ltq_icu_membase[i] = ioremap_nocache(res.start,
328					resource_size(&res));
329		if (!ltq_icu_membase[i])
330			panic("Failed to remap icu memory");
331	}
332
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
333	/* turn off all irqs by default */
334	for (i = 0; i < MAX_IM; i++) {
335		/* make sure all irqs are turned off by default */
336		ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
337		/* clear all possibly pending interrupts */
338		ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
339	}
340
341	mips_cpu_irq_init();
342
343	for (i = 0; i < MAX_IM; i++)
344		irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
345
346	if (cpu_has_vint) {
347		pr_info("Setting up vectored interrupts\n");
348		set_vi_handler(2, ltq_hw0_irqdispatch);
349		set_vi_handler(3, ltq_hw1_irqdispatch);
350		set_vi_handler(4, ltq_hw2_irqdispatch);
351		set_vi_handler(5, ltq_hw3_irqdispatch);
352		set_vi_handler(6, ltq_hw4_irqdispatch);
353		set_vi_handler(7, ltq_hw5_irqdispatch);
354	}
355
356	ltq_domain = irq_domain_add_linear(node,
357		(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
358		&irq_domain_ops, 0);
359
360#ifndef CONFIG_MIPS_MT_SMP
 
 
 
 
 
 
 
 
 
 
 
361	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
362		IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
363#else
364	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
365		IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
366#endif
367
368	/* tell oprofile which irq to use */
369	ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
370
371	/*
372	 * if the timer irq is not one of the mips irqs we need to
373	 * create a mapping
374	 */
375	if (MIPS_CPU_TIMER_IRQ != 7)
376		irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
377
378	/* the external interrupts are optional and xway only */
379	eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
380	if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
381		/* find out how many external irq sources we have */
382		exin_avail = of_property_count_u32_elems(eiu_node,
383							 "lantiq,eiu-irqs");
384
385		if (exin_avail > MAX_EIU)
386			exin_avail = MAX_EIU;
387
388		ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs",
389						ltq_eiu_irq, exin_avail);
390		if (ret)
391			panic("failed to load external irq resources");
392
393		if (!request_mem_region(res.start, resource_size(&res),
394							res.name))
395			pr_err("Failed to request eiu memory");
396
397		ltq_eiu_membase = ioremap_nocache(res.start,
398							resource_size(&res));
399		if (!ltq_eiu_membase)
400			panic("Failed to remap eiu memory");
401	}
402
403	return 0;
404}
405
406int get_c0_perfcount_int(void)
407{
408	return ltq_perfcount_irq;
409}
410EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
411
412unsigned int get_c0_compare_int(void)
413{
414	return MIPS_CPU_TIMER_IRQ;
415}
416
417static struct of_device_id __initdata of_irq_ids[] = {
418	{ .compatible = "lantiq,icu", .data = icu_of_init },
419	{},
420};
421
422void __init arch_init_irq(void)
423{
424	of_irq_init(of_irq_ids);
425}