1/* linux/arch/arm/mach-s3c2416/clock.c
  2 *
  3 * Copyright (c) 2010 Simtec Electronics
  4 * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
  5 *
  6 * S3C2416 Clock control support
  7 *
  8 * This program is free software; you can redistribute it and/or modify
  9 * it under the terms of the GNU General Public License as published by
 10 * the Free Software Foundation; either version 2 of the License, or
 11 * (at your option) any later version.
 12 */
 13
 14#include <linux/init.h>
 15#include <linux/clk.h>
 16
 17#include <plat/clock.h>
 18#include <plat/clock-clksrc.h>
 19#include <plat/cpu.h>
 20
 21#include <plat/cpu-freq.h>
 22#include <plat/pll.h>
 23
 24#include <asm/mach/map.h>
 25
 26#include <mach/regs-clock.h>
 27#include <mach/regs-s3c2443-clock.h>
 28
 29/* armdiv
 30 *
 31 * this clock is sourced from msysclk and can have a number of
 32 * divider values applied to it to then be fed into armclk.
 33 * The real clock definition is done in s3c2443-clock.c,
 34 * only the armdiv divisor table must be defined here.
 35*/
 36
 37static unsigned int armdiv[8] = {
 38	[0] = 1,
 39	[1] = 2,
 40	[2] = 3,
 41	[3] = 4,
 42	[5] = 6,
 43	[7] = 8,
 44};
 45
 46static struct clksrc_clk hsspi_eplldiv = {
 47	.clk = {
 48		.name	= "hsspi-eplldiv",
 49		.parent	= &clk_esysclk.clk,
 50		.ctrlbit = (1 << 14),
 51		.enable = s3c2443_clkcon_enable_s,
 52	},
 53	.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
 54};
 55
 56static struct clk *hsspi_sources[] = {
 57	[0] = &hsspi_eplldiv.clk,
 58	[1] = NULL, /* to fix */
 59};
 60
 61static struct clksrc_clk hsspi_mux = {
 62	.clk	= {
 63		.name	= "hsspi-if",
 64	},
 65	.sources = &(struct clksrc_sources) {
 66		.sources = hsspi_sources,
 67		.nr_sources = ARRAY_SIZE(hsspi_sources),
 68	},
 69	.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
 70};
 71
 72static struct clksrc_clk hsmmc_div[] = {
 73	[0] = {
 74		.clk = {
 75			.name	= "hsmmc-div",
 76			.devname	= "s3c-sdhci.0",
 77			.parent	= &clk_esysclk.clk,
 78		},
 79		.reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
 80	},
 81	[1] = {
 82		.clk = {
 83			.name	= "hsmmc-div",
 84			.devname	= "s3c-sdhci.1",
 85			.parent	= &clk_esysclk.clk,
 86		},
 87		.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
 88	},
 89};
 90
 91static struct clksrc_clk hsmmc_mux0 = {
 92	.clk	= {
 93		.name		= "hsmmc-if",
 94		.devname	= "s3c-sdhci.0",
 95		.ctrlbit	= (1 << 6),
 96		.enable		= s3c2443_clkcon_enable_s,
 97	},
 98	.sources	= &(struct clksrc_sources) {
 99		.nr_sources	= 2,
100		.sources	= (struct clk * []) {
101			[0]	= &hsmmc_div[0].clk,
102			[1]	= NULL, /* to fix */
103		},
104	},
105	.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
106};
107
108static struct clksrc_clk hsmmc_mux1 = {
109	.clk	= {
110		.name		= "hsmmc-if",
111		.devname	= "s3c-sdhci.1",
112		.ctrlbit	= (1 << 12),
113		.enable		= s3c2443_clkcon_enable_s,
114	},
115	.sources	= &(struct clksrc_sources) {
116		.nr_sources	= 2,
117		.sources	= (struct clk * []) {
118			[0]	= &hsmmc_div[1].clk,
119			[1]	= NULL, /* to fix */
120		},
121	},
122	.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
123};
124
125static struct clk hsmmc0_clk = {
126	.name		= "hsmmc",
127	.devname	= "s3c-sdhci.0",
128	.parent		= &clk_h,
129	.enable		= s3c2443_clkcon_enable_h,
130	.ctrlbit	= S3C2416_HCLKCON_HSMMC0,
131};
132
133static struct clksrc_clk *clksrcs[] __initdata = {
134	&hsspi_eplldiv,
135	&hsspi_mux,
136	&hsmmc_div[0],
137	&hsmmc_div[1],
138	&hsmmc_mux0,
139	&hsmmc_mux1,
140};
141
142static struct clk_lookup s3c2416_clk_lookup[] = {
143	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
144	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
145	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
146	/* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */
147	CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk),
148};
149
150void __init s3c2416_init_clocks(int xtal)
151{
152	u32 epllcon = __raw_readl(S3C2443_EPLLCON);
153	u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
154	int ptr;
155
156	/* s3c2416 EPLL compatible with s3c64xx */
157	clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
158
159	clk_epll.parent = &clk_epllref.clk;
160
161	s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
162				   armdiv, ARRAY_SIZE(armdiv),
163				   S3C2416_CLKDIV0_ARMDIV_MASK);
164
165	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
166		s3c_register_clksrc(clksrcs[ptr], 1);
167
168	s3c24xx_register_clock(&hsmmc0_clk);
169	clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
170
171}