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1/*
2 * Support for the Arcom ZEUS.
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * Loosely based on Arcom's 2.6.16.28.
7 * Maintained by Marc Zyngier <maz@misterjones.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/cpufreq.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/pm.h>
18#include <linux/gpio.h>
19#include <linux/serial_8250.h>
20#include <linux/dm9000.h>
21#include <linux/mmc/host.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/pxa2xx_spi.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h>
26#include <linux/mtd/physmap.h>
27#include <linux/i2c.h>
28#include <linux/i2c/pxa-i2c.h>
29#include <linux/platform_data/pca953x.h>
30#include <linux/apm-emulation.h>
31#include <linux/can/platform/mcp251x.h>
32#include <linux/regulator/fixed.h>
33#include <linux/regulator/machine.h>
34
35#include <asm/mach-types.h>
36#include <asm/suspend.h>
37#include <asm/system_info.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40
41#include <mach/pxa27x.h>
42#include <mach/regs-uart.h>
43#include <linux/platform_data/usb-ohci-pxa27x.h>
44#include <linux/platform_data/mmc-pxamci.h>
45#include <mach/pxa27x-udc.h>
46#include <mach/udc.h>
47#include <linux/platform_data/video-pxafb.h>
48#include <mach/pm.h>
49#include <mach/audio.h>
50#include <linux/platform_data/pcmcia-pxa2xx_viper.h>
51#include <mach/zeus.h>
52#include <mach/smemc.h>
53
54#include "generic.h"
55
56/*
57 * Interrupt handling
58 */
59
60static unsigned long zeus_irq_enabled_mask;
61static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
62static const int zeus_isa_irq_map[] = {
63 0, /* ISA irq #0, invalid */
64 0, /* ISA irq #1, invalid */
65 0, /* ISA irq #2, invalid */
66 1 << 0, /* ISA irq #3 */
67 1 << 1, /* ISA irq #4 */
68 1 << 2, /* ISA irq #5 */
69 1 << 3, /* ISA irq #6 */
70 1 << 4, /* ISA irq #7 */
71 0, /* ISA irq #8, invalid */
72 0, /* ISA irq #9, invalid */
73 1 << 5, /* ISA irq #10 */
74 1 << 6, /* ISA irq #11 */
75 1 << 7, /* ISA irq #12 */
76};
77
78static inline int zeus_irq_to_bitmask(unsigned int irq)
79{
80 return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
81}
82
83static inline int zeus_bit_to_irq(int bit)
84{
85 return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
86}
87
88static void zeus_ack_irq(struct irq_data *d)
89{
90 __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
91}
92
93static void zeus_mask_irq(struct irq_data *d)
94{
95 zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
96}
97
98static void zeus_unmask_irq(struct irq_data *d)
99{
100 zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
101}
102
103static inline unsigned long zeus_irq_pending(void)
104{
105 return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
106}
107
108static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc)
109{
110 unsigned long pending;
111
112 pending = zeus_irq_pending();
113 do {
114 /* we're in a chained irq handler,
115 * so ack the interrupt by hand */
116 desc->irq_data.chip->irq_ack(&desc->irq_data);
117
118 if (likely(pending)) {
119 irq = zeus_bit_to_irq(__ffs(pending));
120 generic_handle_irq(irq);
121 }
122 pending = zeus_irq_pending();
123 } while (pending);
124}
125
126static struct irq_chip zeus_irq_chip = {
127 .name = "ISA",
128 .irq_ack = zeus_ack_irq,
129 .irq_mask = zeus_mask_irq,
130 .irq_unmask = zeus_unmask_irq,
131};
132
133static void __init zeus_init_irq(void)
134{
135 int level;
136 int isa_irq;
137
138 pxa27x_init_irq();
139
140 /* Peripheral IRQs. It would be nice to move those inside driver
141 configuration, but it is not supported at the moment. */
142 irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
143 irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
144 irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
145 irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
146 IRQ_TYPE_EDGE_FALLING);
147 irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
148
149 /* Setup ISA IRQs */
150 for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
151 isa_irq = zeus_bit_to_irq(level);
152 irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
153 handle_edge_irq);
154 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
155 }
156
157 irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
158 irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
159}
160
161
162/*
163 * Platform devices
164 */
165
166/* Flash */
167static struct resource zeus_mtd_resources[] = {
168 [0] = { /* NOR Flash (up to 64MB) */
169 .start = ZEUS_FLASH_PHYS,
170 .end = ZEUS_FLASH_PHYS + SZ_64M - 1,
171 .flags = IORESOURCE_MEM,
172 },
173 [1] = { /* SRAM */
174 .start = ZEUS_SRAM_PHYS,
175 .end = ZEUS_SRAM_PHYS + SZ_512K - 1,
176 .flags = IORESOURCE_MEM,
177 },
178};
179
180static struct physmap_flash_data zeus_flash_data[] = {
181 [0] = {
182 .width = 2,
183 .parts = NULL,
184 .nr_parts = 0,
185 },
186};
187
188static struct platform_device zeus_mtd_devices[] = {
189 [0] = {
190 .name = "physmap-flash",
191 .id = 0,
192 .dev = {
193 .platform_data = &zeus_flash_data[0],
194 },
195 .resource = &zeus_mtd_resources[0],
196 .num_resources = 1,
197 },
198};
199
200/* Serial */
201static struct resource zeus_serial_resources[] = {
202 {
203 .start = 0x10000000,
204 .end = 0x1000000f,
205 .flags = IORESOURCE_MEM,
206 },
207 {
208 .start = 0x10800000,
209 .end = 0x1080000f,
210 .flags = IORESOURCE_MEM,
211 },
212 {
213 .start = 0x11000000,
214 .end = 0x1100000f,
215 .flags = IORESOURCE_MEM,
216 },
217 {
218 .start = 0x40100000,
219 .end = 0x4010001f,
220 .flags = IORESOURCE_MEM,
221 },
222 {
223 .start = 0x40200000,
224 .end = 0x4020001f,
225 .flags = IORESOURCE_MEM,
226 },
227 {
228 .start = 0x40700000,
229 .end = 0x4070001f,
230 .flags = IORESOURCE_MEM,
231 },
232};
233
234static struct plat_serial8250_port serial_platform_data[] = {
235 /* External UARTs */
236 /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
237 { /* COM1 */
238 .mapbase = 0x10000000,
239 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO),
240 .irqflags = IRQF_TRIGGER_RISING,
241 .uartclk = 14745600,
242 .regshift = 1,
243 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
244 .iotype = UPIO_MEM,
245 },
246 { /* COM2 */
247 .mapbase = 0x10800000,
248 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO),
249 .irqflags = IRQF_TRIGGER_RISING,
250 .uartclk = 14745600,
251 .regshift = 1,
252 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
253 .iotype = UPIO_MEM,
254 },
255 { /* COM3 */
256 .mapbase = 0x11000000,
257 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO),
258 .irqflags = IRQF_TRIGGER_RISING,
259 .uartclk = 14745600,
260 .regshift = 1,
261 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
262 .iotype = UPIO_MEM,
263 },
264 { /* COM4 */
265 .mapbase = 0x11800000,
266 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO),
267 .irqflags = IRQF_TRIGGER_RISING,
268 .uartclk = 14745600,
269 .regshift = 1,
270 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
271 .iotype = UPIO_MEM,
272 },
273 /* Internal UARTs */
274 { /* FFUART */
275 .membase = (void *)&FFUART,
276 .mapbase = __PREG(FFUART),
277 .irq = IRQ_FFUART,
278 .uartclk = 921600 * 16,
279 .regshift = 2,
280 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
281 .iotype = UPIO_MEM,
282 },
283 { /* BTUART */
284 .membase = (void *)&BTUART,
285 .mapbase = __PREG(BTUART),
286 .irq = IRQ_BTUART,
287 .uartclk = 921600 * 16,
288 .regshift = 2,
289 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
290 .iotype = UPIO_MEM,
291 },
292 { /* STUART */
293 .membase = (void *)&STUART,
294 .mapbase = __PREG(STUART),
295 .irq = IRQ_STUART,
296 .uartclk = 921600 * 16,
297 .regshift = 2,
298 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
299 .iotype = UPIO_MEM,
300 },
301 { },
302};
303
304static struct platform_device zeus_serial_device = {
305 .name = "serial8250",
306 .id = PLAT8250_DEV_PLATFORM,
307 .dev = {
308 .platform_data = serial_platform_data,
309 },
310 .num_resources = ARRAY_SIZE(zeus_serial_resources),
311 .resource = zeus_serial_resources,
312};
313
314/* Ethernet */
315static struct resource zeus_dm9k0_resource[] = {
316 [0] = {
317 .start = ZEUS_ETH0_PHYS,
318 .end = ZEUS_ETH0_PHYS + 1,
319 .flags = IORESOURCE_MEM
320 },
321 [1] = {
322 .start = ZEUS_ETH0_PHYS + 2,
323 .end = ZEUS_ETH0_PHYS + 3,
324 .flags = IORESOURCE_MEM
325 },
326 [2] = {
327 .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
328 .end = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
329 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
330 },
331};
332
333static struct resource zeus_dm9k1_resource[] = {
334 [0] = {
335 .start = ZEUS_ETH1_PHYS,
336 .end = ZEUS_ETH1_PHYS + 1,
337 .flags = IORESOURCE_MEM
338 },
339 [1] = {
340 .start = ZEUS_ETH1_PHYS + 2,
341 .end = ZEUS_ETH1_PHYS + 3,
342 .flags = IORESOURCE_MEM,
343 },
344 [2] = {
345 .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
346 .end = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
347 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
348 },
349};
350
351static struct dm9000_plat_data zeus_dm9k_platdata = {
352 .flags = DM9000_PLATF_16BITONLY,
353};
354
355static struct platform_device zeus_dm9k0_device = {
356 .name = "dm9000",
357 .id = 0,
358 .num_resources = ARRAY_SIZE(zeus_dm9k0_resource),
359 .resource = zeus_dm9k0_resource,
360 .dev = {
361 .platform_data = &zeus_dm9k_platdata,
362 }
363};
364
365static struct platform_device zeus_dm9k1_device = {
366 .name = "dm9000",
367 .id = 1,
368 .num_resources = ARRAY_SIZE(zeus_dm9k1_resource),
369 .resource = zeus_dm9k1_resource,
370 .dev = {
371 .platform_data = &zeus_dm9k_platdata,
372 }
373};
374
375/* External SRAM */
376static struct resource zeus_sram_resource = {
377 .start = ZEUS_SRAM_PHYS,
378 .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
379 .flags = IORESOURCE_MEM,
380};
381
382static struct platform_device zeus_sram_device = {
383 .name = "pxa2xx-8bit-sram",
384 .id = 0,
385 .num_resources = 1,
386 .resource = &zeus_sram_resource,
387};
388
389/* SPI interface on SSP3 */
390static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
391 .num_chipselect = 1,
392 .enable_dma = 1,
393};
394
395/* CAN bus on SPI */
396static struct regulator_consumer_supply can_regulator_consumer =
397 REGULATOR_SUPPLY("vdd", "spi3.0");
398
399static struct regulator_init_data can_regulator_init_data = {
400 .constraints = {
401 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
402 },
403 .consumer_supplies = &can_regulator_consumer,
404 .num_consumer_supplies = 1,
405};
406
407static struct fixed_voltage_config can_regulator_pdata = {
408 .supply_name = "CAN_SHDN",
409 .microvolts = 3300000,
410 .gpio = ZEUS_CAN_SHDN_GPIO,
411 .init_data = &can_regulator_init_data,
412};
413
414static struct platform_device can_regulator_device = {
415 .name = "reg-fixed-volage",
416 .id = -1,
417 .dev = {
418 .platform_data = &can_regulator_pdata,
419 },
420};
421
422static struct mcp251x_platform_data zeus_mcp2515_pdata = {
423 .oscillator_frequency = 16*1000*1000,
424};
425
426static struct spi_board_info zeus_spi_board_info[] = {
427 [0] = {
428 .modalias = "mcp2515",
429 .platform_data = &zeus_mcp2515_pdata,
430 .irq = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
431 .max_speed_hz = 1*1000*1000,
432 .bus_num = 3,
433 .mode = SPI_MODE_0,
434 .chip_select = 0,
435 },
436};
437
438/* Leds */
439static struct gpio_led zeus_leds[] = {
440 [0] = {
441 .name = "zeus:yellow:1",
442 .default_trigger = "heartbeat",
443 .gpio = ZEUS_EXT0_GPIO(3),
444 .active_low = 1,
445 },
446 [1] = {
447 .name = "zeus:yellow:2",
448 .default_trigger = "default-on",
449 .gpio = ZEUS_EXT0_GPIO(4),
450 .active_low = 1,
451 },
452 [2] = {
453 .name = "zeus:yellow:3",
454 .default_trigger = "default-on",
455 .gpio = ZEUS_EXT0_GPIO(5),
456 .active_low = 1,
457 },
458};
459
460static struct gpio_led_platform_data zeus_leds_info = {
461 .leds = zeus_leds,
462 .num_leds = ARRAY_SIZE(zeus_leds),
463};
464
465static struct platform_device zeus_leds_device = {
466 .name = "leds-gpio",
467 .id = -1,
468 .dev = {
469 .platform_data = &zeus_leds_info,
470 },
471};
472
473static void zeus_cf_reset(int state)
474{
475 u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
476
477 if (state)
478 cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
479 else
480 cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
481
482 __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
483}
484
485static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
486 .cd_gpio = ZEUS_CF_CD_GPIO,
487 .rdy_gpio = ZEUS_CF_RDY_GPIO,
488 .pwr_gpio = ZEUS_CF_PWEN_GPIO,
489 .reset = zeus_cf_reset,
490};
491
492static struct platform_device zeus_pcmcia_device = {
493 .name = "zeus-pcmcia",
494 .id = -1,
495 .dev = {
496 .platform_data = &zeus_pcmcia_info,
497 },
498};
499
500static struct resource zeus_max6369_resource = {
501 .start = ZEUS_CPLD_EXTWDOG_PHYS,
502 .end = ZEUS_CPLD_EXTWDOG_PHYS,
503 .flags = IORESOURCE_MEM,
504};
505
506struct platform_device zeus_max6369_device = {
507 .name = "max6369_wdt",
508 .id = -1,
509 .resource = &zeus_max6369_resource,
510 .num_resources = 1,
511};
512
513static struct platform_device *zeus_devices[] __initdata = {
514 &zeus_serial_device,
515 &zeus_mtd_devices[0],
516 &zeus_dm9k0_device,
517 &zeus_dm9k1_device,
518 &zeus_sram_device,
519 &zeus_leds_device,
520 &zeus_pcmcia_device,
521 &zeus_max6369_device,
522 &can_regulator_device,
523};
524
525/* AC'97 */
526static pxa2xx_audio_ops_t zeus_ac97_info = {
527 .reset_gpio = 95,
528};
529
530
531/*
532 * USB host
533 */
534
535static int zeus_ohci_init(struct device *dev)
536{
537 int err;
538
539 /* Switch on port 2. */
540 if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) {
541 dev_err(dev, "Can't request USB2_PWREN\n");
542 return err;
543 }
544
545 if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) {
546 gpio_free(ZEUS_USB2_PWREN_GPIO);
547 dev_err(dev, "Can't enable USB2_PWREN\n");
548 return err;
549 }
550
551 /* Port 2 is shared between host and client interface. */
552 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
553
554 return 0;
555}
556
557static void zeus_ohci_exit(struct device *dev)
558{
559 /* Power-off port 2 */
560 gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0);
561 gpio_free(ZEUS_USB2_PWREN_GPIO);
562}
563
564static struct pxaohci_platform_data zeus_ohci_platform_data = {
565 .port_mode = PMM_NPS_MODE,
566 /* Clear Power Control Polarity Low and set Power Sense
567 * Polarity Low. Supply power to USB ports. */
568 .flags = ENABLE_PORT_ALL | POWER_SENSE_LOW,
569 .init = zeus_ohci_init,
570 .exit = zeus_ohci_exit,
571};
572
573/*
574 * Flat Panel
575 */
576
577static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
578{
579 gpio_set_value(ZEUS_LCD_EN_GPIO, on);
580}
581
582static void zeus_backlight_power(int on)
583{
584 gpio_set_value(ZEUS_BKLEN_GPIO, on);
585}
586
587static int zeus_setup_fb_gpios(void)
588{
589 int err;
590
591 if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
592 goto out_err;
593
594 if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
595 goto out_err_lcd;
596
597 if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
598 goto out_err_lcd;
599
600 if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
601 goto out_err_bkl;
602
603 return 0;
604
605out_err_bkl:
606 gpio_free(ZEUS_BKLEN_GPIO);
607out_err_lcd:
608 gpio_free(ZEUS_LCD_EN_GPIO);
609out_err:
610 return err;
611}
612
613static struct pxafb_mode_info zeus_fb_mode_info[] = {
614 {
615 .pixclock = 39722,
616
617 .xres = 640,
618 .yres = 480,
619
620 .bpp = 16,
621
622 .hsync_len = 63,
623 .left_margin = 16,
624 .right_margin = 81,
625
626 .vsync_len = 2,
627 .upper_margin = 12,
628 .lower_margin = 31,
629
630 .sync = 0,
631 },
632};
633
634static struct pxafb_mach_info zeus_fb_info = {
635 .modes = zeus_fb_mode_info,
636 .num_modes = 1,
637 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
638 .pxafb_lcd_power = zeus_lcd_power,
639 .pxafb_backlight_power = zeus_backlight_power,
640};
641
642/*
643 * MMC/SD Device
644 *
645 * The card detect interrupt isn't debounced so we delay it by 250ms
646 * to give the card a chance to fully insert/eject.
647 */
648
649static struct pxamci_platform_data zeus_mci_platform_data = {
650 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
651 .detect_delay_ms = 250,
652 .gpio_card_detect = ZEUS_MMC_CD_GPIO,
653 .gpio_card_ro = ZEUS_MMC_WP_GPIO,
654 .gpio_card_ro_invert = 1,
655 .gpio_power = -1
656};
657
658/*
659 * USB Device Controller
660 */
661static void zeus_udc_command(int cmd)
662{
663 switch (cmd) {
664 case PXA2XX_UDC_CMD_DISCONNECT:
665 pr_info("zeus: disconnecting USB client\n");
666 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
667 break;
668
669 case PXA2XX_UDC_CMD_CONNECT:
670 pr_info("zeus: connecting USB client\n");
671 UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
672 break;
673 }
674}
675
676static struct pxa2xx_udc_mach_info zeus_udc_info = {
677 .udc_command = zeus_udc_command,
678};
679
680#ifdef CONFIG_PM
681static void zeus_power_off(void)
682{
683 local_irq_disable();
684 cpu_suspend(PWRMODE_DEEPSLEEP, pxa27x_finish_suspend);
685}
686#else
687#define zeus_power_off NULL
688#endif
689
690#ifdef CONFIG_APM_EMULATION
691static void zeus_get_power_status(struct apm_power_info *info)
692{
693 /* Power supply is always present */
694 info->ac_line_status = APM_AC_ONLINE;
695 info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT;
696 info->battery_flag = APM_BATTERY_FLAG_NOT_PRESENT;
697}
698
699static inline void zeus_setup_apm(void)
700{
701 apm_get_power_status = zeus_get_power_status;
702}
703#else
704static inline void zeus_setup_apm(void)
705{
706}
707#endif
708
709static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
710 unsigned ngpio, void *context)
711{
712 int i;
713 u8 pcb_info = 0;
714
715 for (i = 0; i < 8; i++) {
716 int pcb_bit = gpio + i + 8;
717
718 if (gpio_request(pcb_bit, "pcb info")) {
719 dev_err(&client->dev, "Can't request pcb info %d\n", i);
720 continue;
721 }
722
723 if (gpio_direction_input(pcb_bit)) {
724 dev_err(&client->dev, "Can't read pcb info %d\n", i);
725 gpio_free(pcb_bit);
726 continue;
727 }
728
729 pcb_info |= !!gpio_get_value(pcb_bit) << i;
730
731 gpio_free(pcb_bit);
732 }
733
734 dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
735 pcb_info >> 4, pcb_info & 0xf);
736
737 return 0;
738}
739
740static struct pca953x_platform_data zeus_pca953x_pdata[] = {
741 [0] = { .gpio_base = ZEUS_EXT0_GPIO_BASE, },
742 [1] = {
743 .gpio_base = ZEUS_EXT1_GPIO_BASE,
744 .setup = zeus_get_pcb_info,
745 },
746 [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
747};
748
749static struct i2c_board_info __initdata zeus_i2c_devices[] = {
750 {
751 I2C_BOARD_INFO("pca9535", 0x21),
752 .platform_data = &zeus_pca953x_pdata[0],
753 },
754 {
755 I2C_BOARD_INFO("pca9535", 0x22),
756 .platform_data = &zeus_pca953x_pdata[1],
757 },
758 {
759 I2C_BOARD_INFO("pca9535", 0x20),
760 .platform_data = &zeus_pca953x_pdata[2],
761 .irq = PXA_GPIO_TO_IRQ(ZEUS_EXTGPIO_GPIO),
762 },
763 { I2C_BOARD_INFO("lm75a", 0x48) },
764 { I2C_BOARD_INFO("24c01", 0x50) },
765 { I2C_BOARD_INFO("isl1208", 0x6f) },
766};
767
768static mfp_cfg_t zeus_pin_config[] __initdata = {
769 /* AC97 */
770 GPIO28_AC97_BITCLK,
771 GPIO29_AC97_SDATA_IN_0,
772 GPIO30_AC97_SDATA_OUT,
773 GPIO31_AC97_SYNC,
774
775 GPIO15_nCS_1,
776 GPIO78_nCS_2,
777 GPIO80_nCS_4,
778 GPIO33_nCS_5,
779
780 GPIO22_GPIO,
781 GPIO32_MMC_CLK,
782 GPIO92_MMC_DAT_0,
783 GPIO109_MMC_DAT_1,
784 GPIO110_MMC_DAT_2,
785 GPIO111_MMC_DAT_3,
786 GPIO112_MMC_CMD,
787
788 GPIO88_USBH1_PWR,
789 GPIO89_USBH1_PEN,
790 GPIO119_USBH2_PWR,
791 GPIO120_USBH2_PEN,
792
793 GPIO86_LCD_LDD_16,
794 GPIO87_LCD_LDD_17,
795
796 GPIO102_GPIO,
797 GPIO104_CIF_DD_2,
798 GPIO105_CIF_DD_1,
799
800 GPIO81_SSP3_TXD,
801 GPIO82_SSP3_RXD,
802 GPIO83_SSP3_SFRM,
803 GPIO84_SSP3_SCLK,
804
805 GPIO48_nPOE,
806 GPIO49_nPWE,
807 GPIO50_nPIOR,
808 GPIO51_nPIOW,
809 GPIO85_nPCE_1,
810 GPIO54_nPCE_2,
811 GPIO79_PSKTSEL,
812 GPIO55_nPREG,
813 GPIO56_nPWAIT,
814 GPIO57_nIOIS16,
815 GPIO36_GPIO, /* CF CD */
816 GPIO97_GPIO, /* CF PWREN */
817 GPIO99_GPIO, /* CF RDY */
818};
819
820/*
821 * DM9k MSCx settings: SRAM, 16 bits
822 * 17 cycles delay first access
823 * 5 cycles delay next access
824 * 13 cycles recovery time
825 * faster device
826 */
827#define DM9K_MSC_VALUE 0xe4c9
828
829static void __init zeus_init(void)
830{
831 u16 dm9000_msc = DM9K_MSC_VALUE;
832 u32 msc0, msc1;
833
834 system_rev = __raw_readw(ZEUS_CPLD_VERSION);
835 pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
836
837 /* Fix timings for dm9000s (CS1/CS2)*/
838 msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
839 msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
840 __raw_writel(msc0, MSC0);
841 __raw_writel(msc1, MSC1);
842
843 pm_power_off = zeus_power_off;
844 zeus_setup_apm();
845
846 pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
847
848 platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
849
850 pxa_set_ohci_info(&zeus_ohci_platform_data);
851
852 if (zeus_setup_fb_gpios())
853 pr_err("Failed to setup fb gpios\n");
854 else
855 pxa_set_fb_info(NULL, &zeus_fb_info);
856
857 pxa_set_mci_info(&zeus_mci_platform_data);
858 pxa_set_udc_info(&zeus_udc_info);
859 pxa_set_ac97_info(&zeus_ac97_info);
860 pxa_set_i2c_info(NULL);
861 i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
862 pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
863 spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
864}
865
866static struct map_desc zeus_io_desc[] __initdata = {
867 {
868 .virtual = (unsigned long)ZEUS_CPLD_VERSION,
869 .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
870 .length = 0x1000,
871 .type = MT_DEVICE,
872 },
873 {
874 .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ,
875 .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
876 .length = 0x1000,
877 .type = MT_DEVICE,
878 },
879 {
880 .virtual = (unsigned long)ZEUS_CPLD_CONTROL,
881 .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
882 .length = 0x1000,
883 .type = MT_DEVICE,
884 },
885 {
886 .virtual = (unsigned long)ZEUS_PC104IO,
887 .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS),
888 .length = 0x00800000,
889 .type = MT_DEVICE,
890 },
891};
892
893static void __init zeus_map_io(void)
894{
895 pxa27x_map_io();
896
897 iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
898
899 /* Clear PSPR to ensure a full restart on wake-up. */
900 PMCR = PSPR = 0;
901
902 /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
903 OSCC |= OSCC_OON;
904
905 /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
906 * float chip selects and PCMCIA */
907 PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
908}
909
910MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
911 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
912 .atag_offset = 0x100,
913 .map_io = zeus_map_io,
914 .nr_irqs = ZEUS_NR_IRQS,
915 .init_irq = zeus_init_irq,
916 .handle_irq = pxa27x_handle_irq,
917 .init_time = pxa_timer_init,
918 .init_machine = zeus_init,
919 .restart = pxa_restart,
920MACHINE_END
921
1/*
2 * Support for the Arcom ZEUS.
3 *
4 * Copyright (C) 2006 Arcom Control Systems Ltd.
5 *
6 * Loosely based on Arcom's 2.6.16.28.
7 * Maintained by Marc Zyngier <maz@misterjones.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/cpufreq.h>
15#include <linux/interrupt.h>
16#include <linux/leds.h>
17#include <linux/irq.h>
18#include <linux/pm.h>
19#include <linux/gpio.h>
20#include <linux/serial_8250.h>
21#include <linux/dm9000.h>
22#include <linux/mmc/host.h>
23#include <linux/spi/spi.h>
24#include <linux/spi/pxa2xx_spi.h>
25#include <linux/mtd/mtd.h>
26#include <linux/mtd/partitions.h>
27#include <linux/mtd/physmap.h>
28#include <linux/i2c.h>
29#include <linux/platform_data/i2c-pxa.h>
30#include <linux/platform_data/pca953x.h>
31#include <linux/apm-emulation.h>
32#include <linux/can/platform/mcp251x.h>
33#include <linux/regulator/fixed.h>
34#include <linux/regulator/machine.h>
35
36#include <asm/mach-types.h>
37#include <asm/suspend.h>
38#include <asm/system_info.h>
39#include <asm/mach/arch.h>
40#include <asm/mach/map.h>
41
42#include "pxa27x.h"
43#include "devices.h"
44#include <mach/regs-uart.h>
45#include <linux/platform_data/usb-ohci-pxa27x.h>
46#include <linux/platform_data/mmc-pxamci.h>
47#include "pxa27x-udc.h"
48#include "udc.h"
49#include <linux/platform_data/video-pxafb.h>
50#include "pm.h"
51#include <mach/audio.h>
52#include <linux/platform_data/pcmcia-pxa2xx_viper.h>
53#include "zeus.h"
54#include <mach/smemc.h>
55
56#include "generic.h"
57
58/*
59 * Interrupt handling
60 */
61
62static unsigned long zeus_irq_enabled_mask;
63static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
64static const int zeus_isa_irq_map[] = {
65 0, /* ISA irq #0, invalid */
66 0, /* ISA irq #1, invalid */
67 0, /* ISA irq #2, invalid */
68 1 << 0, /* ISA irq #3 */
69 1 << 1, /* ISA irq #4 */
70 1 << 2, /* ISA irq #5 */
71 1 << 3, /* ISA irq #6 */
72 1 << 4, /* ISA irq #7 */
73 0, /* ISA irq #8, invalid */
74 0, /* ISA irq #9, invalid */
75 1 << 5, /* ISA irq #10 */
76 1 << 6, /* ISA irq #11 */
77 1 << 7, /* ISA irq #12 */
78};
79
80static inline int zeus_irq_to_bitmask(unsigned int irq)
81{
82 return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
83}
84
85static inline int zeus_bit_to_irq(int bit)
86{
87 return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
88}
89
90static void zeus_ack_irq(struct irq_data *d)
91{
92 __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
93}
94
95static void zeus_mask_irq(struct irq_data *d)
96{
97 zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
98}
99
100static void zeus_unmask_irq(struct irq_data *d)
101{
102 zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
103}
104
105static inline unsigned long zeus_irq_pending(void)
106{
107 return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
108}
109
110static void zeus_irq_handler(struct irq_desc *desc)
111{
112 unsigned int irq;
113 unsigned long pending;
114
115 pending = zeus_irq_pending();
116 do {
117 /* we're in a chained irq handler,
118 * so ack the interrupt by hand */
119 desc->irq_data.chip->irq_ack(&desc->irq_data);
120
121 if (likely(pending)) {
122 irq = zeus_bit_to_irq(__ffs(pending));
123 generic_handle_irq(irq);
124 }
125 pending = zeus_irq_pending();
126 } while (pending);
127}
128
129static struct irq_chip zeus_irq_chip = {
130 .name = "ISA",
131 .irq_ack = zeus_ack_irq,
132 .irq_mask = zeus_mask_irq,
133 .irq_unmask = zeus_unmask_irq,
134};
135
136static void __init zeus_init_irq(void)
137{
138 int level;
139 int isa_irq;
140
141 pxa27x_init_irq();
142
143 /* Peripheral IRQs. It would be nice to move those inside driver
144 configuration, but it is not supported at the moment. */
145 irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
146 irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
147 irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
148 irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
149 IRQ_TYPE_EDGE_FALLING);
150 irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
151
152 /* Setup ISA IRQs */
153 for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
154 isa_irq = zeus_bit_to_irq(level);
155 irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
156 handle_edge_irq);
157 irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
158 }
159
160 irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
161 irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
162}
163
164
165/*
166 * Platform devices
167 */
168
169/* Flash */
170static struct resource zeus_mtd_resources[] = {
171 [0] = { /* NOR Flash (up to 64MB) */
172 .start = ZEUS_FLASH_PHYS,
173 .end = ZEUS_FLASH_PHYS + SZ_64M - 1,
174 .flags = IORESOURCE_MEM,
175 },
176 [1] = { /* SRAM */
177 .start = ZEUS_SRAM_PHYS,
178 .end = ZEUS_SRAM_PHYS + SZ_512K - 1,
179 .flags = IORESOURCE_MEM,
180 },
181};
182
183static struct physmap_flash_data zeus_flash_data[] = {
184 [0] = {
185 .width = 2,
186 .parts = NULL,
187 .nr_parts = 0,
188 },
189};
190
191static struct platform_device zeus_mtd_devices[] = {
192 [0] = {
193 .name = "physmap-flash",
194 .id = 0,
195 .dev = {
196 .platform_data = &zeus_flash_data[0],
197 },
198 .resource = &zeus_mtd_resources[0],
199 .num_resources = 1,
200 },
201};
202
203/* Serial */
204static struct resource zeus_serial_resources[] = {
205 {
206 .start = 0x10000000,
207 .end = 0x1000000f,
208 .flags = IORESOURCE_MEM,
209 },
210 {
211 .start = 0x10800000,
212 .end = 0x1080000f,
213 .flags = IORESOURCE_MEM,
214 },
215 {
216 .start = 0x11000000,
217 .end = 0x1100000f,
218 .flags = IORESOURCE_MEM,
219 },
220 {
221 .start = 0x40100000,
222 .end = 0x4010001f,
223 .flags = IORESOURCE_MEM,
224 },
225 {
226 .start = 0x40200000,
227 .end = 0x4020001f,
228 .flags = IORESOURCE_MEM,
229 },
230 {
231 .start = 0x40700000,
232 .end = 0x4070001f,
233 .flags = IORESOURCE_MEM,
234 },
235};
236
237static struct plat_serial8250_port serial_platform_data[] = {
238 /* External UARTs */
239 /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
240 { /* COM1 */
241 .mapbase = 0x10000000,
242 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO),
243 .irqflags = IRQF_TRIGGER_RISING,
244 .uartclk = 14745600,
245 .regshift = 1,
246 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
247 .iotype = UPIO_MEM,
248 },
249 { /* COM2 */
250 .mapbase = 0x10800000,
251 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO),
252 .irqflags = IRQF_TRIGGER_RISING,
253 .uartclk = 14745600,
254 .regshift = 1,
255 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
256 .iotype = UPIO_MEM,
257 },
258 { /* COM3 */
259 .mapbase = 0x11000000,
260 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO),
261 .irqflags = IRQF_TRIGGER_RISING,
262 .uartclk = 14745600,
263 .regshift = 1,
264 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
265 .iotype = UPIO_MEM,
266 },
267 { /* COM4 */
268 .mapbase = 0x11800000,
269 .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO),
270 .irqflags = IRQF_TRIGGER_RISING,
271 .uartclk = 14745600,
272 .regshift = 1,
273 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
274 .iotype = UPIO_MEM,
275 },
276 /* Internal UARTs */
277 { /* FFUART */
278 .membase = (void *)&FFUART,
279 .mapbase = __PREG(FFUART),
280 .irq = IRQ_FFUART,
281 .uartclk = 921600 * 16,
282 .regshift = 2,
283 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
284 .iotype = UPIO_MEM,
285 },
286 { /* BTUART */
287 .membase = (void *)&BTUART,
288 .mapbase = __PREG(BTUART),
289 .irq = IRQ_BTUART,
290 .uartclk = 921600 * 16,
291 .regshift = 2,
292 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
293 .iotype = UPIO_MEM,
294 },
295 { /* STUART */
296 .membase = (void *)&STUART,
297 .mapbase = __PREG(STUART),
298 .irq = IRQ_STUART,
299 .uartclk = 921600 * 16,
300 .regshift = 2,
301 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
302 .iotype = UPIO_MEM,
303 },
304 { },
305};
306
307static struct platform_device zeus_serial_device = {
308 .name = "serial8250",
309 .id = PLAT8250_DEV_PLATFORM,
310 .dev = {
311 .platform_data = serial_platform_data,
312 },
313 .num_resources = ARRAY_SIZE(zeus_serial_resources),
314 .resource = zeus_serial_resources,
315};
316
317/* Ethernet */
318static struct resource zeus_dm9k0_resource[] = {
319 [0] = {
320 .start = ZEUS_ETH0_PHYS,
321 .end = ZEUS_ETH0_PHYS + 1,
322 .flags = IORESOURCE_MEM
323 },
324 [1] = {
325 .start = ZEUS_ETH0_PHYS + 2,
326 .end = ZEUS_ETH0_PHYS + 3,
327 .flags = IORESOURCE_MEM
328 },
329 [2] = {
330 .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
331 .end = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
332 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
333 },
334};
335
336static struct resource zeus_dm9k1_resource[] = {
337 [0] = {
338 .start = ZEUS_ETH1_PHYS,
339 .end = ZEUS_ETH1_PHYS + 1,
340 .flags = IORESOURCE_MEM
341 },
342 [1] = {
343 .start = ZEUS_ETH1_PHYS + 2,
344 .end = ZEUS_ETH1_PHYS + 3,
345 .flags = IORESOURCE_MEM,
346 },
347 [2] = {
348 .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
349 .end = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
350 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
351 },
352};
353
354static struct dm9000_plat_data zeus_dm9k_platdata = {
355 .flags = DM9000_PLATF_16BITONLY,
356};
357
358static struct platform_device zeus_dm9k0_device = {
359 .name = "dm9000",
360 .id = 0,
361 .num_resources = ARRAY_SIZE(zeus_dm9k0_resource),
362 .resource = zeus_dm9k0_resource,
363 .dev = {
364 .platform_data = &zeus_dm9k_platdata,
365 }
366};
367
368static struct platform_device zeus_dm9k1_device = {
369 .name = "dm9000",
370 .id = 1,
371 .num_resources = ARRAY_SIZE(zeus_dm9k1_resource),
372 .resource = zeus_dm9k1_resource,
373 .dev = {
374 .platform_data = &zeus_dm9k_platdata,
375 }
376};
377
378/* External SRAM */
379static struct resource zeus_sram_resource = {
380 .start = ZEUS_SRAM_PHYS,
381 .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
382 .flags = IORESOURCE_MEM,
383};
384
385static struct platform_device zeus_sram_device = {
386 .name = "pxa2xx-8bit-sram",
387 .id = 0,
388 .num_resources = 1,
389 .resource = &zeus_sram_resource,
390};
391
392/* SPI interface on SSP3 */
393static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
394 .num_chipselect = 1,
395 .enable_dma = 1,
396};
397
398/* CAN bus on SPI */
399static struct regulator_consumer_supply can_regulator_consumer =
400 REGULATOR_SUPPLY("vdd", "spi3.0");
401
402static struct regulator_init_data can_regulator_init_data = {
403 .constraints = {
404 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
405 },
406 .consumer_supplies = &can_regulator_consumer,
407 .num_consumer_supplies = 1,
408};
409
410static struct fixed_voltage_config can_regulator_pdata = {
411 .supply_name = "CAN_SHDN",
412 .microvolts = 3300000,
413 .gpio = ZEUS_CAN_SHDN_GPIO,
414 .init_data = &can_regulator_init_data,
415};
416
417static struct platform_device can_regulator_device = {
418 .name = "reg-fixed-voltage",
419 .id = 0,
420 .dev = {
421 .platform_data = &can_regulator_pdata,
422 },
423};
424
425static struct mcp251x_platform_data zeus_mcp2515_pdata = {
426 .oscillator_frequency = 16*1000*1000,
427};
428
429static struct spi_board_info zeus_spi_board_info[] = {
430 [0] = {
431 .modalias = "mcp2515",
432 .platform_data = &zeus_mcp2515_pdata,
433 .irq = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
434 .max_speed_hz = 1*1000*1000,
435 .bus_num = 3,
436 .mode = SPI_MODE_0,
437 .chip_select = 0,
438 },
439};
440
441/* Leds */
442static struct gpio_led zeus_leds[] = {
443 [0] = {
444 .name = "zeus:yellow:1",
445 .default_trigger = "heartbeat",
446 .gpio = ZEUS_EXT0_GPIO(3),
447 .active_low = 1,
448 },
449 [1] = {
450 .name = "zeus:yellow:2",
451 .default_trigger = "default-on",
452 .gpio = ZEUS_EXT0_GPIO(4),
453 .active_low = 1,
454 },
455 [2] = {
456 .name = "zeus:yellow:3",
457 .default_trigger = "default-on",
458 .gpio = ZEUS_EXT0_GPIO(5),
459 .active_low = 1,
460 },
461};
462
463static struct gpio_led_platform_data zeus_leds_info = {
464 .leds = zeus_leds,
465 .num_leds = ARRAY_SIZE(zeus_leds),
466};
467
468static struct platform_device zeus_leds_device = {
469 .name = "leds-gpio",
470 .id = -1,
471 .dev = {
472 .platform_data = &zeus_leds_info,
473 },
474};
475
476static void zeus_cf_reset(int state)
477{
478 u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
479
480 if (state)
481 cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
482 else
483 cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
484
485 __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
486}
487
488static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
489 .cd_gpio = ZEUS_CF_CD_GPIO,
490 .rdy_gpio = ZEUS_CF_RDY_GPIO,
491 .pwr_gpio = ZEUS_CF_PWEN_GPIO,
492 .reset = zeus_cf_reset,
493};
494
495static struct platform_device zeus_pcmcia_device = {
496 .name = "zeus-pcmcia",
497 .id = -1,
498 .dev = {
499 .platform_data = &zeus_pcmcia_info,
500 },
501};
502
503static struct resource zeus_max6369_resource = {
504 .start = ZEUS_CPLD_EXTWDOG_PHYS,
505 .end = ZEUS_CPLD_EXTWDOG_PHYS,
506 .flags = IORESOURCE_MEM,
507};
508
509struct platform_device zeus_max6369_device = {
510 .name = "max6369_wdt",
511 .id = -1,
512 .resource = &zeus_max6369_resource,
513 .num_resources = 1,
514};
515
516/* AC'97 */
517static pxa2xx_audio_ops_t zeus_ac97_info = {
518 .reset_gpio = 95,
519};
520
521
522/*
523 * USB host
524 */
525
526static struct regulator_consumer_supply zeus_ohci_regulator_supplies[] = {
527 REGULATOR_SUPPLY("vbus2", "pxa27x-ohci"),
528};
529
530static struct regulator_init_data zeus_ohci_regulator_data = {
531 .constraints = {
532 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
533 },
534 .num_consumer_supplies = ARRAY_SIZE(zeus_ohci_regulator_supplies),
535 .consumer_supplies = zeus_ohci_regulator_supplies,
536};
537
538static struct fixed_voltage_config zeus_ohci_regulator_config = {
539 .supply_name = "vbus2",
540 .microvolts = 5000000, /* 5.0V */
541 .gpio = ZEUS_USB2_PWREN_GPIO,
542 .enable_high = 1,
543 .startup_delay = 0,
544 .init_data = &zeus_ohci_regulator_data,
545};
546
547static struct platform_device zeus_ohci_regulator_device = {
548 .name = "reg-fixed-voltage",
549 .id = 1,
550 .dev = {
551 .platform_data = &zeus_ohci_regulator_config,
552 },
553};
554
555static struct pxaohci_platform_data zeus_ohci_platform_data = {
556 .port_mode = PMM_NPS_MODE,
557 /* Clear Power Control Polarity Low and set Power Sense
558 * Polarity Low. Supply power to USB ports. */
559 .flags = ENABLE_PORT_ALL | POWER_SENSE_LOW,
560};
561
562static void zeus_register_ohci(void)
563{
564 /* Port 2 is shared between host and client interface. */
565 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
566
567 pxa_set_ohci_info(&zeus_ohci_platform_data);
568}
569
570/*
571 * Flat Panel
572 */
573
574static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
575{
576 gpio_set_value(ZEUS_LCD_EN_GPIO, on);
577}
578
579static void zeus_backlight_power(int on)
580{
581 gpio_set_value(ZEUS_BKLEN_GPIO, on);
582}
583
584static int zeus_setup_fb_gpios(void)
585{
586 int err;
587
588 if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
589 goto out_err;
590
591 if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
592 goto out_err_lcd;
593
594 if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
595 goto out_err_lcd;
596
597 if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
598 goto out_err_bkl;
599
600 return 0;
601
602out_err_bkl:
603 gpio_free(ZEUS_BKLEN_GPIO);
604out_err_lcd:
605 gpio_free(ZEUS_LCD_EN_GPIO);
606out_err:
607 return err;
608}
609
610static struct pxafb_mode_info zeus_fb_mode_info[] = {
611 {
612 .pixclock = 39722,
613
614 .xres = 640,
615 .yres = 480,
616
617 .bpp = 16,
618
619 .hsync_len = 63,
620 .left_margin = 16,
621 .right_margin = 81,
622
623 .vsync_len = 2,
624 .upper_margin = 12,
625 .lower_margin = 31,
626
627 .sync = 0,
628 },
629};
630
631static struct pxafb_mach_info zeus_fb_info = {
632 .modes = zeus_fb_mode_info,
633 .num_modes = 1,
634 .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
635 .pxafb_lcd_power = zeus_lcd_power,
636 .pxafb_backlight_power = zeus_backlight_power,
637};
638
639/*
640 * MMC/SD Device
641 *
642 * The card detect interrupt isn't debounced so we delay it by 250ms
643 * to give the card a chance to fully insert/eject.
644 */
645
646static struct pxamci_platform_data zeus_mci_platform_data = {
647 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
648 .detect_delay_ms = 250,
649 .gpio_card_detect = ZEUS_MMC_CD_GPIO,
650 .gpio_card_ro = ZEUS_MMC_WP_GPIO,
651 .gpio_card_ro_invert = 1,
652 .gpio_power = -1
653};
654
655/*
656 * USB Device Controller
657 */
658static void zeus_udc_command(int cmd)
659{
660 switch (cmd) {
661 case PXA2XX_UDC_CMD_DISCONNECT:
662 pr_info("zeus: disconnecting USB client\n");
663 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
664 break;
665
666 case PXA2XX_UDC_CMD_CONNECT:
667 pr_info("zeus: connecting USB client\n");
668 UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
669 break;
670 }
671}
672
673static struct pxa2xx_udc_mach_info zeus_udc_info = {
674 .udc_command = zeus_udc_command,
675};
676
677static struct platform_device *zeus_devices[] __initdata = {
678 &zeus_serial_device,
679 &zeus_mtd_devices[0],
680 &zeus_dm9k0_device,
681 &zeus_dm9k1_device,
682 &zeus_sram_device,
683 &zeus_leds_device,
684 &zeus_pcmcia_device,
685 &zeus_max6369_device,
686 &can_regulator_device,
687 &zeus_ohci_regulator_device,
688};
689
690#ifdef CONFIG_PM
691static void zeus_power_off(void)
692{
693 local_irq_disable();
694 cpu_suspend(PWRMODE_DEEPSLEEP, pxa27x_finish_suspend);
695}
696#else
697#define zeus_power_off NULL
698#endif
699
700#ifdef CONFIG_APM_EMULATION
701static void zeus_get_power_status(struct apm_power_info *info)
702{
703 /* Power supply is always present */
704 info->ac_line_status = APM_AC_ONLINE;
705 info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT;
706 info->battery_flag = APM_BATTERY_FLAG_NOT_PRESENT;
707}
708
709static inline void zeus_setup_apm(void)
710{
711 apm_get_power_status = zeus_get_power_status;
712}
713#else
714static inline void zeus_setup_apm(void)
715{
716}
717#endif
718
719static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
720 unsigned ngpio, void *context)
721{
722 int i;
723 u8 pcb_info = 0;
724
725 for (i = 0; i < 8; i++) {
726 int pcb_bit = gpio + i + 8;
727
728 if (gpio_request(pcb_bit, "pcb info")) {
729 dev_err(&client->dev, "Can't request pcb info %d\n", i);
730 continue;
731 }
732
733 if (gpio_direction_input(pcb_bit)) {
734 dev_err(&client->dev, "Can't read pcb info %d\n", i);
735 gpio_free(pcb_bit);
736 continue;
737 }
738
739 pcb_info |= !!gpio_get_value(pcb_bit) << i;
740
741 gpio_free(pcb_bit);
742 }
743
744 dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
745 pcb_info >> 4, pcb_info & 0xf);
746
747 return 0;
748}
749
750static struct pca953x_platform_data zeus_pca953x_pdata[] = {
751 [0] = { .gpio_base = ZEUS_EXT0_GPIO_BASE, },
752 [1] = {
753 .gpio_base = ZEUS_EXT1_GPIO_BASE,
754 .setup = zeus_get_pcb_info,
755 },
756 [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
757};
758
759static struct i2c_board_info __initdata zeus_i2c_devices[] = {
760 {
761 I2C_BOARD_INFO("pca9535", 0x21),
762 .platform_data = &zeus_pca953x_pdata[0],
763 },
764 {
765 I2C_BOARD_INFO("pca9535", 0x22),
766 .platform_data = &zeus_pca953x_pdata[1],
767 },
768 {
769 I2C_BOARD_INFO("pca9535", 0x20),
770 .platform_data = &zeus_pca953x_pdata[2],
771 .irq = PXA_GPIO_TO_IRQ(ZEUS_EXTGPIO_GPIO),
772 },
773 { I2C_BOARD_INFO("lm75a", 0x48) },
774 { I2C_BOARD_INFO("24c01", 0x50) },
775 { I2C_BOARD_INFO("isl1208", 0x6f) },
776};
777
778static mfp_cfg_t zeus_pin_config[] __initdata = {
779 /* AC97 */
780 GPIO28_AC97_BITCLK,
781 GPIO29_AC97_SDATA_IN_0,
782 GPIO30_AC97_SDATA_OUT,
783 GPIO31_AC97_SYNC,
784
785 GPIO15_nCS_1,
786 GPIO78_nCS_2,
787 GPIO80_nCS_4,
788 GPIO33_nCS_5,
789
790 GPIO22_GPIO,
791 GPIO32_MMC_CLK,
792 GPIO92_MMC_DAT_0,
793 GPIO109_MMC_DAT_1,
794 GPIO110_MMC_DAT_2,
795 GPIO111_MMC_DAT_3,
796 GPIO112_MMC_CMD,
797
798 GPIO88_USBH1_PWR,
799 GPIO89_USBH1_PEN,
800 GPIO119_USBH2_PWR,
801 GPIO120_USBH2_PEN,
802
803 GPIO86_LCD_LDD_16,
804 GPIO87_LCD_LDD_17,
805
806 GPIO102_GPIO,
807 GPIO104_CIF_DD_2,
808 GPIO105_CIF_DD_1,
809
810 GPIO81_SSP3_TXD,
811 GPIO82_SSP3_RXD,
812 GPIO83_SSP3_SFRM,
813 GPIO84_SSP3_SCLK,
814
815 GPIO48_nPOE,
816 GPIO49_nPWE,
817 GPIO50_nPIOR,
818 GPIO51_nPIOW,
819 GPIO85_nPCE_1,
820 GPIO54_nPCE_2,
821 GPIO79_PSKTSEL,
822 GPIO55_nPREG,
823 GPIO56_nPWAIT,
824 GPIO57_nIOIS16,
825 GPIO36_GPIO, /* CF CD */
826 GPIO97_GPIO, /* CF PWREN */
827 GPIO99_GPIO, /* CF RDY */
828};
829
830/*
831 * DM9k MSCx settings: SRAM, 16 bits
832 * 17 cycles delay first access
833 * 5 cycles delay next access
834 * 13 cycles recovery time
835 * faster device
836 */
837#define DM9K_MSC_VALUE 0xe4c9
838
839static void __init zeus_init(void)
840{
841 u16 dm9000_msc = DM9K_MSC_VALUE;
842 u32 msc0, msc1;
843
844 system_rev = __raw_readw(ZEUS_CPLD_VERSION);
845 pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
846
847 /* Fix timings for dm9000s (CS1/CS2)*/
848 msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
849 msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
850 __raw_writel(msc0, MSC0);
851 __raw_writel(msc1, MSC1);
852
853 pm_power_off = zeus_power_off;
854 zeus_setup_apm();
855
856 pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
857
858 platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
859
860 zeus_register_ohci();
861
862 if (zeus_setup_fb_gpios())
863 pr_err("Failed to setup fb gpios\n");
864 else
865 pxa_set_fb_info(NULL, &zeus_fb_info);
866
867 pxa_set_mci_info(&zeus_mci_platform_data);
868 pxa_set_udc_info(&zeus_udc_info);
869 pxa_set_ac97_info(&zeus_ac97_info);
870 pxa_set_i2c_info(NULL);
871 i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
872 pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
873 spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
874
875 regulator_has_full_constraints();
876}
877
878static struct map_desc zeus_io_desc[] __initdata = {
879 {
880 .virtual = (unsigned long)ZEUS_CPLD_VERSION,
881 .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
882 .length = 0x1000,
883 .type = MT_DEVICE,
884 },
885 {
886 .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ,
887 .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
888 .length = 0x1000,
889 .type = MT_DEVICE,
890 },
891 {
892 .virtual = (unsigned long)ZEUS_CPLD_CONTROL,
893 .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
894 .length = 0x1000,
895 .type = MT_DEVICE,
896 },
897 {
898 .virtual = (unsigned long)ZEUS_PC104IO,
899 .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS),
900 .length = 0x00800000,
901 .type = MT_DEVICE,
902 },
903};
904
905static void __init zeus_map_io(void)
906{
907 pxa27x_map_io();
908
909 iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
910
911 /* Clear PSPR to ensure a full restart on wake-up. */
912 PMCR = PSPR = 0;
913
914 /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
915 writel(readl(OSCC) | OSCC_OON, OSCC);
916
917 /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
918 * float chip selects and PCMCIA */
919 PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
920}
921
922MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
923 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
924 .atag_offset = 0x100,
925 .map_io = zeus_map_io,
926 .nr_irqs = ZEUS_NR_IRQS,
927 .init_irq = zeus_init_irq,
928 .handle_irq = pxa27x_handle_irq,
929 .init_time = pxa_timer_init,
930 .init_machine = zeus_init,
931 .restart = pxa_restart,
932MACHINE_END
933