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1/*
2 * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
3 *
4 * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
14#define __ARCH_ARM_MACH_OMAP2_PRM_H
15
16#include "prcm-common.h"
17
18# ifndef __ASSEMBLER__
19extern void __iomem *prm_base;
20extern void omap2_set_globals_prm(void __iomem *prm);
21int of_prcm_init(void);
22# endif
23
24
25/*
26 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
27 * module to softreset
28 */
29#define MAX_MODULE_SOFTRESET_WAIT 10000
30
31/*
32 * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
33 * submodule to exit hardreset
34 */
35#define MAX_MODULE_HARDRESET_WAIT 10000
36
37/*
38 * Register bitfields
39 */
40
41/*
42 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
43 *
44 * 2430: PM_PWSTST_MDM
45 *
46 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
47 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
48 * PM_PWSTST_NEON
49 */
50#define OMAP_INTRANSITION_MASK (1 << 20)
51
52
53/*
54 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
55 *
56 * 2430: PM_PWSTST_MDM
57 *
58 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
59 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
60 * PM_PWSTST_NEON
61 */
62#define OMAP_POWERSTATEST_SHIFT 0
63#define OMAP_POWERSTATEST_MASK (0x3 << 0)
64
65/*
66 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
67 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
68 *
69 * 2430: PM_PWSTCTRL_MDM shared bits
70 *
71 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
72 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
73 * PM_PWSTCTRL_NEON shared bits
74 */
75#define OMAP_POWERSTATE_SHIFT 0
76#define OMAP_POWERSTATE_MASK (0x3 << 0)
77
78/*
79 * Standardized OMAP reset source bits
80 *
81 * To the extent these happen to match the hardware register bit
82 * shifts, it's purely coincidental. Used by omap-wdt.c.
83 * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever
84 * there are any bits remaining in the global PRM_RSTST register that
85 * haven't been identified, or when the PRM code for the current SoC
86 * doesn't know how to interpret the register.
87 */
88#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0
89#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1
90#define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT 2
91#define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3
92#define OMAP_SECU_WD_RST_SRC_ID_SHIFT 4
93#define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5
94#define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT 6
95#define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT 7
96#define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT 8
97#define OMAP_ICEPICK_RST_SRC_ID_SHIFT 9
98#define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT 10
99#define OMAP_C2C_RST_SRC_ID_SHIFT 11
100#define OMAP_UNKNOWN_RST_SRC_ID_SHIFT 12
101
102#ifndef __ASSEMBLER__
103
104/**
105 * struct prm_reset_src_map - map register bitshifts to standard bitshifts
106 * @reg_shift: bitshift in the PRM reset source register
107 * @std_shift: bitshift equivalent in the standard reset source list
108 *
109 * The fields are signed because -1 is used as a terminator.
110 */
111struct prm_reset_src_map {
112 s8 reg_shift;
113 s8 std_shift;
114};
115
116/**
117 * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations
118 * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
119 * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
120 * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
121 *
122 * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
123 * deprecated.
124 */
125struct prm_ll_data {
126 u32 (*read_reset_sources)(void);
127 bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
128 void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
129};
130
131extern int prm_register(struct prm_ll_data *pld);
132extern int prm_unregister(struct prm_ll_data *pld);
133
134extern u32 prm_read_reset_sources(void);
135extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
136extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
137
138#endif
139
140
141#endif
1/*
2 * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
3 *
4 * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
14#define __ARCH_ARM_MACH_OMAP2_PRM_H
15
16#include "prcm-common.h"
17
18# ifndef __ASSEMBLER__
19extern struct omap_domain_base prm_base;
20extern u16 prm_features;
21extern void omap2_set_globals_prm(void __iomem *prm);
22int omap_prcm_init(void);
23int omap2_prm_base_init(void);
24int omap2_prcm_base_init(void);
25# endif
26
27/*
28 * prm_features flag values
29 *
30 * PRM_HAS_IO_WAKEUP: has IO wakeup capability
31 * PRM_HAS_VOLTAGE: has voltage domains
32 */
33#define PRM_HAS_IO_WAKEUP BIT(0)
34#define PRM_HAS_VOLTAGE BIT(1)
35
36/*
37 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
38 * module to softreset
39 */
40#define MAX_MODULE_SOFTRESET_WAIT 10000
41
42/*
43 * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
44 * submodule to exit hardreset
45 */
46#define MAX_MODULE_HARDRESET_WAIT 10000
47
48/*
49 * Register bitfields
50 */
51
52/*
53 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
54 *
55 * 2430: PM_PWSTST_MDM
56 *
57 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
58 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
59 * PM_PWSTST_NEON
60 */
61#define OMAP_INTRANSITION_MASK (1 << 20)
62
63
64/*
65 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
66 *
67 * 2430: PM_PWSTST_MDM
68 *
69 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
70 * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
71 * PM_PWSTST_NEON
72 */
73#define OMAP_POWERSTATEST_SHIFT 0
74#define OMAP_POWERSTATEST_MASK (0x3 << 0)
75
76/*
77 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
78 * PM_PWSTCTRL_DSP, PM_PWSTST_MPU
79 *
80 * 2430: PM_PWSTCTRL_MDM shared bits
81 *
82 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
83 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
84 * PM_PWSTCTRL_NEON shared bits
85 */
86#define OMAP_POWERSTATE_SHIFT 0
87#define OMAP_POWERSTATE_MASK (0x3 << 0)
88
89/*
90 * Standardized OMAP reset source bits
91 *
92 * To the extent these happen to match the hardware register bit
93 * shifts, it's purely coincidental. Used by omap-wdt.c.
94 * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever
95 * there are any bits remaining in the global PRM_RSTST register that
96 * haven't been identified, or when the PRM code for the current SoC
97 * doesn't know how to interpret the register.
98 */
99#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0
100#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1
101#define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT 2
102#define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3
103#define OMAP_SECU_WD_RST_SRC_ID_SHIFT 4
104#define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5
105#define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT 6
106#define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT 7
107#define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT 8
108#define OMAP_ICEPICK_RST_SRC_ID_SHIFT 9
109#define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT 10
110#define OMAP_C2C_RST_SRC_ID_SHIFT 11
111#define OMAP_UNKNOWN_RST_SRC_ID_SHIFT 12
112
113#ifndef __ASSEMBLER__
114
115/**
116 * struct prm_reset_src_map - map register bitshifts to standard bitshifts
117 * @reg_shift: bitshift in the PRM reset source register
118 * @std_shift: bitshift equivalent in the standard reset source list
119 *
120 * The fields are signed because -1 is used as a terminator.
121 */
122struct prm_reset_src_map {
123 s8 reg_shift;
124 s8 std_shift;
125};
126
127/**
128 * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations
129 * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
130 * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
131 * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
132 * @late_init: ptr to the late init function
133 * @assert_hardreset: ptr to the SoC PRM hardreset assert impl
134 * @deassert_hardreset: ptr to the SoC PRM hardreset deassert impl
135 *
136 * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
137 * deprecated.
138 */
139struct prm_ll_data {
140 u32 (*read_reset_sources)(void);
141 bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
142 void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
143 int (*late_init)(void);
144 int (*assert_hardreset)(u8 shift, u8 part, s16 prm_mod, u16 offset);
145 int (*deassert_hardreset)(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
146 u16 offset, u16 st_offset);
147 int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod,
148 u16 offset);
149 void (*reset_system)(void);
150 int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask);
151 u32 (*vp_check_txdone)(u8 vp_id);
152 void (*vp_clear_txdone)(u8 vp_id);
153};
154
155extern int prm_register(struct prm_ll_data *pld);
156extern int prm_unregister(struct prm_ll_data *pld);
157
158int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset);
159int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
160 u16 offset, u16 st_offset);
161int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
162extern u32 prm_read_reset_sources(void);
163extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
164extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
165void omap_prm_reset_system(void);
166
167void omap_prm_reconfigure_io_chain(void);
168int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
169
170/*
171 * Voltage Processor (VP) identifiers
172 */
173#define OMAP3_VP_VDD_MPU_ID 0
174#define OMAP3_VP_VDD_CORE_ID 1
175#define OMAP4_VP_VDD_CORE_ID 0
176#define OMAP4_VP_VDD_IVA_ID 1
177#define OMAP4_VP_VDD_MPU_ID 2
178
179u32 omap_prm_vp_check_txdone(u8 vp_id);
180void omap_prm_vp_clear_txdone(u8 vp_id);
181
182#endif
183
184
185#endif