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1/*
2 * linux/arch/arm/mach-omap1/devices.c
3 *
4 * OMAP1 platform device setup/initialization
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/spi/spi.h>
19
20#include <linux/platform_data/omap-wd-timer.h>
21
22#include <asm/mach/map.h>
23
24#include <mach/tc.h>
25#include <mach/mux.h>
26
27#include <mach/omap7xx.h>
28#include <mach/camera.h>
29#include <mach/hardware.h>
30
31#include "common.h"
32#include "clock.h"
33#include "mmc.h"
34#include "sram.h"
35
36#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
37
38static struct platform_device omap_pcm = {
39 .name = "omap-pcm-audio",
40 .id = -1,
41};
42
43static void omap_init_audio(void)
44{
45 platform_device_register(&omap_pcm);
46}
47
48#else
49static inline void omap_init_audio(void) {}
50#endif
51
52/*-------------------------------------------------------------------------*/
53
54#if defined(CONFIG_RTC_DRV_OMAP) || defined(CONFIG_RTC_DRV_OMAP_MODULE)
55
56#define OMAP_RTC_BASE 0xfffb4800
57
58static struct resource rtc_resources[] = {
59 {
60 .start = OMAP_RTC_BASE,
61 .end = OMAP_RTC_BASE + 0x5f,
62 .flags = IORESOURCE_MEM,
63 },
64 {
65 .start = INT_RTC_TIMER,
66 .flags = IORESOURCE_IRQ,
67 },
68 {
69 .start = INT_RTC_ALARM,
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74static struct platform_device omap_rtc_device = {
75 .name = "omap_rtc",
76 .id = -1,
77 .num_resources = ARRAY_SIZE(rtc_resources),
78 .resource = rtc_resources,
79};
80
81static void omap_init_rtc(void)
82{
83 (void) platform_device_register(&omap_rtc_device);
84}
85#else
86static inline void omap_init_rtc(void) {}
87#endif
88
89static inline void omap_init_mbox(void) { }
90
91/*-------------------------------------------------------------------------*/
92
93#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
94
95static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
96 int controller_nr)
97{
98 if (controller_nr == 0) {
99 if (cpu_is_omap7xx()) {
100 omap_cfg_reg(MMC_7XX_CMD);
101 omap_cfg_reg(MMC_7XX_CLK);
102 omap_cfg_reg(MMC_7XX_DAT0);
103 } else {
104 omap_cfg_reg(MMC_CMD);
105 omap_cfg_reg(MMC_CLK);
106 omap_cfg_reg(MMC_DAT0);
107 }
108
109 if (cpu_is_omap1710()) {
110 omap_cfg_reg(M15_1710_MMC_CLKI);
111 omap_cfg_reg(P19_1710_MMC_CMDDIR);
112 omap_cfg_reg(P20_1710_MMC_DATDIR0);
113 }
114 if (mmc_controller->slots[0].wires == 4 && !cpu_is_omap7xx()) {
115 omap_cfg_reg(MMC_DAT1);
116 /* NOTE: DAT2 can be on W10 (here) or M15 */
117 if (!mmc_controller->slots[0].nomux)
118 omap_cfg_reg(MMC_DAT2);
119 omap_cfg_reg(MMC_DAT3);
120 }
121 }
122
123 /* Block 2 is on newer chips, and has many pinout options */
124 if (cpu_is_omap16xx() && controller_nr == 1) {
125 if (!mmc_controller->slots[1].nomux) {
126 omap_cfg_reg(Y8_1610_MMC2_CMD);
127 omap_cfg_reg(Y10_1610_MMC2_CLK);
128 omap_cfg_reg(R18_1610_MMC2_CLKIN);
129 omap_cfg_reg(W8_1610_MMC2_DAT0);
130 if (mmc_controller->slots[1].wires == 4) {
131 omap_cfg_reg(V8_1610_MMC2_DAT1);
132 omap_cfg_reg(W15_1610_MMC2_DAT2);
133 omap_cfg_reg(R10_1610_MMC2_DAT3);
134 }
135
136 /* These are needed for the level shifter */
137 omap_cfg_reg(V9_1610_MMC2_CMDDIR);
138 omap_cfg_reg(V5_1610_MMC2_DATDIR0);
139 omap_cfg_reg(W19_1610_MMC2_DATDIR1);
140 }
141
142 /* Feedback clock must be set on OMAP-1710 MMC2 */
143 if (cpu_is_omap1710())
144 omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
145 MOD_CONF_CTRL_1);
146 }
147}
148
149#define OMAP_MMC_NR_RES 4
150
151/*
152 * Register MMC devices.
153 */
154static int __init omap_mmc_add(const char *name, int id, unsigned long base,
155 unsigned long size, unsigned int irq,
156 unsigned rx_req, unsigned tx_req,
157 struct omap_mmc_platform_data *data)
158{
159 struct platform_device *pdev;
160 struct resource res[OMAP_MMC_NR_RES];
161 int ret;
162
163 pdev = platform_device_alloc(name, id);
164 if (!pdev)
165 return -ENOMEM;
166
167 memset(res, 0, OMAP_MMC_NR_RES * sizeof(struct resource));
168 res[0].start = base;
169 res[0].end = base + size - 1;
170 res[0].flags = IORESOURCE_MEM;
171 res[1].start = res[1].end = irq;
172 res[1].flags = IORESOURCE_IRQ;
173 res[2].start = rx_req;
174 res[2].name = "rx";
175 res[2].flags = IORESOURCE_DMA;
176 res[3].start = tx_req;
177 res[3].name = "tx";
178 res[3].flags = IORESOURCE_DMA;
179
180 if (cpu_is_omap7xx())
181 data->slots[0].features = MMC_OMAP7XX;
182 if (cpu_is_omap15xx())
183 data->slots[0].features = MMC_OMAP15XX;
184 if (cpu_is_omap16xx())
185 data->slots[0].features = MMC_OMAP16XX;
186
187 ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
188 if (ret == 0)
189 ret = platform_device_add_data(pdev, data, sizeof(*data));
190 if (ret)
191 goto fail;
192
193 ret = platform_device_add(pdev);
194 if (ret)
195 goto fail;
196
197 /* return device handle to board setup code */
198 data->dev = &pdev->dev;
199 return 0;
200
201fail:
202 platform_device_put(pdev);
203 return ret;
204}
205
206void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
207 int nr_controllers)
208{
209 int i;
210
211 for (i = 0; i < nr_controllers; i++) {
212 unsigned long base, size;
213 unsigned rx_req, tx_req;
214 unsigned int irq = 0;
215
216 if (!mmc_data[i])
217 continue;
218
219 omap1_mmc_mux(mmc_data[i], i);
220
221 switch (i) {
222 case 0:
223 base = OMAP1_MMC1_BASE;
224 irq = INT_MMC;
225 rx_req = 22;
226 tx_req = 21;
227 break;
228 case 1:
229 if (!cpu_is_omap16xx())
230 return;
231 base = OMAP1_MMC2_BASE;
232 irq = INT_1610_MMC2;
233 rx_req = 55;
234 tx_req = 54;
235 break;
236 default:
237 continue;
238 }
239 size = OMAP1_MMC_SIZE;
240
241 omap_mmc_add("mmci-omap", i, base, size, irq,
242 rx_req, tx_req, mmc_data[i]);
243 }
244}
245
246#endif
247
248/*-------------------------------------------------------------------------*/
249
250/* OMAP7xx SPI support */
251#if defined(CONFIG_SPI_OMAP_100K) || defined(CONFIG_SPI_OMAP_100K_MODULE)
252
253struct platform_device omap_spi1 = {
254 .name = "omap1_spi100k",
255 .id = 1,
256};
257
258struct platform_device omap_spi2 = {
259 .name = "omap1_spi100k",
260 .id = 2,
261};
262
263static void omap_init_spi100k(void)
264{
265 omap_spi1.dev.platform_data = ioremap(OMAP7XX_SPI1_BASE, 0x7ff);
266 if (omap_spi1.dev.platform_data)
267 platform_device_register(&omap_spi1);
268
269 omap_spi2.dev.platform_data = ioremap(OMAP7XX_SPI2_BASE, 0x7ff);
270 if (omap_spi2.dev.platform_data)
271 platform_device_register(&omap_spi2);
272}
273
274#else
275static inline void omap_init_spi100k(void)
276{
277}
278#endif
279
280
281#define OMAP1_CAMERA_BASE 0xfffb6800
282#define OMAP1_CAMERA_IOSIZE 0x1c
283
284static struct resource omap1_camera_resources[] = {
285 [0] = {
286 .start = OMAP1_CAMERA_BASE,
287 .end = OMAP1_CAMERA_BASE + OMAP1_CAMERA_IOSIZE - 1,
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
291 .start = INT_CAMERA,
292 .flags = IORESOURCE_IRQ,
293 },
294};
295
296static u64 omap1_camera_dma_mask = DMA_BIT_MASK(32);
297
298static struct platform_device omap1_camera_device = {
299 .name = "omap1-camera",
300 .id = 0, /* This is used to put cameras on this interface */
301 .dev = {
302 .dma_mask = &omap1_camera_dma_mask,
303 .coherent_dma_mask = DMA_BIT_MASK(32),
304 },
305 .num_resources = ARRAY_SIZE(omap1_camera_resources),
306 .resource = omap1_camera_resources,
307};
308
309void __init omap1_camera_init(void *info)
310{
311 struct platform_device *dev = &omap1_camera_device;
312 int ret;
313
314 dev->dev.platform_data = info;
315
316 ret = platform_device_register(dev);
317 if (ret)
318 dev_err(&dev->dev, "unable to register device: %d\n", ret);
319}
320
321
322/*-------------------------------------------------------------------------*/
323
324static inline void omap_init_sti(void) {}
325
326/* Numbering for the SPI-capable controllers when used for SPI:
327 * spi = 1
328 * uwire = 2
329 * mmc1..2 = 3..4
330 * mcbsp1..3 = 5..7
331 */
332
333#if defined(CONFIG_SPI_OMAP_UWIRE) || defined(CONFIG_SPI_OMAP_UWIRE_MODULE)
334
335#define OMAP_UWIRE_BASE 0xfffb3000
336
337static struct resource uwire_resources[] = {
338 {
339 .start = OMAP_UWIRE_BASE,
340 .end = OMAP_UWIRE_BASE + 0x20,
341 .flags = IORESOURCE_MEM,
342 },
343};
344
345static struct platform_device omap_uwire_device = {
346 .name = "omap_uwire",
347 .id = -1,
348 .num_resources = ARRAY_SIZE(uwire_resources),
349 .resource = uwire_resources,
350};
351
352static void omap_init_uwire(void)
353{
354 /* FIXME define and use a boot tag; not all boards will be hooking
355 * up devices to the microwire controller, and multi-board configs
356 * mean that CONFIG_SPI_OMAP_UWIRE may be configured anyway...
357 */
358
359 /* board-specific code must configure chipselects (only a few
360 * are normally used) and SCLK/SDI/SDO (each has two choices).
361 */
362 (void) platform_device_register(&omap_uwire_device);
363}
364#else
365static inline void omap_init_uwire(void) {}
366#endif
367
368
369#define OMAP1_RNG_BASE 0xfffe5000
370
371static struct resource omap1_rng_resources[] = {
372 {
373 .start = OMAP1_RNG_BASE,
374 .end = OMAP1_RNG_BASE + 0x4f,
375 .flags = IORESOURCE_MEM,
376 },
377};
378
379static struct platform_device omap1_rng_device = {
380 .name = "omap_rng",
381 .id = -1,
382 .num_resources = ARRAY_SIZE(omap1_rng_resources),
383 .resource = omap1_rng_resources,
384};
385
386static void omap1_init_rng(void)
387{
388 if (!cpu_is_omap16xx())
389 return;
390
391 (void) platform_device_register(&omap1_rng_device);
392}
393
394/*-------------------------------------------------------------------------*/
395
396/*
397 * This gets called after board-specific INIT_MACHINE, and initializes most
398 * on-chip peripherals accessible on this board (except for few like USB):
399 *
400 * (a) Does any "standard config" pin muxing needed. Board-specific
401 * code will have muxed GPIO pins and done "nonstandard" setup;
402 * that code could live in the boot loader.
403 * (b) Populating board-specific platform_data with the data drivers
404 * rely on to handle wiring variations.
405 * (c) Creating platform devices as meaningful on this board and
406 * with this kernel configuration.
407 *
408 * Claiming GPIOs, and setting their direction and initial values, is the
409 * responsibility of the device drivers. So is responding to probe().
410 *
411 * Board-specific knowledge like creating devices or pin setup is to be
412 * kept out of drivers as much as possible. In particular, pin setup
413 * may be handled by the boot loader, and drivers should expect it will
414 * normally have been done by the time they're probed.
415 */
416static int __init omap1_init_devices(void)
417{
418 if (!cpu_class_is_omap1())
419 return -ENODEV;
420
421 omap_sram_init();
422 omap1_clk_late_init();
423
424 /* please keep these calls, and their implementations above,
425 * in alphabetical order so they're easier to sort through.
426 */
427
428 omap_init_audio();
429 omap_init_mbox();
430 omap_init_rtc();
431 omap_init_spi100k();
432 omap_init_sti();
433 omap_init_uwire();
434 omap1_init_rng();
435
436 return 0;
437}
438arch_initcall(omap1_init_devices);
439
440#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
441
442static struct resource wdt_resources[] = {
443 {
444 .start = 0xfffeb000,
445 .end = 0xfffeb07F,
446 .flags = IORESOURCE_MEM,
447 },
448};
449
450static struct platform_device omap_wdt_device = {
451 .name = "omap_wdt",
452 .id = -1,
453 .num_resources = ARRAY_SIZE(wdt_resources),
454 .resource = wdt_resources,
455};
456
457static int __init omap_init_wdt(void)
458{
459 struct omap_wd_timer_platform_data pdata;
460 int ret;
461
462 if (!cpu_is_omap16xx())
463 return -ENODEV;
464
465 pdata.read_reset_sources = omap1_get_reset_sources;
466
467 ret = platform_device_register(&omap_wdt_device);
468 if (!ret) {
469 ret = platform_device_add_data(&omap_wdt_device, &pdata,
470 sizeof(pdata));
471 if (ret)
472 platform_device_del(&omap_wdt_device);
473 }
474
475 return ret;
476}
477subsys_initcall(omap_init_wdt);
478#endif
1/*
2 * linux/arch/arm/mach-omap1/devices.c
3 *
4 * OMAP1 platform device setup/initialization
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/spi/spi.h>
19
20#include <linux/platform_data/omap-wd-timer.h>
21
22#include <asm/mach/map.h>
23
24#include <mach/tc.h>
25#include <mach/mux.h>
26
27#include <mach/omap7xx.h>
28#include "camera.h"
29#include <mach/hardware.h>
30
31#include "common.h"
32#include "clock.h"
33#include "mmc.h"
34#include "sram.h"
35
36#if IS_ENABLED(CONFIG_RTC_DRV_OMAP)
37
38#define OMAP_RTC_BASE 0xfffb4800
39
40static struct resource rtc_resources[] = {
41 {
42 .start = OMAP_RTC_BASE,
43 .end = OMAP_RTC_BASE + 0x5f,
44 .flags = IORESOURCE_MEM,
45 },
46 {
47 .start = INT_RTC_TIMER,
48 .flags = IORESOURCE_IRQ,
49 },
50 {
51 .start = INT_RTC_ALARM,
52 .flags = IORESOURCE_IRQ,
53 },
54};
55
56static struct platform_device omap_rtc_device = {
57 .name = "omap_rtc",
58 .id = -1,
59 .num_resources = ARRAY_SIZE(rtc_resources),
60 .resource = rtc_resources,
61};
62
63static void omap_init_rtc(void)
64{
65 (void) platform_device_register(&omap_rtc_device);
66}
67#else
68static inline void omap_init_rtc(void) {}
69#endif
70
71static inline void omap_init_mbox(void) { }
72
73/*-------------------------------------------------------------------------*/
74
75#if IS_ENABLED(CONFIG_MMC_OMAP)
76
77static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
78 int controller_nr)
79{
80 if (controller_nr == 0) {
81 if (cpu_is_omap7xx()) {
82 omap_cfg_reg(MMC_7XX_CMD);
83 omap_cfg_reg(MMC_7XX_CLK);
84 omap_cfg_reg(MMC_7XX_DAT0);
85 } else {
86 omap_cfg_reg(MMC_CMD);
87 omap_cfg_reg(MMC_CLK);
88 omap_cfg_reg(MMC_DAT0);
89 }
90
91 if (cpu_is_omap1710()) {
92 omap_cfg_reg(M15_1710_MMC_CLKI);
93 omap_cfg_reg(P19_1710_MMC_CMDDIR);
94 omap_cfg_reg(P20_1710_MMC_DATDIR0);
95 }
96 if (mmc_controller->slots[0].wires == 4 && !cpu_is_omap7xx()) {
97 omap_cfg_reg(MMC_DAT1);
98 /* NOTE: DAT2 can be on W10 (here) or M15 */
99 if (!mmc_controller->slots[0].nomux)
100 omap_cfg_reg(MMC_DAT2);
101 omap_cfg_reg(MMC_DAT3);
102 }
103 }
104
105 /* Block 2 is on newer chips, and has many pinout options */
106 if (cpu_is_omap16xx() && controller_nr == 1) {
107 if (!mmc_controller->slots[1].nomux) {
108 omap_cfg_reg(Y8_1610_MMC2_CMD);
109 omap_cfg_reg(Y10_1610_MMC2_CLK);
110 omap_cfg_reg(R18_1610_MMC2_CLKIN);
111 omap_cfg_reg(W8_1610_MMC2_DAT0);
112 if (mmc_controller->slots[1].wires == 4) {
113 omap_cfg_reg(V8_1610_MMC2_DAT1);
114 omap_cfg_reg(W15_1610_MMC2_DAT2);
115 omap_cfg_reg(R10_1610_MMC2_DAT3);
116 }
117
118 /* These are needed for the level shifter */
119 omap_cfg_reg(V9_1610_MMC2_CMDDIR);
120 omap_cfg_reg(V5_1610_MMC2_DATDIR0);
121 omap_cfg_reg(W19_1610_MMC2_DATDIR1);
122 }
123
124 /* Feedback clock must be set on OMAP-1710 MMC2 */
125 if (cpu_is_omap1710())
126 omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
127 MOD_CONF_CTRL_1);
128 }
129}
130
131#define OMAP_MMC_NR_RES 4
132
133/*
134 * Register MMC devices.
135 */
136static int __init omap_mmc_add(const char *name, int id, unsigned long base,
137 unsigned long size, unsigned int irq,
138 unsigned rx_req, unsigned tx_req,
139 struct omap_mmc_platform_data *data)
140{
141 struct platform_device *pdev;
142 struct resource res[OMAP_MMC_NR_RES];
143 int ret;
144
145 pdev = platform_device_alloc(name, id);
146 if (!pdev)
147 return -ENOMEM;
148
149 memset(res, 0, OMAP_MMC_NR_RES * sizeof(struct resource));
150 res[0].start = base;
151 res[0].end = base + size - 1;
152 res[0].flags = IORESOURCE_MEM;
153 res[1].start = res[1].end = irq;
154 res[1].flags = IORESOURCE_IRQ;
155 res[2].start = rx_req;
156 res[2].name = "rx";
157 res[2].flags = IORESOURCE_DMA;
158 res[3].start = tx_req;
159 res[3].name = "tx";
160 res[3].flags = IORESOURCE_DMA;
161
162 if (cpu_is_omap7xx())
163 data->slots[0].features = MMC_OMAP7XX;
164 if (cpu_is_omap15xx())
165 data->slots[0].features = MMC_OMAP15XX;
166 if (cpu_is_omap16xx())
167 data->slots[0].features = MMC_OMAP16XX;
168
169 ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
170 if (ret == 0)
171 ret = platform_device_add_data(pdev, data, sizeof(*data));
172 if (ret)
173 goto fail;
174
175 ret = platform_device_add(pdev);
176 if (ret)
177 goto fail;
178
179 /* return device handle to board setup code */
180 data->dev = &pdev->dev;
181 return 0;
182
183fail:
184 platform_device_put(pdev);
185 return ret;
186}
187
188void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
189 int nr_controllers)
190{
191 int i;
192
193 for (i = 0; i < nr_controllers; i++) {
194 unsigned long base, size;
195 unsigned rx_req, tx_req;
196 unsigned int irq = 0;
197
198 if (!mmc_data[i])
199 continue;
200
201 omap1_mmc_mux(mmc_data[i], i);
202
203 switch (i) {
204 case 0:
205 base = OMAP1_MMC1_BASE;
206 irq = INT_MMC;
207 rx_req = 22;
208 tx_req = 21;
209 break;
210 case 1:
211 if (!cpu_is_omap16xx())
212 return;
213 base = OMAP1_MMC2_BASE;
214 irq = INT_1610_MMC2;
215 rx_req = 55;
216 tx_req = 54;
217 break;
218 default:
219 continue;
220 }
221 size = OMAP1_MMC_SIZE;
222
223 omap_mmc_add("mmci-omap", i, base, size, irq,
224 rx_req, tx_req, mmc_data[i]);
225 }
226}
227
228#endif
229
230/*-------------------------------------------------------------------------*/
231
232/* OMAP7xx SPI support */
233#if IS_ENABLED(CONFIG_SPI_OMAP_100K)
234
235struct platform_device omap_spi1 = {
236 .name = "omap1_spi100k",
237 .id = 1,
238};
239
240struct platform_device omap_spi2 = {
241 .name = "omap1_spi100k",
242 .id = 2,
243};
244
245static void omap_init_spi100k(void)
246{
247 omap_spi1.dev.platform_data = ioremap(OMAP7XX_SPI1_BASE, 0x7ff);
248 if (omap_spi1.dev.platform_data)
249 platform_device_register(&omap_spi1);
250
251 omap_spi2.dev.platform_data = ioremap(OMAP7XX_SPI2_BASE, 0x7ff);
252 if (omap_spi2.dev.platform_data)
253 platform_device_register(&omap_spi2);
254}
255
256#else
257static inline void omap_init_spi100k(void)
258{
259}
260#endif
261
262
263#define OMAP1_CAMERA_BASE 0xfffb6800
264#define OMAP1_CAMERA_IOSIZE 0x1c
265
266static struct resource omap1_camera_resources[] = {
267 [0] = {
268 .start = OMAP1_CAMERA_BASE,
269 .end = OMAP1_CAMERA_BASE + OMAP1_CAMERA_IOSIZE - 1,
270 .flags = IORESOURCE_MEM,
271 },
272 [1] = {
273 .start = INT_CAMERA,
274 .flags = IORESOURCE_IRQ,
275 },
276};
277
278static u64 omap1_camera_dma_mask = DMA_BIT_MASK(32);
279
280static struct platform_device omap1_camera_device = {
281 .name = "omap1-camera",
282 .id = 0, /* This is used to put cameras on this interface */
283 .dev = {
284 .dma_mask = &omap1_camera_dma_mask,
285 .coherent_dma_mask = DMA_BIT_MASK(32),
286 },
287 .num_resources = ARRAY_SIZE(omap1_camera_resources),
288 .resource = omap1_camera_resources,
289};
290
291void __init omap1_camera_init(void *info)
292{
293 struct platform_device *dev = &omap1_camera_device;
294 int ret;
295
296 dev->dev.platform_data = info;
297
298 ret = platform_device_register(dev);
299 if (ret)
300 dev_err(&dev->dev, "unable to register device: %d\n", ret);
301}
302
303
304/*-------------------------------------------------------------------------*/
305
306static inline void omap_init_sti(void) {}
307
308/* Numbering for the SPI-capable controllers when used for SPI:
309 * spi = 1
310 * uwire = 2
311 * mmc1..2 = 3..4
312 * mcbsp1..3 = 5..7
313 */
314
315#if IS_ENABLED(CONFIG_SPI_OMAP_UWIRE)
316
317#define OMAP_UWIRE_BASE 0xfffb3000
318
319static struct resource uwire_resources[] = {
320 {
321 .start = OMAP_UWIRE_BASE,
322 .end = OMAP_UWIRE_BASE + 0x20,
323 .flags = IORESOURCE_MEM,
324 },
325};
326
327static struct platform_device omap_uwire_device = {
328 .name = "omap_uwire",
329 .id = -1,
330 .num_resources = ARRAY_SIZE(uwire_resources),
331 .resource = uwire_resources,
332};
333
334static void omap_init_uwire(void)
335{
336 /* FIXME define and use a boot tag; not all boards will be hooking
337 * up devices to the microwire controller, and multi-board configs
338 * mean that CONFIG_SPI_OMAP_UWIRE may be configured anyway...
339 */
340
341 /* board-specific code must configure chipselects (only a few
342 * are normally used) and SCLK/SDI/SDO (each has two choices).
343 */
344 (void) platform_device_register(&omap_uwire_device);
345}
346#else
347static inline void omap_init_uwire(void) {}
348#endif
349
350
351#define OMAP1_RNG_BASE 0xfffe5000
352
353static struct resource omap1_rng_resources[] = {
354 {
355 .start = OMAP1_RNG_BASE,
356 .end = OMAP1_RNG_BASE + 0x4f,
357 .flags = IORESOURCE_MEM,
358 },
359};
360
361static struct platform_device omap1_rng_device = {
362 .name = "omap_rng",
363 .id = -1,
364 .num_resources = ARRAY_SIZE(omap1_rng_resources),
365 .resource = omap1_rng_resources,
366};
367
368static void omap1_init_rng(void)
369{
370 if (!cpu_is_omap16xx())
371 return;
372
373 (void) platform_device_register(&omap1_rng_device);
374}
375
376/*-------------------------------------------------------------------------*/
377
378/*
379 * This gets called after board-specific INIT_MACHINE, and initializes most
380 * on-chip peripherals accessible on this board (except for few like USB):
381 *
382 * (a) Does any "standard config" pin muxing needed. Board-specific
383 * code will have muxed GPIO pins and done "nonstandard" setup;
384 * that code could live in the boot loader.
385 * (b) Populating board-specific platform_data with the data drivers
386 * rely on to handle wiring variations.
387 * (c) Creating platform devices as meaningful on this board and
388 * with this kernel configuration.
389 *
390 * Claiming GPIOs, and setting their direction and initial values, is the
391 * responsibility of the device drivers. So is responding to probe().
392 *
393 * Board-specific knowledge like creating devices or pin setup is to be
394 * kept out of drivers as much as possible. In particular, pin setup
395 * may be handled by the boot loader, and drivers should expect it will
396 * normally have been done by the time they're probed.
397 */
398static int __init omap1_init_devices(void)
399{
400 if (!cpu_class_is_omap1())
401 return -ENODEV;
402
403 omap_sram_init();
404 omap1_clk_late_init();
405
406 /* please keep these calls, and their implementations above,
407 * in alphabetical order so they're easier to sort through.
408 */
409
410 omap_init_mbox();
411 omap_init_rtc();
412 omap_init_spi100k();
413 omap_init_sti();
414 omap_init_uwire();
415 omap1_init_rng();
416
417 return 0;
418}
419arch_initcall(omap1_init_devices);
420
421#if IS_ENABLED(CONFIG_OMAP_WATCHDOG)
422
423static struct resource wdt_resources[] = {
424 {
425 .start = 0xfffeb000,
426 .end = 0xfffeb07F,
427 .flags = IORESOURCE_MEM,
428 },
429};
430
431static struct platform_device omap_wdt_device = {
432 .name = "omap_wdt",
433 .id = -1,
434 .num_resources = ARRAY_SIZE(wdt_resources),
435 .resource = wdt_resources,
436};
437
438static int __init omap_init_wdt(void)
439{
440 struct omap_wd_timer_platform_data pdata;
441 int ret;
442
443 if (!cpu_is_omap16xx())
444 return -ENODEV;
445
446 pdata.read_reset_sources = omap1_get_reset_sources;
447
448 ret = platform_device_register(&omap_wdt_device);
449 if (!ret) {
450 ret = platform_device_add_data(&omap_wdt_device, &pdata,
451 sizeof(pdata));
452 if (ret)
453 platform_device_del(&omap_wdt_device);
454 }
455
456 return ret;
457}
458subsys_initcall(omap_init_wdt);
459#endif