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1/*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * EXYNOS - CPU PMU(Power Management Unit) support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/io.h>
13#include <linux/kernel.h>
14#include <linux/bug.h>
15
16#include <plat/cpu.h>
17
18#include "common.h"
19#include "regs-pmu.h"
20
21static const struct exynos_pmu_conf *exynos_pmu_config;
22
23static const struct exynos_pmu_conf exynos4210_pmu_config[] = {
24 /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
25 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
26 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
27 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
28 { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
29 { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
30 { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
31 { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
32 { S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } },
33 { S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } },
34 { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
35 { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
36 { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
37 { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
38 { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
39 { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
40 { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
41 { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
42 { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
43 { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
44 { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
45 { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
46 { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
47 { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
48 { S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
49 { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
50 { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
51 { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
52 { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
53 { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
54 { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
55 { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
56 { S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
57 { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
58 { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
59 { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
60 { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
61 { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
62 { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
63 { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
64 { S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
65 { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
66 { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
67 { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
68 { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
69 { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
70 { S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
71 { S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
72 { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
73 { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
74 { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
75 { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
76 { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
77 { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
78 { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
79 { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
80 { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
81 { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
82 { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
83 { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
84 { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
85 { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
86 { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
87 { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
88 { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
89 { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
90 { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
91 { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
92 { S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } },
93 { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
94 { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
95 { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
96 { PMU_TABLE_END,},
97};
98
99static const struct exynos_pmu_conf exynos4x12_pmu_config[] = {
100 { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
101 { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
102 { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
103 { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
104 { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
105 { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
106 { S5P_ISP_ARM_LOWPWR, { 0x1, 0x0, 0x0 } },
107 { S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR, { 0x0, 0x0, 0x0 } },
108 { S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR, { 0x0, 0x0, 0x0 } },
109 { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
110 { S5P_L2_0_LOWPWR, { 0x0, 0x0, 0x3 } },
111 /* XXX_OPTION register should be set other field */
112 { S5P_ARM_L2_0_OPTION, { 0x10, 0x10, 0x0 } },
113 { S5P_L2_1_LOWPWR, { 0x0, 0x0, 0x3 } },
114 { S5P_ARM_L2_1_OPTION, { 0x10, 0x10, 0x0 } },
115 { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
116 { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
117 { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
118 { S5P_DRAM_FREQ_DOWN_LOWPWR, { 0x1, 0x1, 0x1 } },
119 { S5P_DDRPHY_DLLOFF_LOWPWR, { 0x1, 0x1, 0x1 } },
120 { S5P_LPDDR_PHY_DLL_LOCK_LOWPWR, { 0x1, 0x1, 0x1 } },
121 { S5P_CMU_ACLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
122 { S5P_CMU_SCLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
123 { S5P_CMU_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
124 { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
125 { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
126 { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
127 { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
128 { S5P_MPLLUSER_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
129 { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
130 { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
131 { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
132 { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
133 { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
134 { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
135 { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
136 { S5P_CMU_CLKSTOP_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
137 { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x0, 0x0 } },
138 { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
139 { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
140 { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
141 { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
142 { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
143 { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
144 { S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
145 { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
146 { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
147 { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
148 { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
149 { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
150 { S5P_TOP_BUS_COREBLK_LOWPWR, { 0x3, 0x0, 0x0 } },
151 { S5P_TOP_RETENTION_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
152 { S5P_TOP_PWR_COREBLK_LOWPWR, { 0x3, 0x0, 0x3 } },
153 { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
154 { S5P_OSCCLK_GATE_LOWPWR, { 0x1, 0x0, 0x1 } },
155 { S5P_LOGIC_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
156 { S5P_OSCCLK_GATE_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
157 { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
158 { S5P_ONENAND_MEM_OPTION, { 0x10, 0x10, 0x0 } },
159 { S5P_HSI_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
160 { S5P_HSI_MEM_OPTION, { 0x10, 0x10, 0x0 } },
161 { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
162 { S5P_G2D_ACP_MEM_OPTION, { 0x10, 0x10, 0x0 } },
163 { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
164 { S5P_USBOTG_MEM_OPTION, { 0x10, 0x10, 0x0 } },
165 { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
166 { S5P_HSMMC_MEM_OPTION, { 0x10, 0x10, 0x0 } },
167 { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
168 { S5P_CSSYS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
169 { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
170 { S5P_SECSS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
171 { S5P_ROTATOR_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
172 { S5P_ROTATOR_MEM_OPTION, { 0x10, 0x10, 0x0 } },
173 { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
174 { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
175 { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
176 { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
177 { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
178 { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
179 { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
180 { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
181 { S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } },
182 { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
183 { S5P_PAD_ISOLATION_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
184 { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
185 { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
186 { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
187 { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
188 { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
189 { S5P_GPIO_MODE_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
190 { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
191 { S5P_TOP_ASB_RESET_LOWPWR, { 0x1, 0x1, 0x1 } },
192 { S5P_TOP_ASB_ISOLATION_LOWPWR, { 0x1, 0x0, 0x1 } },
193 { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
194 { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
195 { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
196 { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
197 { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
198 { S5P_ISP_LOWPWR, { 0x7, 0x0, 0x0 } },
199 { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
200 { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
201 { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
202 { S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
203 { S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
204 { PMU_TABLE_END,},
205};
206
207static const struct exynos_pmu_conf exynos4412_pmu_config[] = {
208 { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } },
209 { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } },
210 { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } },
211 { S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } },
212 { S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } },
213 { S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } },
214 { PMU_TABLE_END,},
215};
216
217static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
218 /* { .reg = address, .val = { AFTR, LPA, SLEEP } */
219 { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
220 { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
221 { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
222 { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
223 { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
224 { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
225 { EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
226 { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
227 { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
228 { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
229 { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
230 { EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
231 { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
232 { EXYNOS5_ARM_L2_OPTION, { 0x10, 0x10, 0x0 } },
233 { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
234 { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
235 { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
236 { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
237 { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
238 { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
239 { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
240 { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
241 { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
242 { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
243 { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
244 { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
245 { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
246 { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
247 { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
248 { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
249 { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
250 { EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
251 { EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
252 { EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
253 { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
254 { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
255 { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
256 { EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
257 { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
258 { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
259 { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
260 { EXYNOS5_USBOTG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
261 { EXYNOS5_G2D_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
262 { EXYNOS5_USBDRD_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
263 { EXYNOS5_SDMMC_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
264 { EXYNOS5_CSSYS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
265 { EXYNOS5_SECSS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
266 { EXYNOS5_ROTATOR_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
267 { EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
268 { EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
269 { EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
270 { EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
271 { EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
272 { EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
273 { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
274 { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
275 { EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
276 { EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
277 { EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
278 { EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
279 { EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
280 { EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
281 { EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
282 { EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
283 { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
284 { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
285 { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
286 { EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
287 { EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
288 { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
289 { EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
290 { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
291 { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
292 { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
293 { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
294 { EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
295 { EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
296 { EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
297 { EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
298 { EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
299 { EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} },
300 { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
301 { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
302 { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
303 { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
304 { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
305 { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
306 { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
307 { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
308 { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
309 { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
310 { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
311 { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
312 { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
313 { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
314 { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
315 { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
316 { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
317 { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
318 { PMU_TABLE_END,},
319};
320
321static void __iomem * const exynos5_list_both_cnt_feed[] = {
322 EXYNOS5_ARM_CORE0_OPTION,
323 EXYNOS5_ARM_CORE1_OPTION,
324 EXYNOS5_ARM_COMMON_OPTION,
325 EXYNOS5_GSCL_OPTION,
326 EXYNOS5_ISP_OPTION,
327 EXYNOS5_MFC_OPTION,
328 EXYNOS5_G3D_OPTION,
329 EXYNOS5_DISP1_OPTION,
330 EXYNOS5_MAU_OPTION,
331 EXYNOS5_TOP_PWR_OPTION,
332 EXYNOS5_TOP_PWR_SYSMEM_OPTION,
333};
334
335static void __iomem * const exynos5_list_diable_wfi_wfe[] = {
336 EXYNOS5_ARM_CORE1_OPTION,
337 EXYNOS5_FSYS_ARM_OPTION,
338 EXYNOS5_ISP_ARM_OPTION,
339};
340
341static void exynos5_init_pmu(void)
342{
343 unsigned int i;
344 unsigned int tmp;
345
346 /*
347 * Enable both SC_FEEDBACK and SC_COUNTER
348 */
349 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
350 tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
351 tmp |= (EXYNOS5_USE_SC_FEEDBACK |
352 EXYNOS5_USE_SC_COUNTER);
353 __raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
354 }
355
356 /*
357 * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
358 */
359 tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
360 tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
361 __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
362
363 /*
364 * Disable WFI/WFE on XXX_OPTION
365 */
366 for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
367 tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
368 tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
369 EXYNOS5_OPTION_USE_STANDBYWFI);
370 __raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
371 }
372}
373
374void exynos_sys_powerdown_conf(enum sys_powerdown mode)
375{
376 unsigned int i;
377
378 if (soc_is_exynos5250())
379 exynos5_init_pmu();
380
381 for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
382 __raw_writel(exynos_pmu_config[i].val[mode],
383 exynos_pmu_config[i].reg);
384
385 if (soc_is_exynos4412()) {
386 for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
387 __raw_writel(exynos4412_pmu_config[i].val[mode],
388 exynos4412_pmu_config[i].reg);
389 }
390}
391
392static int __init exynos_pmu_init(void)
393{
394 unsigned int value;
395
396 exynos_pmu_config = exynos4210_pmu_config;
397
398 if (soc_is_exynos4210()) {
399 exynos_pmu_config = exynos4210_pmu_config;
400 pr_info("EXYNOS4210 PMU Initialize\n");
401 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
402 exynos_pmu_config = exynos4x12_pmu_config;
403 pr_info("EXYNOS4x12 PMU Initialize\n");
404 } else if (soc_is_exynos5250()) {
405 /*
406 * When SYS_WDTRESET is set, watchdog timer reset request
407 * is ignored by power management unit.
408 */
409 value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
410 value &= ~EXYNOS5_SYS_WDTRESET;
411 __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
412
413 value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
414 value &= ~EXYNOS5_SYS_WDTRESET;
415 __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
416
417 exynos_pmu_config = exynos5250_pmu_config;
418 pr_info("EXYNOS5250 PMU Initialize\n");
419 } else {
420 pr_info("EXYNOS: PMU not supported\n");
421 }
422
423 return 0;
424}
425arch_initcall(exynos_pmu_init);