1/*
   2 * Aic94xx SAS/SATA driver hardware interface.
   3 *
   4 * Copyright (C) 2005 Adaptec, Inc.  All rights reserved.
   5 * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
   6 *
   7 * This file is licensed under GPLv2.
   8 *
   9 * This file is part of the aic94xx driver.
  10 *
  11 * The aic94xx driver is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; version 2 of the
  14 * License.
  15 *
  16 * The aic94xx driver is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19 * General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with the aic94xx driver; if not, write to the Free Software
  23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  24 *
  25 */
  26
  27#include <linux/pci.h>
  28#include <linux/slab.h>
  29#include <linux/delay.h>
  30#include <linux/module.h>
  31#include <linux/firmware.h>
  32
  33#include "aic94xx.h"
  34#include "aic94xx_reg.h"
  35#include "aic94xx_hwi.h"
  36#include "aic94xx_seq.h"
  37#include "aic94xx_dump.h"
  38
  39u32 MBAR0_SWB_SIZE;
  40
  41/* ---------- Initialization ---------- */
  42
  43static int asd_get_user_sas_addr(struct asd_ha_struct *asd_ha)
  44{
  45	/* adapter came with a sas address */
  46	if (asd_ha->hw_prof.sas_addr[0])
  47		return 0;
  48
  49	return sas_request_addr(asd_ha->sas_ha.core.shost,
  50				asd_ha->hw_prof.sas_addr);
  51}
  52
  53static void asd_propagate_sas_addr(struct asd_ha_struct *asd_ha)
  54{
  55	int i;
  56
  57	for (i = 0; i < ASD_MAX_PHYS; i++) {
  58		if (asd_ha->hw_prof.phy_desc[i].sas_addr[0] == 0)
  59			continue;
  60		/* Set a phy's address only if it has none.
  61		 */
  62		ASD_DPRINTK("setting phy%d addr to %llx\n", i,
  63			    SAS_ADDR(asd_ha->hw_prof.sas_addr));
  64		memcpy(asd_ha->hw_prof.phy_desc[i].sas_addr,
  65		       asd_ha->hw_prof.sas_addr, SAS_ADDR_SIZE);
  66	}
  67}
  68
  69/* ---------- PHY initialization ---------- */
  70
  71static void asd_init_phy_identify(struct asd_phy *phy)
  72{
  73	phy->identify_frame = phy->id_frm_tok->vaddr;
  74
  75	memset(phy->identify_frame, 0, sizeof(*phy->identify_frame));
  76
  77	phy->identify_frame->dev_type = SAS_END_DEVICE;
  78	if (phy->sas_phy.role & PHY_ROLE_INITIATOR)
  79		phy->identify_frame->initiator_bits = phy->sas_phy.iproto;
  80	if (phy->sas_phy.role & PHY_ROLE_TARGET)
  81		phy->identify_frame->target_bits = phy->sas_phy.tproto;
  82	memcpy(phy->identify_frame->sas_addr, phy->phy_desc->sas_addr,
  83	       SAS_ADDR_SIZE);
  84	phy->identify_frame->phy_id = phy->sas_phy.id;
  85}
  86
  87static int asd_init_phy(struct asd_phy *phy)
  88{
  89	struct asd_ha_struct *asd_ha = phy->sas_phy.ha->lldd_ha;
  90	struct asd_sas_phy *sas_phy = &phy->sas_phy;
  91
  92	sas_phy->enabled = 1;
  93	sas_phy->class = SAS;
  94	sas_phy->iproto = SAS_PROTOCOL_ALL;
  95	sas_phy->tproto = 0;
  96	sas_phy->type = PHY_TYPE_PHYSICAL;
  97	sas_phy->role = PHY_ROLE_INITIATOR;
  98	sas_phy->oob_mode = OOB_NOT_CONNECTED;
  99	sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 100
 101	phy->id_frm_tok = asd_alloc_coherent(asd_ha,
 102					     sizeof(*phy->identify_frame),
 103					     GFP_KERNEL);
 104	if (!phy->id_frm_tok) {
 105		asd_printk("no mem for IDENTIFY for phy%d\n", sas_phy->id);
 106		return -ENOMEM;
 107	} else
 108		asd_init_phy_identify(phy);
 109
 110	memset(phy->frame_rcvd, 0, sizeof(phy->frame_rcvd));
 111
 112	return 0;
 113}
 114
 115static void asd_init_ports(struct asd_ha_struct *asd_ha)
 116{
 117	int i;
 118
 119	spin_lock_init(&asd_ha->asd_ports_lock);
 120	for (i = 0; i < ASD_MAX_PHYS; i++) {
 121		struct asd_port *asd_port = &asd_ha->asd_ports[i];
 122
 123		memset(asd_port->sas_addr, 0, SAS_ADDR_SIZE);
 124		memset(asd_port->attached_sas_addr, 0, SAS_ADDR_SIZE);
 125		asd_port->phy_mask = 0;
 126		asd_port->num_phys = 0;
 127	}
 128}
 129
 130static int asd_init_phys(struct asd_ha_struct *asd_ha)
 131{
 132	u8 i;
 133	u8 phy_mask = asd_ha->hw_prof.enabled_phys;
 134
 135	for (i = 0; i < ASD_MAX_PHYS; i++) {
 136		struct asd_phy *phy = &asd_ha->phys[i];
 137
 138		phy->phy_desc = &asd_ha->hw_prof.phy_desc[i];
 139		phy->asd_port = NULL;
 140
 141		phy->sas_phy.enabled = 0;
 142		phy->sas_phy.id = i;
 143		phy->sas_phy.sas_addr = &phy->phy_desc->sas_addr[0];
 144		phy->sas_phy.frame_rcvd = &phy->frame_rcvd[0];
 145		phy->sas_phy.ha = &asd_ha->sas_ha;
 146		phy->sas_phy.lldd_phy = phy;
 147	}
 148
 149	/* Now enable and initialize only the enabled phys. */
 150	for_each_phy(phy_mask, phy_mask, i) {
 151		int err = asd_init_phy(&asd_ha->phys[i]);
 152		if (err)
 153			return err;
 154	}
 155
 156	return 0;
 157}
 158
 159/* ---------- Sliding windows ---------- */
 160
 161static int asd_init_sw(struct asd_ha_struct *asd_ha)
 162{
 163	struct pci_dev *pcidev = asd_ha->pcidev;
 164	int err;
 165	u32 v;
 166
 167	/* Unlock MBARs */
 168	err = pci_read_config_dword(pcidev, PCI_CONF_MBAR_KEY, &v);
 169	if (err) {
 170		asd_printk("couldn't access conf. space of %s\n",
 171			   pci_name(pcidev));
 172		goto Err;
 173	}
 174	if (v)
 175		err = pci_write_config_dword(pcidev, PCI_CONF_MBAR_KEY, v);
 176	if (err) {
 177		asd_printk("couldn't write to MBAR_KEY of %s\n",
 178			   pci_name(pcidev));
 179		goto Err;
 180	}
 181
 182	/* Set sliding windows A, B and C to point to proper internal
 183	 * memory regions.
 184	 */
 185	pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWA, REG_BASE_ADDR);
 186	pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWB,
 187			       REG_BASE_ADDR_CSEQCIO);
 188	pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWC, REG_BASE_ADDR_EXSI);
 189	asd_ha->io_handle[0].swa_base = REG_BASE_ADDR;
 190	asd_ha->io_handle[0].swb_base = REG_BASE_ADDR_CSEQCIO;
 191	asd_ha->io_handle[0].swc_base = REG_BASE_ADDR_EXSI;
 192	MBAR0_SWB_SIZE = asd_ha->io_handle[0].len - 0x80;
 193	if (!asd_ha->iospace) {
 194		/* MBAR1 will point to OCM (On Chip Memory) */
 195		pci_write_config_dword(pcidev, PCI_CONF_MBAR1, OCM_BASE_ADDR);
 196		asd_ha->io_handle[1].swa_base = OCM_BASE_ADDR;
 197	}
 198	spin_lock_init(&asd_ha->iolock);
 199Err:
 200	return err;
 201}
 202
 203/* ---------- SCB initialization ---------- */
 204
 205/**
 206 * asd_init_scbs - manually allocate the first SCB.
 207 * @asd_ha: pointer to host adapter structure
 208 *
 209 * This allocates the very first SCB which would be sent to the
 210 * sequencer for execution.  Its bus address is written to
 211 * CSEQ_Q_NEW_POINTER, mode page 2, mode 8.  Since the bus address of
 212 * the _next_ scb to be DMA-ed to the host adapter is read from the last
 213 * SCB DMA-ed to the host adapter, we have to always stay one step
 214 * ahead of the sequencer and keep one SCB already allocated.
 215 */
 216static int asd_init_scbs(struct asd_ha_struct *asd_ha)
 217{
 218	struct asd_seq_data *seq = &asd_ha->seq;
 219	int bitmap_bytes;
 220
 221	/* allocate the index array and bitmap */
 222	asd_ha->seq.tc_index_bitmap_bits = asd_ha->hw_prof.max_scbs;
 223	asd_ha->seq.tc_index_array = kzalloc(asd_ha->seq.tc_index_bitmap_bits*
 224					     sizeof(void *), GFP_KERNEL);
 225	if (!asd_ha->seq.tc_index_array)
 226		return -ENOMEM;
 227
 228	bitmap_bytes = (asd_ha->seq.tc_index_bitmap_bits+7)/8;
 229	bitmap_bytes = BITS_TO_LONGS(bitmap_bytes*8)*sizeof(unsigned long);
 230	asd_ha->seq.tc_index_bitmap = kzalloc(bitmap_bytes, GFP_KERNEL);
 231	if (!asd_ha->seq.tc_index_bitmap)
 
 
 232		return -ENOMEM;
 
 233
 234	spin_lock_init(&seq->tc_index_lock);
 235
 236	seq->next_scb.size = sizeof(struct scb);
 237	seq->next_scb.vaddr = dma_pool_alloc(asd_ha->scb_pool, GFP_KERNEL,
 238					     &seq->next_scb.dma_handle);
 239	if (!seq->next_scb.vaddr) {
 240		kfree(asd_ha->seq.tc_index_bitmap);
 241		kfree(asd_ha->seq.tc_index_array);
 242		asd_ha->seq.tc_index_bitmap = NULL;
 243		asd_ha->seq.tc_index_array = NULL;
 244		return -ENOMEM;
 245	}
 246
 247	seq->pending = 0;
 248	spin_lock_init(&seq->pend_q_lock);
 249	INIT_LIST_HEAD(&seq->pend_q);
 250
 251	return 0;
 252}
 253
 254static void asd_get_max_scb_ddb(struct asd_ha_struct *asd_ha)
 255{
 256	asd_ha->hw_prof.max_scbs = asd_get_cmdctx_size(asd_ha)/ASD_SCB_SIZE;
 257	asd_ha->hw_prof.max_ddbs = asd_get_devctx_size(asd_ha)/ASD_DDB_SIZE;
 258	ASD_DPRINTK("max_scbs:%d, max_ddbs:%d\n",
 259		    asd_ha->hw_prof.max_scbs,
 260		    asd_ha->hw_prof.max_ddbs);
 261}
 262
 263/* ---------- Done List initialization ---------- */
 264
 265static void asd_dl_tasklet_handler(unsigned long);
 266
 267static int asd_init_dl(struct asd_ha_struct *asd_ha)
 268{
 269	asd_ha->seq.actual_dl
 270		= asd_alloc_coherent(asd_ha,
 271			     ASD_DL_SIZE * sizeof(struct done_list_struct),
 272				     GFP_KERNEL);
 273	if (!asd_ha->seq.actual_dl)
 274		return -ENOMEM;
 275	asd_ha->seq.dl = asd_ha->seq.actual_dl->vaddr;
 276	asd_ha->seq.dl_toggle = ASD_DEF_DL_TOGGLE;
 277	asd_ha->seq.dl_next = 0;
 278	tasklet_init(&asd_ha->seq.dl_tasklet, asd_dl_tasklet_handler,
 279		     (unsigned long) asd_ha);
 280
 281	return 0;
 282}
 283
 284/* ---------- EDB and ESCB init ---------- */
 285
 286static int asd_alloc_edbs(struct asd_ha_struct *asd_ha, gfp_t gfp_flags)
 287{
 288	struct asd_seq_data *seq = &asd_ha->seq;
 289	int i;
 290
 291	seq->edb_arr = kmalloc(seq->num_edbs*sizeof(*seq->edb_arr), gfp_flags);
 292	if (!seq->edb_arr)
 293		return -ENOMEM;
 294
 295	for (i = 0; i < seq->num_edbs; i++) {
 296		seq->edb_arr[i] = asd_alloc_coherent(asd_ha, ASD_EDB_SIZE,
 297						     gfp_flags);
 298		if (!seq->edb_arr[i])
 299			goto Err_unroll;
 300		memset(seq->edb_arr[i]->vaddr, 0, ASD_EDB_SIZE);
 301	}
 302
 303	ASD_DPRINTK("num_edbs:%d\n", seq->num_edbs);
 304
 305	return 0;
 306
 307Err_unroll:
 308	for (i-- ; i >= 0; i--)
 309		asd_free_coherent(asd_ha, seq->edb_arr[i]);
 310	kfree(seq->edb_arr);
 311	seq->edb_arr = NULL;
 312
 313	return -ENOMEM;
 314}
 315
 316static int asd_alloc_escbs(struct asd_ha_struct *asd_ha,
 317			   gfp_t gfp_flags)
 318{
 319	struct asd_seq_data *seq = &asd_ha->seq;
 320	struct asd_ascb *escb;
 321	int i, escbs;
 322
 323	seq->escb_arr = kmalloc(seq->num_escbs*sizeof(*seq->escb_arr),
 324				gfp_flags);
 325	if (!seq->escb_arr)
 326		return -ENOMEM;
 327
 328	escbs = seq->num_escbs;
 329	escb = asd_ascb_alloc_list(asd_ha, &escbs, gfp_flags);
 330	if (!escb) {
 331		asd_printk("couldn't allocate list of escbs\n");
 332		goto Err;
 333	}
 334	seq->num_escbs -= escbs;  /* subtract what was not allocated */
 335	ASD_DPRINTK("num_escbs:%d\n", seq->num_escbs);
 336
 337	for (i = 0; i < seq->num_escbs; i++, escb = list_entry(escb->list.next,
 338							       struct asd_ascb,
 339							       list)) {
 340		seq->escb_arr[i] = escb;
 341		escb->scb->header.opcode = EMPTY_SCB;
 342	}
 343
 344	return 0;
 345Err:
 346	kfree(seq->escb_arr);
 347	seq->escb_arr = NULL;
 348	return -ENOMEM;
 349
 350}
 351
 352static void asd_assign_edbs2escbs(struct asd_ha_struct *asd_ha)
 353{
 354	struct asd_seq_data *seq = &asd_ha->seq;
 355	int i, k, z = 0;
 356
 357	for (i = 0; i < seq->num_escbs; i++) {
 358		struct asd_ascb *ascb = seq->escb_arr[i];
 359		struct empty_scb *escb = &ascb->scb->escb;
 360
 361		ascb->edb_index = z;
 362
 363		escb->num_valid = ASD_EDBS_PER_SCB;
 364
 365		for (k = 0; k < ASD_EDBS_PER_SCB; k++) {
 366			struct sg_el *eb = &escb->eb[k];
 367			struct asd_dma_tok *edb = seq->edb_arr[z++];
 368
 369			memset(eb, 0, sizeof(*eb));
 370			eb->bus_addr = cpu_to_le64(((u64) edb->dma_handle));
 371			eb->size = cpu_to_le32(((u32) edb->size));
 372		}
 373	}
 374}
 375
 376/**
 377 * asd_init_escbs -- allocate and initialize empty scbs
 378 * @asd_ha: pointer to host adapter structure
 379 *
 380 * An empty SCB has sg_elements of ASD_EDBS_PER_SCB (7) buffers.
 381 * They transport sense data, etc.
 382 */
 383static int asd_init_escbs(struct asd_ha_struct *asd_ha)
 384{
 385	struct asd_seq_data *seq = &asd_ha->seq;
 386	int err = 0;
 387
 388	/* Allocate two empty data buffers (edb) per sequencer. */
 389	int edbs = 2*(1+asd_ha->hw_prof.num_phys);
 390
 391	seq->num_escbs = (edbs+ASD_EDBS_PER_SCB-1)/ASD_EDBS_PER_SCB;
 392	seq->num_edbs = seq->num_escbs * ASD_EDBS_PER_SCB;
 393
 394	err = asd_alloc_edbs(asd_ha, GFP_KERNEL);
 395	if (err) {
 396		asd_printk("couldn't allocate edbs\n");
 397		return err;
 398	}
 399
 400	err = asd_alloc_escbs(asd_ha, GFP_KERNEL);
 401	if (err) {
 402		asd_printk("couldn't allocate escbs\n");
 403		return err;
 404	}
 405
 406	asd_assign_edbs2escbs(asd_ha);
 407	/* In order to insure that normal SCBs do not overfill sequencer
 408	 * memory and leave no space for escbs (halting condition),
 409	 * we increment pending here by the number of escbs.  However,
 410	 * escbs are never pending.
 411	 */
 412	seq->pending   = seq->num_escbs;
 413	seq->can_queue = 1 + (asd_ha->hw_prof.max_scbs - seq->pending)/2;
 414
 415	return 0;
 416}
 417
 418/* ---------- HW initialization ---------- */
 419
 420/**
 421 * asd_chip_hardrst -- hard reset the chip
 422 * @asd_ha: pointer to host adapter structure
 423 *
 424 * This takes 16 cycles and is synchronous to CFCLK, which runs
 425 * at 200 MHz, so this should take at most 80 nanoseconds.
 426 */
 427int asd_chip_hardrst(struct asd_ha_struct *asd_ha)
 428{
 429	int i;
 430	int count = 100;
 431	u32 reg;
 432
 433	for (i = 0 ; i < 4 ; i++) {
 434		asd_write_reg_dword(asd_ha, COMBIST, HARDRST);
 435	}
 436
 437	do {
 438		udelay(1);
 439		reg = asd_read_reg_dword(asd_ha, CHIMINT);
 440		if (reg & HARDRSTDET) {
 441			asd_write_reg_dword(asd_ha, CHIMINT,
 442					    HARDRSTDET|PORRSTDET);
 443			return 0;
 444		}
 445	} while (--count > 0);
 446
 447	return -ENODEV;
 448}
 449
 450/**
 451 * asd_init_chip -- initialize the chip
 452 * @asd_ha: pointer to host adapter structure
 453 *
 454 * Hard resets the chip, disables HA interrupts, downloads the sequnecer
 455 * microcode and starts the sequencers.  The caller has to explicitly
 456 * enable HA interrupts with asd_enable_ints(asd_ha).
 457 */
 458static int asd_init_chip(struct asd_ha_struct *asd_ha)
 459{
 460	int err;
 461
 462	err = asd_chip_hardrst(asd_ha);
 463	if (err) {
 464		asd_printk("couldn't hard reset %s\n",
 465			    pci_name(asd_ha->pcidev));
 466		goto out;
 467	}
 468
 469	asd_disable_ints(asd_ha);
 470
 471	err = asd_init_seqs(asd_ha);
 472	if (err) {
 473		asd_printk("couldn't init seqs for %s\n",
 474			   pci_name(asd_ha->pcidev));
 475		goto out;
 476	}
 477
 478	err = asd_start_seqs(asd_ha);
 479	if (err) {
 480		asd_printk("coudln't start seqs for %s\n",
 481			   pci_name(asd_ha->pcidev));
 482		goto out;
 483	}
 484out:
 485	return err;
 486}
 487
 488#define MAX_DEVS ((OCM_MAX_SIZE) / (ASD_DDB_SIZE))
 489
 490static int max_devs = 0;
 491module_param_named(max_devs, max_devs, int, S_IRUGO);
 492MODULE_PARM_DESC(max_devs, "\n"
 493	"\tMaximum number of SAS devices to support (not LUs).\n"
 494	"\tDefault: 2176, Maximum: 65663.\n");
 495
 496static int max_cmnds = 0;
 497module_param_named(max_cmnds, max_cmnds, int, S_IRUGO);
 498MODULE_PARM_DESC(max_cmnds, "\n"
 499	"\tMaximum number of commands queuable.\n"
 500	"\tDefault: 512, Maximum: 66047.\n");
 501
 502static void asd_extend_devctx_ocm(struct asd_ha_struct *asd_ha)
 503{
 504	unsigned long dma_addr = OCM_BASE_ADDR;
 505	u32 d;
 506
 507	dma_addr -= asd_ha->hw_prof.max_ddbs * ASD_DDB_SIZE;
 508	asd_write_reg_addr(asd_ha, DEVCTXBASE, (dma_addr_t) dma_addr);
 509	d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
 510	d |= 4;
 511	asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
 512	asd_ha->hw_prof.max_ddbs += MAX_DEVS;
 513}
 514
 515static int asd_extend_devctx(struct asd_ha_struct *asd_ha)
 516{
 517	dma_addr_t dma_handle;
 518	unsigned long dma_addr;
 519	u32 d;
 520	int size;
 521
 522	asd_extend_devctx_ocm(asd_ha);
 523
 524	asd_ha->hw_prof.ddb_ext = NULL;
 525	if (max_devs <= asd_ha->hw_prof.max_ddbs || max_devs > 0xFFFF) {
 526		max_devs = asd_ha->hw_prof.max_ddbs;
 527		return 0;
 528	}
 529
 530	size = (max_devs - asd_ha->hw_prof.max_ddbs + 1) * ASD_DDB_SIZE;
 531
 532	asd_ha->hw_prof.ddb_ext = asd_alloc_coherent(asd_ha, size, GFP_KERNEL);
 533	if (!asd_ha->hw_prof.ddb_ext) {
 534		asd_printk("couldn't allocate memory for %d devices\n",
 535			   max_devs);
 536		max_devs = asd_ha->hw_prof.max_ddbs;
 537		return -ENOMEM;
 538	}
 539	dma_handle = asd_ha->hw_prof.ddb_ext->dma_handle;
 540	dma_addr = ALIGN((unsigned long) dma_handle, ASD_DDB_SIZE);
 541	dma_addr -= asd_ha->hw_prof.max_ddbs * ASD_DDB_SIZE;
 542	dma_handle = (dma_addr_t) dma_addr;
 543	asd_write_reg_addr(asd_ha, DEVCTXBASE, dma_handle);
 544	d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
 545	d &= ~4;
 546	asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
 547
 548	asd_ha->hw_prof.max_ddbs = max_devs;
 549
 550	return 0;
 551}
 552
 553static int asd_extend_cmdctx(struct asd_ha_struct *asd_ha)
 554{
 555	dma_addr_t dma_handle;
 556	unsigned long dma_addr;
 557	u32 d;
 558	int size;
 559
 560	asd_ha->hw_prof.scb_ext = NULL;
 561	if (max_cmnds <= asd_ha->hw_prof.max_scbs || max_cmnds > 0xFFFF) {
 562		max_cmnds = asd_ha->hw_prof.max_scbs;
 563		return 0;
 564	}
 565
 566	size = (max_cmnds - asd_ha->hw_prof.max_scbs + 1) * ASD_SCB_SIZE;
 567
 568	asd_ha->hw_prof.scb_ext = asd_alloc_coherent(asd_ha, size, GFP_KERNEL);
 569	if (!asd_ha->hw_prof.scb_ext) {
 570		asd_printk("couldn't allocate memory for %d commands\n",
 571			   max_cmnds);
 572		max_cmnds = asd_ha->hw_prof.max_scbs;
 573		return -ENOMEM;
 574	}
 575	dma_handle = asd_ha->hw_prof.scb_ext->dma_handle;
 576	dma_addr = ALIGN((unsigned long) dma_handle, ASD_SCB_SIZE);
 577	dma_addr -= asd_ha->hw_prof.max_scbs * ASD_SCB_SIZE;
 578	dma_handle = (dma_addr_t) dma_addr;
 579	asd_write_reg_addr(asd_ha, CMDCTXBASE, dma_handle);
 580	d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
 581	d &= ~1;
 582	asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
 583
 584	asd_ha->hw_prof.max_scbs = max_cmnds;
 585
 586	return 0;
 587}
 588
 589/**
 590 * asd_init_ctxmem -- initialize context memory
 591 * asd_ha: pointer to host adapter structure
 592 *
 593 * This function sets the maximum number of SCBs and
 594 * DDBs which can be used by the sequencer.  This is normally
 595 * 512 and 128 respectively.  If support for more SCBs or more DDBs
 596 * is required then CMDCTXBASE, DEVCTXBASE and CTXDOMAIN are
 597 * initialized here to extend context memory to point to host memory,
 598 * thus allowing unlimited support for SCBs and DDBs -- only limited
 599 * by host memory.
 600 */
 601static int asd_init_ctxmem(struct asd_ha_struct *asd_ha)
 602{
 603	int bitmap_bytes;
 604
 605	asd_get_max_scb_ddb(asd_ha);
 606	asd_extend_devctx(asd_ha);
 607	asd_extend_cmdctx(asd_ha);
 608
 609	/* The kernel wants bitmaps to be unsigned long sized. */
 610	bitmap_bytes = (asd_ha->hw_prof.max_ddbs+7)/8;
 611	bitmap_bytes = BITS_TO_LONGS(bitmap_bytes*8)*sizeof(unsigned long);
 612	asd_ha->hw_prof.ddb_bitmap = kzalloc(bitmap_bytes, GFP_KERNEL);
 613	if (!asd_ha->hw_prof.ddb_bitmap)
 614		return -ENOMEM;
 615	spin_lock_init(&asd_ha->hw_prof.ddb_lock);
 616
 617	return 0;
 618}
 619
 620int asd_init_hw(struct asd_ha_struct *asd_ha)
 621{
 622	int err;
 623	u32 v;
 624
 625	err = asd_init_sw(asd_ha);
 626	if (err)
 627		return err;
 628
 629	err = pci_read_config_dword(asd_ha->pcidev, PCIC_HSTPCIX_CNTRL, &v);
 630	if (err) {
 631		asd_printk("couldn't read PCIC_HSTPCIX_CNTRL of %s\n",
 632			   pci_name(asd_ha->pcidev));
 633		return err;
 634	}
 635	pci_write_config_dword(asd_ha->pcidev, PCIC_HSTPCIX_CNTRL,
 636					v | SC_TMR_DIS);
 637	if (err) {
 638		asd_printk("couldn't disable split completion timer of %s\n",
 639			   pci_name(asd_ha->pcidev));
 640		return err;
 641	}
 642
 643	err = asd_read_ocm(asd_ha);
 644	if (err) {
 645		asd_printk("couldn't read ocm(%d)\n", err);
 646		/* While suspicios, it is not an error that we
 647		 * couldn't read the OCM. */
 648	}
 649
 650	err = asd_read_flash(asd_ha);
 651	if (err) {
 652		asd_printk("couldn't read flash(%d)\n", err);
 653		/* While suspicios, it is not an error that we
 654		 * couldn't read FLASH memory.
 655		 */
 656	}
 657
 658	asd_init_ctxmem(asd_ha);
 659
 660	if (asd_get_user_sas_addr(asd_ha)) {
 661		asd_printk("No SAS Address provided for %s\n",
 662			   pci_name(asd_ha->pcidev));
 663		err = -ENODEV;
 664		goto Out;
 665	}
 666
 667	asd_propagate_sas_addr(asd_ha);
 668
 669	err = asd_init_phys(asd_ha);
 670	if (err) {
 671		asd_printk("couldn't initialize phys for %s\n",
 672			    pci_name(asd_ha->pcidev));
 673		goto Out;
 674	}
 675
 676	asd_init_ports(asd_ha);
 677
 678	err = asd_init_scbs(asd_ha);
 679	if (err) {
 680		asd_printk("couldn't initialize scbs for %s\n",
 681			    pci_name(asd_ha->pcidev));
 682		goto Out;
 683	}
 684
 685	err = asd_init_dl(asd_ha);
 686	if (err) {
 687		asd_printk("couldn't initialize the done list:%d\n",
 688			    err);
 689		goto Out;
 690	}
 691
 692	err = asd_init_escbs(asd_ha);
 693	if (err) {
 694		asd_printk("couldn't initialize escbs\n");
 695		goto Out;
 696	}
 697
 698	err = asd_init_chip(asd_ha);
 699	if (err) {
 700		asd_printk("couldn't init the chip\n");
 701		goto Out;
 702	}
 703Out:
 704	return err;
 705}
 706
 707/* ---------- Chip reset ---------- */
 708
 709/**
 710 * asd_chip_reset -- reset the host adapter, etc
 711 * @asd_ha: pointer to host adapter structure of interest
 712 *
 713 * Called from the ISR.  Hard reset the chip.  Let everything
 714 * timeout.  This should be no different than hot-unplugging the
 715 * host adapter.  Once everything times out we'll init the chip with
 716 * a call to asd_init_chip() and enable interrupts with asd_enable_ints().
 717 * XXX finish.
 718 */
 719static void asd_chip_reset(struct asd_ha_struct *asd_ha)
 720{
 721	struct sas_ha_struct *sas_ha = &asd_ha->sas_ha;
 722
 723	ASD_DPRINTK("chip reset for %s\n", pci_name(asd_ha->pcidev));
 724	asd_chip_hardrst(asd_ha);
 725	sas_ha->notify_ha_event(sas_ha, HAE_RESET);
 726}
 727
 728/* ---------- Done List Routines ---------- */
 729
 730static void asd_dl_tasklet_handler(unsigned long data)
 731{
 732	struct asd_ha_struct *asd_ha = (struct asd_ha_struct *) data;
 733	struct asd_seq_data *seq = &asd_ha->seq;
 734	unsigned long flags;
 735
 736	while (1) {
 737		struct done_list_struct *dl = &seq->dl[seq->dl_next];
 738		struct asd_ascb *ascb;
 739
 740		if ((dl->toggle & DL_TOGGLE_MASK) != seq->dl_toggle)
 741			break;
 742
 743		/* find the aSCB */
 744		spin_lock_irqsave(&seq->tc_index_lock, flags);
 745		ascb = asd_tc_index_find(seq, (int)le16_to_cpu(dl->index));
 746		spin_unlock_irqrestore(&seq->tc_index_lock, flags);
 747		if (unlikely(!ascb)) {
 748			ASD_DPRINTK("BUG:sequencer:dl:no ascb?!\n");
 749			goto next_1;
 750		} else if (ascb->scb->header.opcode == EMPTY_SCB) {
 751			goto out;
 752		} else if (!ascb->uldd_timer && !del_timer(&ascb->timer)) {
 753			goto next_1;
 754		}
 755		spin_lock_irqsave(&seq->pend_q_lock, flags);
 756		list_del_init(&ascb->list);
 757		seq->pending--;
 758		spin_unlock_irqrestore(&seq->pend_q_lock, flags);
 759	out:
 760		ascb->tasklet_complete(ascb, dl);
 761
 762	next_1:
 763		seq->dl_next = (seq->dl_next + 1) & (ASD_DL_SIZE-1);
 764		if (!seq->dl_next)
 765			seq->dl_toggle ^= DL_TOGGLE_MASK;
 766	}
 767}
 768
 769/* ---------- Interrupt Service Routines ---------- */
 770
 771/**
 772 * asd_process_donelist_isr -- schedule processing of done list entries
 773 * @asd_ha: pointer to host adapter structure
 774 */
 775static void asd_process_donelist_isr(struct asd_ha_struct *asd_ha)
 776{
 777	tasklet_schedule(&asd_ha->seq.dl_tasklet);
 778}
 779
 780/**
 781 * asd_com_sas_isr -- process device communication interrupt (COMINT)
 782 * @asd_ha: pointer to host adapter structure
 783 */
 784static void asd_com_sas_isr(struct asd_ha_struct *asd_ha)
 785{
 786	u32 comstat = asd_read_reg_dword(asd_ha, COMSTAT);
 787
 788	/* clear COMSTAT int */
 789	asd_write_reg_dword(asd_ha, COMSTAT, 0xFFFFFFFF);
 790
 791	if (comstat & CSBUFPERR) {
 792		asd_printk("%s: command/status buffer dma parity error\n",
 793			   pci_name(asd_ha->pcidev));
 794	} else if (comstat & CSERR) {
 795		int i;
 796		u32 dmaerr = asd_read_reg_dword(asd_ha, DMAERR);
 797		dmaerr &= 0xFF;
 798		asd_printk("%s: command/status dma error, DMAERR: 0x%02x, "
 799			   "CSDMAADR: 0x%04x, CSDMAADR+4: 0x%04x\n",
 800			   pci_name(asd_ha->pcidev),
 801			   dmaerr,
 802			   asd_read_reg_dword(asd_ha, CSDMAADR),
 803			   asd_read_reg_dword(asd_ha, CSDMAADR+4));
 804		asd_printk("CSBUFFER:\n");
 805		for (i = 0; i < 8; i++) {
 806			asd_printk("%08x %08x %08x %08x\n",
 807				   asd_read_reg_dword(asd_ha, CSBUFFER),
 808				   asd_read_reg_dword(asd_ha, CSBUFFER+4),
 809				   asd_read_reg_dword(asd_ha, CSBUFFER+8),
 810				   asd_read_reg_dword(asd_ha, CSBUFFER+12));
 811		}
 812		asd_dump_seq_state(asd_ha, 0);
 813	} else if (comstat & OVLYERR) {
 814		u32 dmaerr = asd_read_reg_dword(asd_ha, DMAERR);
 815		dmaerr = (dmaerr >> 8) & 0xFF;
 816		asd_printk("%s: overlay dma error:0x%x\n",
 817			   pci_name(asd_ha->pcidev),
 818			   dmaerr);
 819	}
 820	asd_chip_reset(asd_ha);
 821}
 822
 823static void asd_arp2_err(struct asd_ha_struct *asd_ha, u32 dchstatus)
 824{
 825	static const char *halt_code[256] = {
 826		"UNEXPECTED_INTERRUPT0",
 827		"UNEXPECTED_INTERRUPT1",
 828		"UNEXPECTED_INTERRUPT2",
 829		"UNEXPECTED_INTERRUPT3",
 830		"UNEXPECTED_INTERRUPT4",
 831		"UNEXPECTED_INTERRUPT5",
 832		"UNEXPECTED_INTERRUPT6",
 833		"UNEXPECTED_INTERRUPT7",
 834		"UNEXPECTED_INTERRUPT8",
 835		"UNEXPECTED_INTERRUPT9",
 836		"UNEXPECTED_INTERRUPT10",
 837		[11 ... 19] = "unknown[11,19]",
 838		"NO_FREE_SCB_AVAILABLE",
 839		"INVALID_SCB_OPCODE",
 840		"INVALID_MBX_OPCODE",
 841		"INVALID_ATA_STATE",
 842		"ATA_QUEUE_FULL",
 843		"ATA_TAG_TABLE_FAULT",
 844		"ATA_TAG_MASK_FAULT",
 845		"BAD_LINK_QUEUE_STATE",
 846		"DMA2CHIM_QUEUE_ERROR",
 847		"EMPTY_SCB_LIST_FULL",
 848		"unknown[30]",
 849		"IN_USE_SCB_ON_FREE_LIST",
 850		"BAD_OPEN_WAIT_STATE",
 851		"INVALID_STP_AFFILIATION",
 852		"unknown[34]",
 853		"EXEC_QUEUE_ERROR",
 854		"TOO_MANY_EMPTIES_NEEDED",
 855		"EMPTY_REQ_QUEUE_ERROR",
 856		"Q_MONIRTT_MGMT_ERROR",
 857		"TARGET_MODE_FLOW_ERROR",
 858		"DEVICE_QUEUE_NOT_FOUND",
 859		"START_IRTT_TIMER_ERROR",
 860		"ABORT_TASK_ILLEGAL_REQ",
 861		[43 ... 255] = "unknown[43,255]"
 862	};
 863
 864	if (dchstatus & CSEQINT) {
 865		u32 arp2int = asd_read_reg_dword(asd_ha, CARP2INT);
 866
 867		if (arp2int & (ARP2WAITTO|ARP2ILLOPC|ARP2PERR|ARP2CIOPERR)) {
 868			asd_printk("%s: CSEQ arp2int:0x%x\n",
 869				   pci_name(asd_ha->pcidev),
 870				   arp2int);
 871		} else if (arp2int & ARP2HALTC)
 872			asd_printk("%s: CSEQ halted: %s\n",
 873				   pci_name(asd_ha->pcidev),
 874				   halt_code[(arp2int>>16)&0xFF]);
 875		else
 876			asd_printk("%s: CARP2INT:0x%x\n",
 877				   pci_name(asd_ha->pcidev),
 878				   arp2int);
 879	}
 880	if (dchstatus & LSEQINT_MASK) {
 881		int lseq;
 882		u8  lseq_mask = dchstatus & LSEQINT_MASK;
 883
 884		for_each_sequencer(lseq_mask, lseq_mask, lseq) {
 885			u32 arp2int = asd_read_reg_dword(asd_ha,
 886							 LmARP2INT(lseq));
 887			if (arp2int & (ARP2WAITTO | ARP2ILLOPC | ARP2PERR
 888				       | ARP2CIOPERR)) {
 889				asd_printk("%s: LSEQ%d arp2int:0x%x\n",
 890					   pci_name(asd_ha->pcidev),
 891					   lseq, arp2int);
 892				/* XXX we should only do lseq reset */
 893			} else if (arp2int & ARP2HALTC)
 894				asd_printk("%s: LSEQ%d halted: %s\n",
 895					   pci_name(asd_ha->pcidev),
 896					   lseq,halt_code[(arp2int>>16)&0xFF]);
 897			else
 898				asd_printk("%s: LSEQ%d ARP2INT:0x%x\n",
 899					   pci_name(asd_ha->pcidev), lseq,
 900					   arp2int);
 901		}
 902	}
 903	asd_chip_reset(asd_ha);
 904}
 905
 906/**
 907 * asd_dch_sas_isr -- process device channel interrupt (DEVINT)
 908 * @asd_ha: pointer to host adapter structure
 909 */
 910static void asd_dch_sas_isr(struct asd_ha_struct *asd_ha)
 911{
 912	u32 dchstatus = asd_read_reg_dword(asd_ha, DCHSTATUS);
 913
 914	if (dchstatus & CFIFTOERR) {
 915		asd_printk("%s: CFIFTOERR\n", pci_name(asd_ha->pcidev));
 916		asd_chip_reset(asd_ha);
 917	} else
 918		asd_arp2_err(asd_ha, dchstatus);
 919}
 920
 921/**
 922 * ads_rbi_exsi_isr -- process external system interface interrupt (INITERR)
 923 * @asd_ha: pointer to host adapter structure
 924 */
 925static void asd_rbi_exsi_isr(struct asd_ha_struct *asd_ha)
 926{
 927	u32 stat0r = asd_read_reg_dword(asd_ha, ASISTAT0R);
 928
 929	if (!(stat0r & ASIERR)) {
 930		asd_printk("hmm, EXSI interrupted but no error?\n");
 931		return;
 932	}
 933
 934	if (stat0r & ASIFMTERR) {
 935		asd_printk("ASI SEEPROM format error for %s\n",
 936			   pci_name(asd_ha->pcidev));
 937	} else if (stat0r & ASISEECHKERR) {
 938		u32 stat1r = asd_read_reg_dword(asd_ha, ASISTAT1R);
 939		asd_printk("ASI SEEPROM checksum 0x%x error for %s\n",
 940			   stat1r & CHECKSUM_MASK,
 941			   pci_name(asd_ha->pcidev));
 942	} else {
 943		u32 statr = asd_read_reg_dword(asd_ha, ASIERRSTATR);
 944
 945		if (!(statr & CPI2ASIMSTERR_MASK)) {
 946			ASD_DPRINTK("hmm, ASIERR?\n");
 947			return;
 948		} else {
 949			u32 addr = asd_read_reg_dword(asd_ha, ASIERRADDR);
 950			u32 data = asd_read_reg_dword(asd_ha, ASIERRDATAR);
 951
 952			asd_printk("%s: CPI2 xfer err: addr: 0x%x, wdata: 0x%x, "
 953				   "count: 0x%x, byteen: 0x%x, targerr: 0x%x "
 954				   "master id: 0x%x, master err: 0x%x\n",
 955				   pci_name(asd_ha->pcidev),
 956				   addr, data,
 957				   (statr & CPI2ASIBYTECNT_MASK) >> 16,
 958				   (statr & CPI2ASIBYTEEN_MASK) >> 12,
 959				   (statr & CPI2ASITARGERR_MASK) >> 8,
 960				   (statr & CPI2ASITARGMID_MASK) >> 4,
 961				   (statr & CPI2ASIMSTERR_MASK));
 962		}
 963	}
 964	asd_chip_reset(asd_ha);
 965}
 966
 967/**
 968 * asd_hst_pcix_isr -- process host interface interrupts
 969 * @asd_ha: pointer to host adapter structure
 970 *
 971 * Asserted on PCIX errors: target abort, etc.
 972 */
 973static void asd_hst_pcix_isr(struct asd_ha_struct *asd_ha)
 974{
 975	u16 status;
 976	u32 pcix_status;
 977	u32 ecc_status;
 978
 979	pci_read_config_word(asd_ha->pcidev, PCI_STATUS, &status);
 980	pci_read_config_dword(asd_ha->pcidev, PCIX_STATUS, &pcix_status);
 981	pci_read_config_dword(asd_ha->pcidev, ECC_CTRL_STAT, &ecc_status);
 982
 983	if (status & PCI_STATUS_DETECTED_PARITY)
 984		asd_printk("parity error for %s\n", pci_name(asd_ha->pcidev));
 985	else if (status & PCI_STATUS_REC_MASTER_ABORT)
 986		asd_printk("master abort for %s\n", pci_name(asd_ha->pcidev));
 987	else if (status & PCI_STATUS_REC_TARGET_ABORT)
 988		asd_printk("target abort for %s\n", pci_name(asd_ha->pcidev));
 989	else if (status & PCI_STATUS_PARITY)
 990		asd_printk("data parity for %s\n", pci_name(asd_ha->pcidev));
 991	else if (pcix_status & RCV_SCE) {
 992		asd_printk("received split completion error for %s\n",
 993			   pci_name(asd_ha->pcidev));
 994		pci_write_config_dword(asd_ha->pcidev,PCIX_STATUS,pcix_status);
 995		/* XXX: Abort task? */
 996		return;
 997	} else if (pcix_status & UNEXP_SC) {
 998		asd_printk("unexpected split completion for %s\n",
 999			   pci_name(asd_ha->pcidev));
1000		pci_write_config_dword(asd_ha->pcidev,PCIX_STATUS,pcix_status);
1001		/* ignore */
1002		return;
1003	} else if (pcix_status & SC_DISCARD)
1004		asd_printk("split completion discarded for %s\n",
1005			   pci_name(asd_ha->pcidev));
1006	else if (ecc_status & UNCOR_ECCERR)
1007		asd_printk("uncorrectable ECC error for %s\n",
1008			   pci_name(asd_ha->pcidev));
1009	asd_chip_reset(asd_ha);
1010}
1011
1012/**
1013 * asd_hw_isr -- host adapter interrupt service routine
1014 * @irq: ignored
1015 * @dev_id: pointer to host adapter structure
1016 *
1017 * The ISR processes done list entries and level 3 error handling.
1018 */
1019irqreturn_t asd_hw_isr(int irq, void *dev_id)
1020{
1021	struct asd_ha_struct *asd_ha = dev_id;
1022	u32 chimint = asd_read_reg_dword(asd_ha, CHIMINT);
1023
1024	if (!chimint)
1025		return IRQ_NONE;
1026
1027	asd_write_reg_dword(asd_ha, CHIMINT, chimint);
1028	(void) asd_read_reg_dword(asd_ha, CHIMINT);
1029
1030	if (chimint & DLAVAIL)
1031		asd_process_donelist_isr(asd_ha);
1032	if (chimint & COMINT)
1033		asd_com_sas_isr(asd_ha);
1034	if (chimint & DEVINT)
1035		asd_dch_sas_isr(asd_ha);
1036	if (chimint & INITERR)
1037		asd_rbi_exsi_isr(asd_ha);
1038	if (chimint & HOSTERR)
1039		asd_hst_pcix_isr(asd_ha);
1040
1041	return IRQ_HANDLED;
1042}
1043
1044/* ---------- SCB handling ---------- */
1045
1046static struct asd_ascb *asd_ascb_alloc(struct asd_ha_struct *asd_ha,
1047				       gfp_t gfp_flags)
1048{
1049	extern struct kmem_cache *asd_ascb_cache;
1050	struct asd_seq_data *seq = &asd_ha->seq;
1051	struct asd_ascb *ascb;
1052	unsigned long flags;
1053
1054	ascb = kmem_cache_zalloc(asd_ascb_cache, gfp_flags);
1055
1056	if (ascb) {
1057		ascb->dma_scb.size = sizeof(struct scb);
1058		ascb->dma_scb.vaddr = dma_pool_alloc(asd_ha->scb_pool,
1059						     gfp_flags,
1060						    &ascb->dma_scb.dma_handle);
1061		if (!ascb->dma_scb.vaddr) {
1062			kmem_cache_free(asd_ascb_cache, ascb);
1063			return NULL;
1064		}
1065		memset(ascb->dma_scb.vaddr, 0, sizeof(struct scb));
1066		asd_init_ascb(asd_ha, ascb);
1067
1068		spin_lock_irqsave(&seq->tc_index_lock, flags);
1069		ascb->tc_index = asd_tc_index_get(seq, ascb);
1070		spin_unlock_irqrestore(&seq->tc_index_lock, flags);
1071		if (ascb->tc_index == -1)
1072			goto undo;
1073
1074		ascb->scb->header.index = cpu_to_le16((u16)ascb->tc_index);
1075	}
1076
1077	return ascb;
1078undo:
1079	dma_pool_free(asd_ha->scb_pool, ascb->dma_scb.vaddr,
1080		      ascb->dma_scb.dma_handle);
1081	kmem_cache_free(asd_ascb_cache, ascb);
1082	ASD_DPRINTK("no index for ascb\n");
1083	return NULL;
1084}
1085
1086/**
1087 * asd_ascb_alloc_list -- allocate a list of aSCBs
1088 * @asd_ha: pointer to host adapter structure
1089 * @num: pointer to integer number of aSCBs
1090 * @gfp_flags: GFP_ flags.
1091 *
1092 * This is the only function which is used to allocate aSCBs.
1093 * It can allocate one or many. If more than one, then they form
1094 * a linked list in two ways: by their list field of the ascb struct
1095 * and by the next_scb field of the scb_header.
1096 *
1097 * Returns NULL if no memory was available, else pointer to a list
1098 * of ascbs.  When this function returns, @num would be the number
1099 * of SCBs which were not able to be allocated, 0 if all requested
1100 * were able to be allocated.
1101 */
1102struct asd_ascb *asd_ascb_alloc_list(struct asd_ha_struct
1103				     *asd_ha, int *num,
1104				     gfp_t gfp_flags)
1105{
1106	struct asd_ascb *first = NULL;
1107
1108	for ( ; *num > 0; --*num) {
1109		struct asd_ascb *ascb = asd_ascb_alloc(asd_ha, gfp_flags);
1110
1111		if (!ascb)
1112			break;
1113		else if (!first)
1114			first = ascb;
1115		else {
1116			struct asd_ascb *last = list_entry(first->list.prev,
1117							   struct asd_ascb,
1118							   list);
1119			list_add_tail(&ascb->list, &first->list);
1120			last->scb->header.next_scb =
1121				cpu_to_le64(((u64)ascb->dma_scb.dma_handle));
1122		}
1123	}
1124
1125	return first;
1126}
1127
1128/**
1129 * asd_swap_head_scb -- swap the head scb
1130 * @asd_ha: pointer to host adapter structure
1131 * @ascb: pointer to the head of an ascb list
1132 *
1133 * The sequencer knows the DMA address of the next SCB to be DMAed to
1134 * the host adapter, from initialization or from the last list DMAed.
1135 * seq->next_scb keeps the address of this SCB.  The sequencer will
1136 * DMA to the host adapter this list of SCBs.  But the head (first
1137 * element) of this list is not known to the sequencer.  Here we swap
1138 * the head of the list with the known SCB (memcpy()).
1139 * Only one memcpy() is required per list so it is in our interest
1140 * to keep the list of SCB as long as possible so that the ratio
1141 * of number of memcpy calls to the number of SCB DMA-ed is as small
1142 * as possible.
1143 *
1144 * LOCKING: called with the pending list lock held.
1145 */
1146static void asd_swap_head_scb(struct asd_ha_struct *asd_ha,
1147			      struct asd_ascb *ascb)
1148{
1149	struct asd_seq_data *seq = &asd_ha->seq;
1150	struct asd_ascb *last = list_entry(ascb->list.prev,
1151					   struct asd_ascb,
1152					   list);
1153	struct asd_dma_tok t = ascb->dma_scb;
1154
1155	memcpy(seq->next_scb.vaddr, ascb->scb, sizeof(*ascb->scb));
1156	ascb->dma_scb = seq->next_scb;
1157	ascb->scb = ascb->dma_scb.vaddr;
1158	seq->next_scb = t;
1159	last->scb->header.next_scb =
1160		cpu_to_le64(((u64)seq->next_scb.dma_handle));
1161}
1162
1163/**
1164 * asd_start_timers -- (add and) start timers of SCBs
1165 * @list: pointer to struct list_head of the scbs
1166 * @to: timeout in jiffies
1167 *
1168 * If an SCB in the @list has no timer function, assign the default
1169 * one,  then start the timer of the SCB.  This function is
1170 * intended to be called from asd_post_ascb_list(), just prior to
1171 * posting the SCBs to the sequencer.
1172 */
1173static void asd_start_scb_timers(struct list_head *list)
1174{
1175	struct asd_ascb *ascb;
1176	list_for_each_entry(ascb, list, list) {
1177		if (!ascb->uldd_timer) {
1178			ascb->timer.data = (unsigned long) ascb;
1179			ascb->timer.function = asd_ascb_timedout;
1180			ascb->timer.expires = jiffies + AIC94XX_SCB_TIMEOUT;
1181			add_timer(&ascb->timer);
1182		}
1183	}
1184}
1185
1186/**
1187 * asd_post_ascb_list -- post a list of 1 or more aSCBs to the host adapter
1188 * @asd_ha: pointer to a host adapter structure
1189 * @ascb: pointer to the first aSCB in the list
1190 * @num: number of aSCBs in the list (to be posted)
1191 *
1192 * See queueing comment in asd_post_escb_list().
1193 *
1194 * Additional note on queuing: In order to minimize the ratio of memcpy()
1195 * to the number of ascbs sent, we try to batch-send as many ascbs as possible
1196 * in one go.
1197 * Two cases are possible:
1198 *    A) can_queue >= num,
1199 *    B) can_queue < num.
1200 * Case A: we can send the whole batch at once.  Increment "pending"
1201 * in the beginning of this function, when it is checked, in order to
1202 * eliminate races when this function is called by multiple processes.
1203 * Case B: should never happen if the managing layer considers
1204 * lldd_queue_size.
1205 */
1206int asd_post_ascb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
1207		       int num)
1208{
1209	unsigned long flags;
1210	LIST_HEAD(list);
1211	int can_queue;
1212
1213	spin_lock_irqsave(&asd_ha->seq.pend_q_lock, flags);
1214	can_queue = asd_ha->hw_prof.max_scbs - asd_ha->seq.pending;
1215	if (can_queue >= num)
1216		asd_ha->seq.pending += num;
1217	else
1218		can_queue = 0;
1219
1220	if (!can_queue) {
1221		spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
1222		asd_printk("%s: scb queue full\n", pci_name(asd_ha->pcidev));
1223		return -SAS_QUEUE_FULL;
1224	}
1225
1226	asd_swap_head_scb(asd_ha, ascb);
1227
1228	__list_add(&list, ascb->list.prev, &ascb->list);
1229
1230	asd_start_scb_timers(&list);
1231
1232	asd_ha->seq.scbpro += num;
1233	list_splice_init(&list, asd_ha->seq.pend_q.prev);
1234	asd_write_reg_dword(asd_ha, SCBPRO, (u32)asd_ha->seq.scbpro);
1235	spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
1236
1237	return 0;
1238}
1239
1240/**
1241 * asd_post_escb_list -- post a list of 1 or more empty scb
1242 * @asd_ha: pointer to a host adapter structure
1243 * @ascb: pointer to the first empty SCB in the list
1244 * @num: number of aSCBs in the list (to be posted)
1245 *
1246 * This is essentially the same as asd_post_ascb_list, but we do not
1247 * increment pending, add those to the pending list or get indexes.
1248 * See asd_init_escbs() and asd_init_post_escbs().
1249 *
1250 * Since sending a list of ascbs is a superset of sending a single
1251 * ascb, this function exists to generalize this.  More specifically,
1252 * when sending a list of those, we want to do only a _single_
1253 * memcpy() at swap head, as opposed to for each ascb sent (in the
1254 * case of sending them one by one).  That is, we want to minimize the
1255 * ratio of memcpy() operations to the number of ascbs sent.  The same
1256 * logic applies to asd_post_ascb_list().
1257 */
1258int asd_post_escb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
1259		       int num)
1260{
1261	unsigned long flags;
1262
1263	spin_lock_irqsave(&asd_ha->seq.pend_q_lock, flags);
1264	asd_swap_head_scb(asd_ha, ascb);
1265	asd_ha->seq.scbpro += num;
1266	asd_write_reg_dword(asd_ha, SCBPRO, (u32)asd_ha->seq.scbpro);
1267	spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
1268
1269	return 0;
1270}
1271
1272/* ---------- LED ---------- */
1273
1274/**
1275 * asd_turn_led -- turn on/off an LED
1276 * @asd_ha: pointer to host adapter structure
1277 * @phy_id: the PHY id whose LED we want to manupulate
1278 * @op: 1 to turn on, 0 to turn off
1279 */
1280void asd_turn_led(struct asd_ha_struct *asd_ha, int phy_id, int op)
1281{
1282	if (phy_id < ASD_MAX_PHYS) {
1283		u32 v = asd_read_reg_dword(asd_ha, LmCONTROL(phy_id));
1284		if (op)
1285			v |= LEDPOL;
1286		else
1287			v &= ~LEDPOL;
1288		asd_write_reg_dword(asd_ha, LmCONTROL(phy_id), v);
1289	}
1290}
1291
1292/**
1293 * asd_control_led -- enable/disable an LED on the board
1294 * @asd_ha: pointer to host adapter structure
1295 * @phy_id: integer, the phy id
1296 * @op: integer, 1 to enable, 0 to disable the LED
1297 *
1298 * First we output enable the LED, then we set the source
1299 * to be an external module.
1300 */
1301void asd_control_led(struct asd_ha_struct *asd_ha, int phy_id, int op)
1302{
1303	if (phy_id < ASD_MAX_PHYS) {
1304		u32 v;
1305
1306		v = asd_read_reg_dword(asd_ha, GPIOOER);
1307		if (op)
1308			v |= (1 << phy_id);
1309		else
1310			v &= ~(1 << phy_id);
1311		asd_write_reg_dword(asd_ha, GPIOOER, v);
1312
1313		v = asd_read_reg_dword(asd_ha, GPIOCNFGR);
1314		if (op)
1315			v |= (1 << phy_id);
1316		else
1317			v &= ~(1 << phy_id);
1318		asd_write_reg_dword(asd_ha, GPIOCNFGR, v);
1319	}
1320}
1321
1322/* ---------- PHY enable ---------- */
1323
1324static int asd_enable_phy(struct asd_ha_struct *asd_ha, int phy_id)
1325{
1326	struct asd_phy *phy = &asd_ha->phys[phy_id];
1327
1328	asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, INT_ENABLE_2), 0);
1329	asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, HOT_PLUG_DELAY),
1330			   HOTPLUG_DELAY_TIMEOUT);
1331
1332	/* Get defaults from manuf. sector */
1333	/* XXX we need defaults for those in case MS is broken. */
1334	asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_0),
1335			   phy->phy_desc->phy_control_0);
1336	asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_1),
1337			   phy->phy_desc->phy_control_1);
1338	asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_2),
1339			   phy->phy_desc->phy_control_2);
1340	asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_3),
1341			   phy->phy_desc->phy_control_3);
1342
1343	asd_write_reg_dword(asd_ha, LmSEQ_TEN_MS_COMINIT_TIMEOUT(phy_id),
1344			    ASD_COMINIT_TIMEOUT);
1345
1346	asd_write_reg_addr(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(phy_id),
1347			   phy->id_frm_tok->dma_handle);
1348
1349	asd_control_led(asd_ha, phy_id, 1);
1350
1351	return 0;
1352}
1353
1354int asd_enable_phys(struct asd_ha_struct *asd_ha, const u8 phy_mask)
1355{
1356	u8  phy_m;
1357	u8  i;
1358	int num = 0, k;
1359	struct asd_ascb *ascb;
1360	struct asd_ascb *ascb_list;
1361
1362	if (!phy_mask) {
1363		asd_printk("%s called with phy_mask of 0!?\n", __func__);
1364		return 0;
1365	}
1366
1367	for_each_phy(phy_mask, phy_m, i) {
1368		num++;
1369		asd_enable_phy(asd_ha, i);
1370	}
1371
1372	k = num;
1373	ascb_list = asd_ascb_alloc_list(asd_ha, &k, GFP_KERNEL);
1374	if (!ascb_list) {
1375		asd_printk("no memory for control phy ascb list\n");
1376		return -ENOMEM;
1377	}
1378	num -= k;
1379
1380	ascb = ascb_list;
1381	for_each_phy(phy_mask, phy_m, i) {
1382		asd_build_control_phy(ascb, i, ENABLE_PHY);
1383		ascb = list_entry(ascb->list.next, struct asd_ascb, list);
1384	}
1385	ASD_DPRINTK("posting %d control phy scbs\n", num);
1386	k = asd_post_ascb_list(asd_ha, ascb_list, num);
1387	if (k)
1388		asd_ascb_free_list(ascb_list);
1389
1390	return k;
1391}