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1/*
2 * An SPI driver for the Philips PCF2123 RTC
3 * Copyright 2009 Cyber Switching, Inc.
4 *
5 * Author: Chris Verges <chrisv@cyberswitching.com>
6 * Maintainers: http://www.cyberswitching.com
7 *
8 * based on the RS5C348 driver in this same directory.
9 *
10 * Thanks to Christian Pellegrin <chripell@fsfe.org> for
11 * the sysfs contributions to this driver.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 * Please note that the CS is active high, so platform data
18 * should look something like:
19 *
20 * static struct spi_board_info ek_spi_devices[] = {
21 * ...
22 * {
23 * .modalias = "rtc-pcf2123",
24 * .chip_select = 1,
25 * .controller_data = (void *)AT91_PIN_PA10,
26 * .max_speed_hz = 1000 * 1000,
27 * .mode = SPI_CS_HIGH,
28 * .bus_num = 0,
29 * },
30 * ...
31 *};
32 *
33 */
34
35#include <linux/bcd.h>
36#include <linux/delay.h>
37#include <linux/device.h>
38#include <linux/errno.h>
39#include <linux/init.h>
40#include <linux/kernel.h>
41#include <linux/string.h>
42#include <linux/slab.h>
43#include <linux/rtc.h>
44#include <linux/spi/spi.h>
45#include <linux/module.h>
46#include <linux/sysfs.h>
47
48#define DRV_VERSION "0.6"
49
50#define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
51#define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
52#define PCF2123_REG_SC (0x02) /* datetime */
53#define PCF2123_REG_MN (0x03)
54#define PCF2123_REG_HR (0x04)
55#define PCF2123_REG_DM (0x05)
56#define PCF2123_REG_DW (0x06)
57#define PCF2123_REG_MO (0x07)
58#define PCF2123_REG_YR (0x08)
59
60#define PCF2123_SUBADDR (1 << 4)
61#define PCF2123_WRITE ((0 << 7) | PCF2123_SUBADDR)
62#define PCF2123_READ ((1 << 7) | PCF2123_SUBADDR)
63
64static struct spi_driver pcf2123_driver;
65
66struct pcf2123_sysfs_reg {
67 struct device_attribute attr;
68 char name[2];
69};
70
71struct pcf2123_plat_data {
72 struct rtc_device *rtc;
73 struct pcf2123_sysfs_reg regs[16];
74};
75
76/*
77 * Causes a 30 nanosecond delay to ensure that the PCF2123 chip select
78 * is released properly after an SPI write. This function should be
79 * called after EVERY read/write call over SPI.
80 */
81static inline void pcf2123_delay_trec(void)
82{
83 ndelay(30);
84}
85
86static ssize_t pcf2123_show(struct device *dev, struct device_attribute *attr,
87 char *buffer)
88{
89 struct spi_device *spi = to_spi_device(dev);
90 struct pcf2123_sysfs_reg *r;
91 u8 txbuf[1], rxbuf[1];
92 unsigned long reg;
93 int ret;
94
95 r = container_of(attr, struct pcf2123_sysfs_reg, attr);
96
97 ret = kstrtoul(r->name, 16, ®);
98 if (ret)
99 return ret;
100
101 txbuf[0] = PCF2123_READ | reg;
102 ret = spi_write_then_read(spi, txbuf, 1, rxbuf, 1);
103 if (ret < 0)
104 return -EIO;
105 pcf2123_delay_trec();
106 return sprintf(buffer, "0x%x\n", rxbuf[0]);
107}
108
109static ssize_t pcf2123_store(struct device *dev, struct device_attribute *attr,
110 const char *buffer, size_t count) {
111 struct spi_device *spi = to_spi_device(dev);
112 struct pcf2123_sysfs_reg *r;
113 u8 txbuf[2];
114 unsigned long reg;
115 unsigned long val;
116
117 int ret;
118
119 r = container_of(attr, struct pcf2123_sysfs_reg, attr);
120
121 ret = kstrtoul(r->name, 16, ®);
122 if (ret)
123 return ret;
124
125 ret = kstrtoul(buffer, 10, &val);
126 if (ret)
127 return ret;
128
129 txbuf[0] = PCF2123_WRITE | reg;
130 txbuf[1] = val;
131 ret = spi_write(spi, txbuf, sizeof(txbuf));
132 if (ret < 0)
133 return -EIO;
134 pcf2123_delay_trec();
135 return count;
136}
137
138static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
139{
140 struct spi_device *spi = to_spi_device(dev);
141 u8 txbuf[1], rxbuf[7];
142 int ret;
143
144 txbuf[0] = PCF2123_READ | PCF2123_REG_SC;
145 ret = spi_write_then_read(spi, txbuf, sizeof(txbuf),
146 rxbuf, sizeof(rxbuf));
147 if (ret < 0)
148 return ret;
149 pcf2123_delay_trec();
150
151 tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
152 tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
153 tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
154 tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
155 tm->tm_wday = rxbuf[4] & 0x07;
156 tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
157 tm->tm_year = bcd2bin(rxbuf[6]);
158 if (tm->tm_year < 70)
159 tm->tm_year += 100; /* assume we are in 1970...2069 */
160
161 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
162 "mday=%d, mon=%d, year=%d, wday=%d\n",
163 __func__,
164 tm->tm_sec, tm->tm_min, tm->tm_hour,
165 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
166
167 /* the clock can give out invalid datetime, but we cannot return
168 * -EINVAL otherwise hwclock will refuse to set the time on bootup.
169 */
170 if (rtc_valid_tm(tm) < 0)
171 dev_err(dev, "retrieved date/time is not valid.\n");
172
173 return 0;
174}
175
176static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
177{
178 struct spi_device *spi = to_spi_device(dev);
179 u8 txbuf[8];
180 int ret;
181
182 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
183 "mday=%d, mon=%d, year=%d, wday=%d\n",
184 __func__,
185 tm->tm_sec, tm->tm_min, tm->tm_hour,
186 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
187
188 /* Stop the counter first */
189 txbuf[0] = PCF2123_WRITE | PCF2123_REG_CTRL1;
190 txbuf[1] = 0x20;
191 ret = spi_write(spi, txbuf, 2);
192 if (ret < 0)
193 return ret;
194 pcf2123_delay_trec();
195
196 /* Set the new time */
197 txbuf[0] = PCF2123_WRITE | PCF2123_REG_SC;
198 txbuf[1] = bin2bcd(tm->tm_sec & 0x7F);
199 txbuf[2] = bin2bcd(tm->tm_min & 0x7F);
200 txbuf[3] = bin2bcd(tm->tm_hour & 0x3F);
201 txbuf[4] = bin2bcd(tm->tm_mday & 0x3F);
202 txbuf[5] = tm->tm_wday & 0x07;
203 txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
204 txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);
205
206 ret = spi_write(spi, txbuf, sizeof(txbuf));
207 if (ret < 0)
208 return ret;
209 pcf2123_delay_trec();
210
211 /* Start the counter */
212 txbuf[0] = PCF2123_WRITE | PCF2123_REG_CTRL1;
213 txbuf[1] = 0x00;
214 ret = spi_write(spi, txbuf, 2);
215 if (ret < 0)
216 return ret;
217 pcf2123_delay_trec();
218
219 return 0;
220}
221
222static const struct rtc_class_ops pcf2123_rtc_ops = {
223 .read_time = pcf2123_rtc_read_time,
224 .set_time = pcf2123_rtc_set_time,
225};
226
227static int pcf2123_probe(struct spi_device *spi)
228{
229 struct rtc_device *rtc;
230 struct pcf2123_plat_data *pdata;
231 u8 txbuf[2], rxbuf[2];
232 int ret, i;
233
234 pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
235 GFP_KERNEL);
236 if (!pdata)
237 return -ENOMEM;
238 spi->dev.platform_data = pdata;
239
240 /* Send a software reset command */
241 txbuf[0] = PCF2123_WRITE | PCF2123_REG_CTRL1;
242 txbuf[1] = 0x58;
243 dev_dbg(&spi->dev, "resetting RTC (0x%02X 0x%02X)\n",
244 txbuf[0], txbuf[1]);
245 ret = spi_write(spi, txbuf, 2 * sizeof(u8));
246 if (ret < 0)
247 goto kfree_exit;
248 pcf2123_delay_trec();
249
250 /* Stop the counter */
251 txbuf[0] = PCF2123_WRITE | PCF2123_REG_CTRL1;
252 txbuf[1] = 0x20;
253 dev_dbg(&spi->dev, "stopping RTC (0x%02X 0x%02X)\n",
254 txbuf[0], txbuf[1]);
255 ret = spi_write(spi, txbuf, 2 * sizeof(u8));
256 if (ret < 0)
257 goto kfree_exit;
258 pcf2123_delay_trec();
259
260 /* See if the counter was actually stopped */
261 txbuf[0] = PCF2123_READ | PCF2123_REG_CTRL1;
262 dev_dbg(&spi->dev, "checking for presence of RTC (0x%02X)\n",
263 txbuf[0]);
264 ret = spi_write_then_read(spi, txbuf, 1 * sizeof(u8),
265 rxbuf, 2 * sizeof(u8));
266 dev_dbg(&spi->dev, "received data from RTC (0x%02X 0x%02X)\n",
267 rxbuf[0], rxbuf[1]);
268 if (ret < 0)
269 goto kfree_exit;
270 pcf2123_delay_trec();
271
272 if (!(rxbuf[0] & 0x20)) {
273 dev_err(&spi->dev, "chip not found\n");
274 ret = -ENODEV;
275 goto kfree_exit;
276 }
277
278 dev_info(&spi->dev, "chip found, driver version " DRV_VERSION "\n");
279 dev_info(&spi->dev, "spiclk %u KHz.\n",
280 (spi->max_speed_hz + 500) / 1000);
281
282 /* Start the counter */
283 txbuf[0] = PCF2123_WRITE | PCF2123_REG_CTRL1;
284 txbuf[1] = 0x00;
285 ret = spi_write(spi, txbuf, sizeof(txbuf));
286 if (ret < 0)
287 goto kfree_exit;
288 pcf2123_delay_trec();
289
290 /* Finalize the initialization */
291 rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
292 &pcf2123_rtc_ops, THIS_MODULE);
293
294 if (IS_ERR(rtc)) {
295 dev_err(&spi->dev, "failed to register.\n");
296 ret = PTR_ERR(rtc);
297 goto kfree_exit;
298 }
299
300 pdata->rtc = rtc;
301
302 for (i = 0; i < 16; i++) {
303 sysfs_attr_init(&pdata->regs[i].attr.attr);
304 sprintf(pdata->regs[i].name, "%1x", i);
305 pdata->regs[i].attr.attr.mode = S_IRUGO | S_IWUSR;
306 pdata->regs[i].attr.attr.name = pdata->regs[i].name;
307 pdata->regs[i].attr.show = pcf2123_show;
308 pdata->regs[i].attr.store = pcf2123_store;
309 ret = device_create_file(&spi->dev, &pdata->regs[i].attr);
310 if (ret) {
311 dev_err(&spi->dev, "Unable to create sysfs %s\n",
312 pdata->regs[i].name);
313 goto sysfs_exit;
314 }
315 }
316
317 return 0;
318
319sysfs_exit:
320 for (i--; i >= 0; i--)
321 device_remove_file(&spi->dev, &pdata->regs[i].attr);
322
323kfree_exit:
324 spi->dev.platform_data = NULL;
325 return ret;
326}
327
328static int pcf2123_remove(struct spi_device *spi)
329{
330 struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev);
331 int i;
332
333 if (pdata) {
334 for (i = 0; i < 16; i++)
335 if (pdata->regs[i].name[0])
336 device_remove_file(&spi->dev,
337 &pdata->regs[i].attr);
338 }
339
340 return 0;
341}
342
343static struct spi_driver pcf2123_driver = {
344 .driver = {
345 .name = "rtc-pcf2123",
346 .owner = THIS_MODULE,
347 },
348 .probe = pcf2123_probe,
349 .remove = pcf2123_remove,
350};
351
352module_spi_driver(pcf2123_driver);
353
354MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
355MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
356MODULE_LICENSE("GPL");
357MODULE_VERSION(DRV_VERSION);
1/*
2 * An SPI driver for the Philips PCF2123 RTC
3 * Copyright 2009 Cyber Switching, Inc.
4 *
5 * Author: Chris Verges <chrisv@cyberswitching.com>
6 * Maintainers: http://www.cyberswitching.com
7 *
8 * based on the RS5C348 driver in this same directory.
9 *
10 * Thanks to Christian Pellegrin <chripell@fsfe.org> for
11 * the sysfs contributions to this driver.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 * Please note that the CS is active high, so platform data
18 * should look something like:
19 *
20 * static struct spi_board_info ek_spi_devices[] = {
21 * ...
22 * {
23 * .modalias = "rtc-pcf2123",
24 * .chip_select = 1,
25 * .controller_data = (void *)AT91_PIN_PA10,
26 * .max_speed_hz = 1000 * 1000,
27 * .mode = SPI_CS_HIGH,
28 * .bus_num = 0,
29 * },
30 * ...
31 *};
32 *
33 */
34
35#include <linux/bcd.h>
36#include <linux/delay.h>
37#include <linux/device.h>
38#include <linux/errno.h>
39#include <linux/init.h>
40#include <linux/kernel.h>
41#include <linux/of.h>
42#include <linux/string.h>
43#include <linux/slab.h>
44#include <linux/rtc.h>
45#include <linux/spi/spi.h>
46#include <linux/module.h>
47#include <linux/sysfs.h>
48
49/* REGISTERS */
50#define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
51#define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
52#define PCF2123_REG_SC (0x02) /* datetime */
53#define PCF2123_REG_MN (0x03)
54#define PCF2123_REG_HR (0x04)
55#define PCF2123_REG_DM (0x05)
56#define PCF2123_REG_DW (0x06)
57#define PCF2123_REG_MO (0x07)
58#define PCF2123_REG_YR (0x08)
59#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */
60#define PCF2123_REG_ALRM_HR (0x0a)
61#define PCF2123_REG_ALRM_DM (0x0b)
62#define PCF2123_REG_ALRM_DW (0x0c)
63#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */
64#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */
65#define PCF2123_REG_CTDWN_TMR (0x0f)
66
67/* PCF2123_REG_CTRL1 BITS */
68#define CTRL1_CLEAR (0) /* Clear */
69#define CTRL1_CORR_INT BIT(1) /* Correction irq enable */
70#define CTRL1_12_HOUR BIT(2) /* 12 hour time */
71#define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */
72#define CTRL1_STOP BIT(5) /* Stop the clock */
73#define CTRL1_EXT_TEST BIT(7) /* External clock test mode */
74
75/* PCF2123_REG_CTRL2 BITS */
76#define CTRL2_TIE BIT(0) /* Countdown timer irq enable */
77#define CTRL2_AIE BIT(1) /* Alarm irq enable */
78#define CTRL2_TF BIT(2) /* Countdown timer flag */
79#define CTRL2_AF BIT(3) /* Alarm flag */
80#define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */
81#define CTRL2_MSF BIT(5) /* Minute or second irq flag */
82#define CTRL2_SI BIT(6) /* Second irq enable */
83#define CTRL2_MI BIT(7) /* Minute irq enable */
84
85/* PCF2123_REG_SC BITS */
86#define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */
87
88/* PCF2123_REG_ALRM_XX BITS */
89#define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */
90
91/* PCF2123_REG_TMR_CLKOUT BITS */
92#define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */
93#define CD_TMR_64HZ (1) /* 64 Hz countdown timer */
94#define CD_TMR_1HZ (2) /* 1 Hz countdown timer */
95#define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */
96#define CD_TMR_TE BIT(3) /* Countdown timer enable */
97
98/* PCF2123_REG_OFFSET BITS */
99#define OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
100#define OFFSET_COARSE BIT(7) /* Coarse mode offset */
101#define OFFSET_STEP (2170) /* Offset step in parts per billion */
102
103/* READ/WRITE ADDRESS BITS */
104#define PCF2123_WRITE BIT(4)
105#define PCF2123_READ (BIT(4) | BIT(7))
106
107
108static struct spi_driver pcf2123_driver;
109
110struct pcf2123_sysfs_reg {
111 struct device_attribute attr;
112 char name[2];
113};
114
115struct pcf2123_plat_data {
116 struct rtc_device *rtc;
117 struct pcf2123_sysfs_reg regs[16];
118};
119
120/*
121 * Causes a 30 nanosecond delay to ensure that the PCF2123 chip select
122 * is released properly after an SPI write. This function should be
123 * called after EVERY read/write call over SPI.
124 */
125static inline void pcf2123_delay_trec(void)
126{
127 ndelay(30);
128}
129
130static int pcf2123_read(struct device *dev, u8 reg, u8 *rxbuf, size_t size)
131{
132 struct spi_device *spi = to_spi_device(dev);
133 int ret;
134
135 reg |= PCF2123_READ;
136 ret = spi_write_then_read(spi, ®, 1, rxbuf, size);
137 pcf2123_delay_trec();
138
139 return ret;
140}
141
142static int pcf2123_write(struct device *dev, u8 *txbuf, size_t size)
143{
144 struct spi_device *spi = to_spi_device(dev);
145 int ret;
146
147 txbuf[0] |= PCF2123_WRITE;
148 ret = spi_write(spi, txbuf, size);
149 pcf2123_delay_trec();
150
151 return ret;
152}
153
154static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val)
155{
156 u8 txbuf[2];
157
158 txbuf[0] = reg;
159 txbuf[1] = val;
160 return pcf2123_write(dev, txbuf, sizeof(txbuf));
161}
162
163static ssize_t pcf2123_show(struct device *dev, struct device_attribute *attr,
164 char *buffer)
165{
166 struct pcf2123_sysfs_reg *r;
167 u8 rxbuf[1];
168 unsigned long reg;
169 int ret;
170
171 r = container_of(attr, struct pcf2123_sysfs_reg, attr);
172
173 ret = kstrtoul(r->name, 16, ®);
174 if (ret)
175 return ret;
176
177 ret = pcf2123_read(dev, reg, rxbuf, 1);
178 if (ret < 0)
179 return -EIO;
180
181 return sprintf(buffer, "0x%x\n", rxbuf[0]);
182}
183
184static ssize_t pcf2123_store(struct device *dev, struct device_attribute *attr,
185 const char *buffer, size_t count)
186{
187 struct pcf2123_sysfs_reg *r;
188 unsigned long reg;
189 unsigned long val;
190
191 int ret;
192
193 r = container_of(attr, struct pcf2123_sysfs_reg, attr);
194
195 ret = kstrtoul(r->name, 16, ®);
196 if (ret)
197 return ret;
198
199 ret = kstrtoul(buffer, 10, &val);
200 if (ret)
201 return ret;
202
203 ret = pcf2123_write_reg(dev, reg, val);
204 if (ret < 0)
205 return -EIO;
206 return count;
207}
208
209static int pcf2123_read_offset(struct device *dev, long *offset)
210{
211 int ret;
212 s8 reg;
213
214 ret = pcf2123_read(dev, PCF2123_REG_OFFSET, ®, 1);
215 if (ret < 0)
216 return ret;
217
218 if (reg & OFFSET_COARSE)
219 reg <<= 1; /* multiply by 2 and sign extend */
220 else
221 reg = sign_extend32(reg, OFFSET_SIGN_BIT);
222
223 *offset = ((long)reg) * OFFSET_STEP;
224
225 return 0;
226}
227
228/*
229 * The offset register is a 7 bit signed value with a coarse bit in bit 7.
230 * The main difference between the two is normal offset adjusts the first
231 * second of n minutes every other hour, with 61, 62 and 63 being shoved
232 * into the 60th minute.
233 * The coarse adjustment does the same, but every hour.
234 * the two overlap, with every even normal offset value corresponding
235 * to a coarse offset. Based on this algorithm, it seems that despite the
236 * name, coarse offset is a better fit for overlapping values.
237 */
238static int pcf2123_set_offset(struct device *dev, long offset)
239{
240 s8 reg;
241
242 if (offset > OFFSET_STEP * 127)
243 reg = 127;
244 else if (offset < OFFSET_STEP * -128)
245 reg = -128;
246 else
247 reg = (s8)((offset + (OFFSET_STEP >> 1)) / OFFSET_STEP);
248
249 /* choose fine offset only for odd values in the normal range */
250 if (reg & 1 && reg <= 63 && reg >= -64) {
251 /* Normal offset. Clear the coarse bit */
252 reg &= ~OFFSET_COARSE;
253 } else {
254 /* Coarse offset. Divide by 2 and set the coarse bit */
255 reg >>= 1;
256 reg |= OFFSET_COARSE;
257 }
258
259 return pcf2123_write_reg(dev, PCF2123_REG_OFFSET, reg);
260}
261
262static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
263{
264 u8 rxbuf[7];
265 int ret;
266
267 ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf));
268 if (ret < 0)
269 return ret;
270
271 if (rxbuf[0] & OSC_HAS_STOPPED) {
272 dev_info(dev, "clock was stopped. Time is not valid\n");
273 return -EINVAL;
274 }
275
276 tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
277 tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
278 tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
279 tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
280 tm->tm_wday = rxbuf[4] & 0x07;
281 tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
282 tm->tm_year = bcd2bin(rxbuf[6]);
283 if (tm->tm_year < 70)
284 tm->tm_year += 100; /* assume we are in 1970...2069 */
285
286 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
287 "mday=%d, mon=%d, year=%d, wday=%d\n",
288 __func__,
289 tm->tm_sec, tm->tm_min, tm->tm_hour,
290 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
291
292 return 0;
293}
294
295static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
296{
297 u8 txbuf[8];
298 int ret;
299
300 dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
301 "mday=%d, mon=%d, year=%d, wday=%d\n",
302 __func__,
303 tm->tm_sec, tm->tm_min, tm->tm_hour,
304 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
305
306 /* Stop the counter first */
307 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
308 if (ret < 0)
309 return ret;
310
311 /* Set the new time */
312 txbuf[0] = PCF2123_REG_SC;
313 txbuf[1] = bin2bcd(tm->tm_sec & 0x7F);
314 txbuf[2] = bin2bcd(tm->tm_min & 0x7F);
315 txbuf[3] = bin2bcd(tm->tm_hour & 0x3F);
316 txbuf[4] = bin2bcd(tm->tm_mday & 0x3F);
317 txbuf[5] = tm->tm_wday & 0x07;
318 txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
319 txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);
320
321 ret = pcf2123_write(dev, txbuf, sizeof(txbuf));
322 if (ret < 0)
323 return ret;
324
325 /* Start the counter */
326 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
327 if (ret < 0)
328 return ret;
329
330 return 0;
331}
332
333static int pcf2123_reset(struct device *dev)
334{
335 int ret;
336 u8 rxbuf[2];
337
338 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
339 if (ret < 0)
340 return ret;
341
342 /* Stop the counter */
343 dev_dbg(dev, "stopping RTC\n");
344 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
345 if (ret < 0)
346 return ret;
347
348 /* See if the counter was actually stopped */
349 dev_dbg(dev, "checking for presence of RTC\n");
350 ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf));
351 if (ret < 0)
352 return ret;
353
354 dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n",
355 rxbuf[0], rxbuf[1]);
356 if (!(rxbuf[0] & CTRL1_STOP))
357 return -ENODEV;
358
359 /* Start the counter */
360 ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
361 if (ret < 0)
362 return ret;
363
364 return 0;
365}
366
367static const struct rtc_class_ops pcf2123_rtc_ops = {
368 .read_time = pcf2123_rtc_read_time,
369 .set_time = pcf2123_rtc_set_time,
370 .read_offset = pcf2123_read_offset,
371 .set_offset = pcf2123_set_offset,
372
373};
374
375static int pcf2123_probe(struct spi_device *spi)
376{
377 struct rtc_device *rtc;
378 struct rtc_time tm;
379 struct pcf2123_plat_data *pdata;
380 int ret, i;
381
382 pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
383 GFP_KERNEL);
384 if (!pdata)
385 return -ENOMEM;
386 spi->dev.platform_data = pdata;
387
388 ret = pcf2123_rtc_read_time(&spi->dev, &tm);
389 if (ret < 0) {
390 ret = pcf2123_reset(&spi->dev);
391 if (ret < 0) {
392 dev_err(&spi->dev, "chip not found\n");
393 goto kfree_exit;
394 }
395 }
396
397 dev_info(&spi->dev, "spiclk %u KHz.\n",
398 (spi->max_speed_hz + 500) / 1000);
399
400 /* Finalize the initialization */
401 rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
402 &pcf2123_rtc_ops, THIS_MODULE);
403
404 if (IS_ERR(rtc)) {
405 dev_err(&spi->dev, "failed to register.\n");
406 ret = PTR_ERR(rtc);
407 goto kfree_exit;
408 }
409
410 pdata->rtc = rtc;
411
412 for (i = 0; i < 16; i++) {
413 sysfs_attr_init(&pdata->regs[i].attr.attr);
414 sprintf(pdata->regs[i].name, "%1x", i);
415 pdata->regs[i].attr.attr.mode = S_IRUGO | S_IWUSR;
416 pdata->regs[i].attr.attr.name = pdata->regs[i].name;
417 pdata->regs[i].attr.show = pcf2123_show;
418 pdata->regs[i].attr.store = pcf2123_store;
419 ret = device_create_file(&spi->dev, &pdata->regs[i].attr);
420 if (ret) {
421 dev_err(&spi->dev, "Unable to create sysfs %s\n",
422 pdata->regs[i].name);
423 goto sysfs_exit;
424 }
425 }
426
427 return 0;
428
429sysfs_exit:
430 for (i--; i >= 0; i--)
431 device_remove_file(&spi->dev, &pdata->regs[i].attr);
432
433kfree_exit:
434 spi->dev.platform_data = NULL;
435 return ret;
436}
437
438static int pcf2123_remove(struct spi_device *spi)
439{
440 struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev);
441 int i;
442
443 if (pdata) {
444 for (i = 0; i < 16; i++)
445 if (pdata->regs[i].name[0])
446 device_remove_file(&spi->dev,
447 &pdata->regs[i].attr);
448 }
449
450 return 0;
451}
452
453#ifdef CONFIG_OF
454static const struct of_device_id pcf2123_dt_ids[] = {
455 { .compatible = "nxp,rtc-pcf2123", },
456 { /* sentinel */ }
457};
458MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
459#endif
460
461static struct spi_driver pcf2123_driver = {
462 .driver = {
463 .name = "rtc-pcf2123",
464 .of_match_table = of_match_ptr(pcf2123_dt_ids),
465 },
466 .probe = pcf2123_probe,
467 .remove = pcf2123_remove,
468};
469
470module_spi_driver(pcf2123_driver);
471
472MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
473MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
474MODULE_LICENSE("GPL");