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1/*
2 * Copyright (C) 2013 BayHub Technology Ltd.
3 *
4 * Authors: Peter Guo <peter.guo@bayhubtech.com>
5 * Adam Lee <adam.lee@canonical.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/pci.h>
19
20#include "sdhci.h"
21#include "sdhci-pci.h"
22#include "sdhci-pci-o2micro.h"
23
24void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
25{
26 u32 scratch_32;
27 int ret;
28 /* Improve write performance for SD3.0 */
29 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
30 if (ret)
31 return;
32 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
33 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
34
35 /* Enable Link abnormal reset generating Reset */
36 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
37 if (ret)
38 return;
39 scratch_32 &= ~((1 << 19) | (1 << 11));
40 scratch_32 |= (1 << 10);
41 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
42
43 /* set card power over current protection */
44 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
45 if (ret)
46 return;
47 scratch_32 |= (1 << 4);
48 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
49
50 /* adjust the output delay for SD mode */
51 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
52
53 /* Set the output voltage setting of Aux 1.2v LDO */
54 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
55 if (ret)
56 return;
57 scratch_32 &= ~(3 << 12);
58 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
59
60 /* Set Max power supply capability of SD host */
61 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
62 if (ret)
63 return;
64 scratch_32 &= ~(0x01FE);
65 scratch_32 |= 0x00CC;
66 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
67 /* Set DLL Tuning Window */
68 ret = pci_read_config_dword(chip->pdev,
69 O2_SD_TUNING_CTRL, &scratch_32);
70 if (ret)
71 return;
72 scratch_32 &= ~(0x000000FF);
73 scratch_32 |= 0x00000066;
74 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
75
76 /* Set UHS2 T_EIDLE */
77 ret = pci_read_config_dword(chip->pdev,
78 O2_SD_UHS2_L1_CTRL, &scratch_32);
79 if (ret)
80 return;
81 scratch_32 &= ~(0x000000FC);
82 scratch_32 |= 0x00000084;
83 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
84
85 /* Set UHS2 Termination */
86 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
87 if (ret)
88 return;
89 scratch_32 &= ~((1 << 21) | (1 << 30));
90
91 /* Set RTD3 function disabled */
92 scratch_32 |= ((1 << 29) | (1 << 28));
93 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
94
95 /* Set L1 Entrance Timer */
96 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
97 if (ret)
98 return;
99 scratch_32 &= ~(0xf0000000);
100 scratch_32 |= 0x30000000;
101 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
102
103 ret = pci_read_config_dword(chip->pdev,
104 O2_SD_MISC_CTRL4, &scratch_32);
105 if (ret)
106 return;
107 scratch_32 &= ~(0x000f0000);
108 scratch_32 |= 0x00080000;
109 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
110}
111EXPORT_SYMBOL_GPL(sdhci_pci_o2_fujin2_pci_init);
112
113int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
114{
115 struct sdhci_pci_chip *chip;
116 struct sdhci_host *host;
117 u32 reg;
118
119 chip = slot->chip;
120 host = slot->host;
121 switch (chip->pdev->device) {
122 case PCI_DEVICE_ID_O2_SDS0:
123 case PCI_DEVICE_ID_O2_SEABIRD0:
124 case PCI_DEVICE_ID_O2_SEABIRD1:
125 case PCI_DEVICE_ID_O2_SDS1:
126 case PCI_DEVICE_ID_O2_FUJIN2:
127 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
128 if (reg & 0x1)
129 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
130
131 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
132 break;
133 /* set dll watch dog timer */
134 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
135 reg |= (1 << 12);
136 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
137
138 break;
139 default:
140 break;
141 }
142
143 return 0;
144}
145EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe_slot);
146
147int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
148{
149 int ret;
150 u8 scratch;
151 u32 scratch_32;
152
153 switch (chip->pdev->device) {
154 case PCI_DEVICE_ID_O2_8220:
155 case PCI_DEVICE_ID_O2_8221:
156 case PCI_DEVICE_ID_O2_8320:
157 case PCI_DEVICE_ID_O2_8321:
158 /* This extra setup is required due to broken ADMA. */
159 ret = pci_read_config_byte(chip->pdev,
160 O2_SD_LOCK_WP, &scratch);
161 if (ret)
162 return ret;
163 scratch &= 0x7f;
164 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
165
166 /* Set Multi 3 to VCC3V# */
167 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
168
169 /* Disable CLK_REQ# support after media DET */
170 ret = pci_read_config_byte(chip->pdev,
171 O2_SD_CLKREQ, &scratch);
172 if (ret)
173 return ret;
174 scratch |= 0x20;
175 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
176
177 /* Choose capabilities, enable SDMA. We have to write 0x01
178 * to the capabilities register first to unlock it.
179 */
180 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
181 if (ret)
182 return ret;
183 scratch |= 0x01;
184 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
185 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
186
187 /* Disable ADMA1/2 */
188 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
189 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
190
191 /* Disable the infinite transfer mode */
192 ret = pci_read_config_byte(chip->pdev,
193 O2_SD_INF_MOD, &scratch);
194 if (ret)
195 return ret;
196 scratch |= 0x08;
197 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
198
199 /* Lock WP */
200 ret = pci_read_config_byte(chip->pdev,
201 O2_SD_LOCK_WP, &scratch);
202 if (ret)
203 return ret;
204 scratch |= 0x80;
205 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
206 break;
207 case PCI_DEVICE_ID_O2_SDS0:
208 case PCI_DEVICE_ID_O2_SDS1:
209 case PCI_DEVICE_ID_O2_FUJIN2:
210 /* UnLock WP */
211 ret = pci_read_config_byte(chip->pdev,
212 O2_SD_LOCK_WP, &scratch);
213 if (ret)
214 return ret;
215
216 scratch &= 0x7f;
217 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
218
219 /* Set timeout CLK */
220 ret = pci_read_config_dword(chip->pdev,
221 O2_SD_CLK_SETTING, &scratch_32);
222 if (ret)
223 return ret;
224
225 scratch_32 &= ~(0xFF00);
226 scratch_32 |= 0x07E0C800;
227 pci_write_config_dword(chip->pdev,
228 O2_SD_CLK_SETTING, scratch_32);
229
230 ret = pci_read_config_dword(chip->pdev,
231 O2_SD_CLKREQ, &scratch_32);
232 if (ret)
233 return ret;
234 scratch_32 |= 0x3;
235 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
236
237 ret = pci_read_config_dword(chip->pdev,
238 O2_SD_PLL_SETTING, &scratch_32);
239 if (ret)
240 return ret;
241
242 scratch_32 &= ~(0x1F3F070E);
243 scratch_32 |= 0x18270106;
244 pci_write_config_dword(chip->pdev,
245 O2_SD_PLL_SETTING, scratch_32);
246
247 /* Disable UHS1 funciton */
248 ret = pci_read_config_dword(chip->pdev,
249 O2_SD_CAP_REG2, &scratch_32);
250 if (ret)
251 return ret;
252 scratch_32 &= ~(0xE0);
253 pci_write_config_dword(chip->pdev,
254 O2_SD_CAP_REG2, scratch_32);
255
256 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
257 sdhci_pci_o2_fujin2_pci_init(chip);
258
259 /* Lock WP */
260 ret = pci_read_config_byte(chip->pdev,
261 O2_SD_LOCK_WP, &scratch);
262 if (ret)
263 return ret;
264 scratch |= 0x80;
265 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
266 break;
267 case PCI_DEVICE_ID_O2_SEABIRD0:
268 case PCI_DEVICE_ID_O2_SEABIRD1:
269 /* UnLock WP */
270 ret = pci_read_config_byte(chip->pdev,
271 O2_SD_LOCK_WP, &scratch);
272 if (ret)
273 return ret;
274
275 scratch &= 0x7f;
276 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
277
278 ret = pci_read_config_dword(chip->pdev,
279 O2_SD_FUNC_REG0, &scratch_32);
280
281 if ((scratch_32 & 0xff000000) == 0x01000000) {
282 scratch_32 &= 0x0000FFFF;
283 scratch_32 |= 0x1F340000;
284
285 pci_write_config_dword(chip->pdev,
286 O2_SD_PLL_SETTING, scratch_32);
287 } else {
288 scratch_32 &= 0x0000FFFF;
289 scratch_32 |= 0x2c280000;
290
291 pci_write_config_dword(chip->pdev,
292 O2_SD_PLL_SETTING, scratch_32);
293
294 ret = pci_read_config_dword(chip->pdev,
295 O2_SD_FUNC_REG4,
296 &scratch_32);
297 scratch_32 |= (1 << 22);
298 pci_write_config_dword(chip->pdev,
299 O2_SD_FUNC_REG4, scratch_32);
300 }
301
302 /* Lock WP */
303 ret = pci_read_config_byte(chip->pdev,
304 O2_SD_LOCK_WP, &scratch);
305 if (ret)
306 return ret;
307 scratch |= 0x80;
308 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
309 break;
310 }
311
312 return 0;
313}
314EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe);
315
316int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
317{
318 sdhci_pci_o2_probe(chip);
319 return 0;
320}
321EXPORT_SYMBOL_GPL(sdhci_pci_o2_resume);
1/*
2 * Copyright (C) 2013 BayHub Technology Ltd.
3 *
4 * Authors: Peter Guo <peter.guo@bayhubtech.com>
5 * Adam Lee <adam.lee@canonical.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/pci.h>
19
20#include "sdhci.h"
21#include "sdhci-pci.h"
22
23/*
24 * O2Micro device registers
25 */
26
27#define O2_SD_MISC_REG5 0x64
28#define O2_SD_LD0_CTRL 0x68
29#define O2_SD_DEV_CTRL 0x88
30#define O2_SD_LOCK_WP 0xD3
31#define O2_SD_TEST_REG 0xD4
32#define O2_SD_FUNC_REG0 0xDC
33#define O2_SD_MULTI_VCC3V 0xEE
34#define O2_SD_CLKREQ 0xEC
35#define O2_SD_CAPS 0xE0
36#define O2_SD_ADMA1 0xE2
37#define O2_SD_ADMA2 0xE7
38#define O2_SD_INF_MOD 0xF1
39#define O2_SD_MISC_CTRL4 0xFC
40#define O2_SD_TUNING_CTRL 0x300
41#define O2_SD_PLL_SETTING 0x304
42#define O2_SD_CLK_SETTING 0x328
43#define O2_SD_CAP_REG2 0x330
44#define O2_SD_CAP_REG0 0x334
45#define O2_SD_UHS1_CAP_SETTING 0x33C
46#define O2_SD_DELAY_CTRL 0x350
47#define O2_SD_UHS2_L1_CTRL 0x35C
48#define O2_SD_FUNC_REG3 0x3E0
49#define O2_SD_FUNC_REG4 0x3E4
50#define O2_SD_LED_ENABLE BIT(6)
51#define O2_SD_FREG0_LEDOFF BIT(13)
52#define O2_SD_FREG4_ENABLE_CLK_SET BIT(22)
53
54#define O2_SD_VENDOR_SETTING 0x110
55#define O2_SD_VENDOR_SETTING2 0x1C8
56
57static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
58{
59 u32 scratch_32;
60 pci_read_config_dword(chip->pdev,
61 O2_SD_PLL_SETTING, &scratch_32);
62
63 scratch_32 &= 0x0000FFFF;
64 scratch_32 |= value;
65
66 pci_write_config_dword(chip->pdev,
67 O2_SD_PLL_SETTING, scratch_32);
68}
69
70static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
71{
72 int ret;
73 u32 scratch_32;
74
75 /* Set led of SD host function enable */
76 ret = pci_read_config_dword(chip->pdev,
77 O2_SD_FUNC_REG0, &scratch_32);
78 if (ret)
79 return;
80
81 scratch_32 &= ~O2_SD_FREG0_LEDOFF;
82 pci_write_config_dword(chip->pdev,
83 O2_SD_FUNC_REG0, scratch_32);
84
85 ret = pci_read_config_dword(chip->pdev,
86 O2_SD_TEST_REG, &scratch_32);
87 if (ret)
88 return;
89
90 scratch_32 |= O2_SD_LED_ENABLE;
91 pci_write_config_dword(chip->pdev,
92 O2_SD_TEST_REG, scratch_32);
93
94}
95
96static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
97{
98 u32 scratch_32;
99 int ret;
100 /* Improve write performance for SD3.0 */
101 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
102 if (ret)
103 return;
104 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
105 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
106
107 /* Enable Link abnormal reset generating Reset */
108 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
109 if (ret)
110 return;
111 scratch_32 &= ~((1 << 19) | (1 << 11));
112 scratch_32 |= (1 << 10);
113 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
114
115 /* set card power over current protection */
116 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
117 if (ret)
118 return;
119 scratch_32 |= (1 << 4);
120 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
121
122 /* adjust the output delay for SD mode */
123 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
124
125 /* Set the output voltage setting of Aux 1.2v LDO */
126 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
127 if (ret)
128 return;
129 scratch_32 &= ~(3 << 12);
130 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
131
132 /* Set Max power supply capability of SD host */
133 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
134 if (ret)
135 return;
136 scratch_32 &= ~(0x01FE);
137 scratch_32 |= 0x00CC;
138 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
139 /* Set DLL Tuning Window */
140 ret = pci_read_config_dword(chip->pdev,
141 O2_SD_TUNING_CTRL, &scratch_32);
142 if (ret)
143 return;
144 scratch_32 &= ~(0x000000FF);
145 scratch_32 |= 0x00000066;
146 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
147
148 /* Set UHS2 T_EIDLE */
149 ret = pci_read_config_dword(chip->pdev,
150 O2_SD_UHS2_L1_CTRL, &scratch_32);
151 if (ret)
152 return;
153 scratch_32 &= ~(0x000000FC);
154 scratch_32 |= 0x00000084;
155 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
156
157 /* Set UHS2 Termination */
158 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
159 if (ret)
160 return;
161 scratch_32 &= ~((1 << 21) | (1 << 30));
162
163 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
164
165 /* Set L1 Entrance Timer */
166 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
167 if (ret)
168 return;
169 scratch_32 &= ~(0xf0000000);
170 scratch_32 |= 0x30000000;
171 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
172
173 ret = pci_read_config_dword(chip->pdev,
174 O2_SD_MISC_CTRL4, &scratch_32);
175 if (ret)
176 return;
177 scratch_32 &= ~(0x000f0000);
178 scratch_32 |= 0x00080000;
179 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
180}
181
182int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
183{
184 struct sdhci_pci_chip *chip;
185 struct sdhci_host *host;
186 u32 reg;
187
188 chip = slot->chip;
189 host = slot->host;
190 switch (chip->pdev->device) {
191 case PCI_DEVICE_ID_O2_SDS0:
192 case PCI_DEVICE_ID_O2_SEABIRD0:
193 case PCI_DEVICE_ID_O2_SEABIRD1:
194 case PCI_DEVICE_ID_O2_SDS1:
195 case PCI_DEVICE_ID_O2_FUJIN2:
196 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
197 if (reg & 0x1)
198 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
199
200 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
201 break;
202 /* set dll watch dog timer */
203 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
204 reg |= (1 << 12);
205 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
206
207 break;
208 default:
209 break;
210 }
211
212 return 0;
213}
214
215int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
216{
217 int ret;
218 u8 scratch;
219 u32 scratch_32;
220
221 switch (chip->pdev->device) {
222 case PCI_DEVICE_ID_O2_8220:
223 case PCI_DEVICE_ID_O2_8221:
224 case PCI_DEVICE_ID_O2_8320:
225 case PCI_DEVICE_ID_O2_8321:
226 /* This extra setup is required due to broken ADMA. */
227 ret = pci_read_config_byte(chip->pdev,
228 O2_SD_LOCK_WP, &scratch);
229 if (ret)
230 return ret;
231 scratch &= 0x7f;
232 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
233
234 /* Set Multi 3 to VCC3V# */
235 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
236
237 /* Disable CLK_REQ# support after media DET */
238 ret = pci_read_config_byte(chip->pdev,
239 O2_SD_CLKREQ, &scratch);
240 if (ret)
241 return ret;
242 scratch |= 0x20;
243 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
244
245 /* Choose capabilities, enable SDMA. We have to write 0x01
246 * to the capabilities register first to unlock it.
247 */
248 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
249 if (ret)
250 return ret;
251 scratch |= 0x01;
252 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
253 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
254
255 /* Disable ADMA1/2 */
256 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
257 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
258
259 /* Disable the infinite transfer mode */
260 ret = pci_read_config_byte(chip->pdev,
261 O2_SD_INF_MOD, &scratch);
262 if (ret)
263 return ret;
264 scratch |= 0x08;
265 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
266
267 /* Lock WP */
268 ret = pci_read_config_byte(chip->pdev,
269 O2_SD_LOCK_WP, &scratch);
270 if (ret)
271 return ret;
272 scratch |= 0x80;
273 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
274 break;
275 case PCI_DEVICE_ID_O2_SDS0:
276 case PCI_DEVICE_ID_O2_SDS1:
277 case PCI_DEVICE_ID_O2_FUJIN2:
278 /* UnLock WP */
279 ret = pci_read_config_byte(chip->pdev,
280 O2_SD_LOCK_WP, &scratch);
281 if (ret)
282 return ret;
283
284 scratch &= 0x7f;
285 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
286
287 /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
288 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
289 ret = pci_read_config_dword(chip->pdev,
290 O2_SD_FUNC_REG0,
291 &scratch_32);
292 scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
293
294 /* Check Whether subId is 0x11 or 0x12 */
295 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
296 scratch_32 = 0x2c280000;
297
298 /* Set Base Clock to 208MZ */
299 o2_pci_set_baseclk(chip, scratch_32);
300 ret = pci_read_config_dword(chip->pdev,
301 O2_SD_FUNC_REG4,
302 &scratch_32);
303
304 /* Enable Base Clk setting change */
305 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
306 pci_write_config_dword(chip->pdev,
307 O2_SD_FUNC_REG4,
308 scratch_32);
309
310 /* Set Tuning Window to 4 */
311 pci_write_config_byte(chip->pdev,
312 O2_SD_TUNING_CTRL, 0x44);
313
314 break;
315 }
316 }
317
318 /* Enable 8520 led function */
319 o2_pci_led_enable(chip);
320
321 /* Set timeout CLK */
322 ret = pci_read_config_dword(chip->pdev,
323 O2_SD_CLK_SETTING, &scratch_32);
324 if (ret)
325 return ret;
326
327 scratch_32 &= ~(0xFF00);
328 scratch_32 |= 0x07E0C800;
329 pci_write_config_dword(chip->pdev,
330 O2_SD_CLK_SETTING, scratch_32);
331
332 ret = pci_read_config_dword(chip->pdev,
333 O2_SD_CLKREQ, &scratch_32);
334 if (ret)
335 return ret;
336 scratch_32 |= 0x3;
337 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
338
339 ret = pci_read_config_dword(chip->pdev,
340 O2_SD_PLL_SETTING, &scratch_32);
341 if (ret)
342 return ret;
343
344 scratch_32 &= ~(0x1F3F070E);
345 scratch_32 |= 0x18270106;
346 pci_write_config_dword(chip->pdev,
347 O2_SD_PLL_SETTING, scratch_32);
348
349 /* Disable UHS1 funciton */
350 ret = pci_read_config_dword(chip->pdev,
351 O2_SD_CAP_REG2, &scratch_32);
352 if (ret)
353 return ret;
354 scratch_32 &= ~(0xE0);
355 pci_write_config_dword(chip->pdev,
356 O2_SD_CAP_REG2, scratch_32);
357
358 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
359 sdhci_pci_o2_fujin2_pci_init(chip);
360
361 /* Lock WP */
362 ret = pci_read_config_byte(chip->pdev,
363 O2_SD_LOCK_WP, &scratch);
364 if (ret)
365 return ret;
366 scratch |= 0x80;
367 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
368 break;
369 case PCI_DEVICE_ID_O2_SEABIRD0:
370 case PCI_DEVICE_ID_O2_SEABIRD1:
371 /* UnLock WP */
372 ret = pci_read_config_byte(chip->pdev,
373 O2_SD_LOCK_WP, &scratch);
374 if (ret)
375 return ret;
376
377 scratch &= 0x7f;
378 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
379
380 ret = pci_read_config_dword(chip->pdev,
381 O2_SD_PLL_SETTING, &scratch_32);
382
383 if ((scratch_32 & 0xff000000) == 0x01000000) {
384 scratch_32 &= 0x0000FFFF;
385 scratch_32 |= 0x1F340000;
386
387 pci_write_config_dword(chip->pdev,
388 O2_SD_PLL_SETTING, scratch_32);
389 } else {
390 scratch_32 &= 0x0000FFFF;
391 scratch_32 |= 0x2c280000;
392
393 pci_write_config_dword(chip->pdev,
394 O2_SD_PLL_SETTING, scratch_32);
395
396 ret = pci_read_config_dword(chip->pdev,
397 O2_SD_FUNC_REG4,
398 &scratch_32);
399 scratch_32 |= (1 << 22);
400 pci_write_config_dword(chip->pdev,
401 O2_SD_FUNC_REG4, scratch_32);
402 }
403
404 /* Set Tuning Windows to 5 */
405 pci_write_config_byte(chip->pdev,
406 O2_SD_TUNING_CTRL, 0x55);
407 /* Lock WP */
408 ret = pci_read_config_byte(chip->pdev,
409 O2_SD_LOCK_WP, &scratch);
410 if (ret)
411 return ret;
412 scratch |= 0x80;
413 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
414 break;
415 }
416
417 return 0;
418}
419
420#ifdef CONFIG_PM_SLEEP
421int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
422{
423 sdhci_pci_o2_probe(chip);
424 return sdhci_pci_resume_host(chip);
425}
426#endif