1/*
  2 * SH7264 Setup
  3 *
  4 * Copyright (C) 2012  Renesas Electronics Europe Ltd
  5 *
  6 * This file is subject to the terms and conditions of the GNU General Public
  7 * License.  See the file "COPYING" in the main directory of this archive
  8 * for more details.
  9 */
 10#include <linux/platform_device.h>
 11#include <linux/init.h>
 12#include <linux/serial.h>
 13#include <linux/serial_sci.h>
 14#include <linux/usb/r8a66597.h>
 15#include <linux/sh_timer.h>
 16#include <linux/io.h>
 17
 18enum {
 19	UNUSED = 0,
 20
 21	/* interrupt sources */
 22	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 23	PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
 24
 25	DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
 26	DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
 27	USB, VDC3, CMT0, CMT1, BSC, WDT,
 28	MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
 29	MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
 30	PWMT1, PWMT2, ADC_ADI,
 31	SSIF0, SSII1, SSII2, SSII3,
 32	RSPDIF,
 33	IIC30, IIC31, IIC32, IIC33,
 34	SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
 35	SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
 36	SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
 37	SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
 38	SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
 39	SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
 40	SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
 41	SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
 42	SIO_FIFO, RSPIC0, RSPIC1,
 43	RCAN0, RCAN1, IEBC, CD_ROMD,
 44	NFMC, SDHI, RTC,
 45	SRCC0, SRCC1, DCOMU, OFFI, IFEI,
 46
 47	/* interrupt groups */
 48	PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
 49};
 50
 51static struct intc_vect vectors[] __initdata = {
 52	INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
 53	INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
 54	INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
 55	INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
 56
 57	INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
 58	INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
 59	INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
 60	INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
 61
 62	INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
 63	INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
 64	INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
 65	INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
 66	INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
 67	INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
 68	INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
 69	INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
 70	INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
 71	INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
 72	INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
 73	INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
 74	INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
 75	INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
 76	INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
 77	INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
 78
 79	INTC_IRQ(USB, 170),
 80	INTC_IRQ(VDC3, 171), INTC_IRQ(VDC3, 172),
 81	INTC_IRQ(VDC3, 173), INTC_IRQ(VDC3, 174),
 82	INTC_IRQ(CMT0, 175), INTC_IRQ(CMT1, 176),
 83	INTC_IRQ(BSC, 177), INTC_IRQ(WDT, 178),
 84
 85	INTC_IRQ(MTU0_ABCD, 179), INTC_IRQ(MTU0_ABCD, 180),
 86	INTC_IRQ(MTU0_ABCD, 181), INTC_IRQ(MTU0_ABCD, 182),
 87	INTC_IRQ(MTU0_VEF, 183),
 88	INTC_IRQ(MTU0_VEF, 184), INTC_IRQ(MTU0_VEF, 185),
 89	INTC_IRQ(MTU1_AB, 186), INTC_IRQ(MTU1_AB, 187),
 90	INTC_IRQ(MTU1_VU, 188), INTC_IRQ(MTU1_VU, 189),
 91	INTC_IRQ(MTU2_AB, 190), INTC_IRQ(MTU2_AB, 191),
 92	INTC_IRQ(MTU2_VU, 192), INTC_IRQ(MTU2_VU, 193),
 93	INTC_IRQ(MTU3_ABCD, 194), INTC_IRQ(MTU3_ABCD, 195),
 94	INTC_IRQ(MTU3_ABCD, 196), INTC_IRQ(MTU3_ABCD, 197),
 95	INTC_IRQ(MTU3_TCI3V, 198),
 96	INTC_IRQ(MTU4_ABCD, 199), INTC_IRQ(MTU4_ABCD, 200),
 97	INTC_IRQ(MTU4_ABCD, 201), INTC_IRQ(MTU4_ABCD, 202),
 98	INTC_IRQ(MTU4_TCI4V, 203),
 99
100	INTC_IRQ(PWMT1, 204), INTC_IRQ(PWMT2, 205),
101
102	INTC_IRQ(ADC_ADI, 206),
103
104	INTC_IRQ(SSIF0, 207), INTC_IRQ(SSIF0, 208),
105	INTC_IRQ(SSIF0, 209),
106	INTC_IRQ(SSII1, 210), INTC_IRQ(SSII1, 211),
107	INTC_IRQ(SSII2, 212), INTC_IRQ(SSII2, 213),
108	INTC_IRQ(SSII3, 214), INTC_IRQ(SSII3, 215),
109
110	INTC_IRQ(RSPDIF, 216),
111
112	INTC_IRQ(IIC30, 217), INTC_IRQ(IIC30, 218),
113	INTC_IRQ(IIC30, 219), INTC_IRQ(IIC30, 220),
114	INTC_IRQ(IIC30, 221),
115	INTC_IRQ(IIC31, 222), INTC_IRQ(IIC31, 223),
116	INTC_IRQ(IIC31, 224), INTC_IRQ(IIC31, 225),
117	INTC_IRQ(IIC31, 226),
118	INTC_IRQ(IIC32, 227), INTC_IRQ(IIC32, 228),
119	INTC_IRQ(IIC32, 229), INTC_IRQ(IIC32, 230),
120	INTC_IRQ(IIC32, 231),
121
122	INTC_IRQ(SCIF0_BRI, 232), INTC_IRQ(SCIF0_ERI, 233),
123	INTC_IRQ(SCIF0_RXI, 234), INTC_IRQ(SCIF0_TXI, 235),
124	INTC_IRQ(SCIF1_BRI, 236), INTC_IRQ(SCIF1_ERI, 237),
125	INTC_IRQ(SCIF1_RXI, 238), INTC_IRQ(SCIF1_TXI, 239),
126	INTC_IRQ(SCIF2_BRI, 240), INTC_IRQ(SCIF2_ERI, 241),
127	INTC_IRQ(SCIF2_RXI, 242), INTC_IRQ(SCIF2_TXI, 243),
128	INTC_IRQ(SCIF3_BRI, 244), INTC_IRQ(SCIF3_ERI, 245),
129	INTC_IRQ(SCIF3_RXI, 246), INTC_IRQ(SCIF3_TXI, 247),
130	INTC_IRQ(SCIF4_BRI, 248), INTC_IRQ(SCIF4_ERI, 249),
131	INTC_IRQ(SCIF4_RXI, 250), INTC_IRQ(SCIF4_TXI, 251),
132	INTC_IRQ(SCIF5_BRI, 252), INTC_IRQ(SCIF5_ERI, 253),
133	INTC_IRQ(SCIF5_RXI, 254), INTC_IRQ(SCIF5_TXI, 255),
134	INTC_IRQ(SCIF6_BRI, 256), INTC_IRQ(SCIF6_ERI, 257),
135	INTC_IRQ(SCIF6_RXI, 258), INTC_IRQ(SCIF6_TXI, 259),
136	INTC_IRQ(SCIF7_BRI, 260), INTC_IRQ(SCIF7_ERI, 261),
137	INTC_IRQ(SCIF7_RXI, 262), INTC_IRQ(SCIF7_TXI, 263),
138
139	INTC_IRQ(SIO_FIFO, 264),
140
141	INTC_IRQ(RSPIC0, 265), INTC_IRQ(RSPIC0, 266),
142	INTC_IRQ(RSPIC0, 267),
143	INTC_IRQ(RSPIC1, 268), INTC_IRQ(RSPIC1, 269),
144	INTC_IRQ(RSPIC1, 270),
145
146	INTC_IRQ(RCAN0, 271), INTC_IRQ(RCAN0, 272),
147	INTC_IRQ(RCAN0, 273), INTC_IRQ(RCAN0, 274),
148	INTC_IRQ(RCAN0, 275),
149	INTC_IRQ(RCAN1, 276), INTC_IRQ(RCAN1, 277),
150	INTC_IRQ(RCAN1, 278), INTC_IRQ(RCAN1, 279),
151	INTC_IRQ(RCAN1, 280),
152
153	INTC_IRQ(IEBC, 281),
154
155	INTC_IRQ(CD_ROMD, 282), INTC_IRQ(CD_ROMD, 283),
156	INTC_IRQ(CD_ROMD, 284), INTC_IRQ(CD_ROMD, 285),
157	INTC_IRQ(CD_ROMD, 286), INTC_IRQ(CD_ROMD, 287),
158
159	INTC_IRQ(NFMC, 288), INTC_IRQ(NFMC, 289),
160	INTC_IRQ(NFMC, 290), INTC_IRQ(NFMC, 291),
161
162	INTC_IRQ(SDHI, 292), INTC_IRQ(SDHI, 293),
163	INTC_IRQ(SDHI, 294),
164
165	INTC_IRQ(RTC, 296), INTC_IRQ(RTC, 297),
166	INTC_IRQ(RTC, 298),
167
168	INTC_IRQ(SRCC0, 299), INTC_IRQ(SRCC0, 300),
169	INTC_IRQ(SRCC0, 301), INTC_IRQ(SRCC0, 302),
170	INTC_IRQ(SRCC0, 303),
171	INTC_IRQ(SRCC1, 304), INTC_IRQ(SRCC1, 305),
172	INTC_IRQ(SRCC1, 306), INTC_IRQ(SRCC1, 307),
173	INTC_IRQ(SRCC1, 308),
174
175	INTC_IRQ(DCOMU, 310), INTC_IRQ(DCOMU, 311),
176	INTC_IRQ(DCOMU, 312),
177};
178
179static struct intc_group groups[] __initdata = {
180	INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
181		   PINT4, PINT5, PINT6, PINT7),
182	INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
183	INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
184	INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
185	INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
186	INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
187	INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
188	INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
189	INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
190};
191
192static struct intc_prio_reg prio_registers[] __initdata = {
193	{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
194	{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
195	{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
196	{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0,  DMAC1,  DMAC2,  DMAC3 } },
197	{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4,  DMAC5,  DMAC6,  DMAC7 } },
198	{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8,  DMAC9,
199					      DMAC10, DMAC11 } },
200	{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
201					      DMAC14, DMAC15 } },
202	{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC3, CMT0, CMT1 } },
203	{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
204	{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU1_AB, MTU1_VU,
205					      MTU2_AB, MTU2_VU } },
206	{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU3_ABCD, MTU3_TCI3V,
207					      MTU4_ABCD, MTU4_TCI4V } },
208	{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { PWMT1, PWMT2, ADC_ADI, 0 } },
209	{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSIF0, SSII1, SSII2, SSII3 } },
210	{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { RSPDIF, IIC30, IIC31, IIC32 } },
211	{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
212	{ 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
213	{ 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { SIO_FIFO, 0, RSPIC0, RSPIC1, } },
214	{ 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { RCAN0, RCAN1, IEBC, CD_ROMD } },
215	{ 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { NFMC, SDHI, RTC, 0 } },
216	{ 0xfffe0c20, 0, 16, 4, /* IPR22 */ { SRCC0, SRCC1, 0, DCOMU } },
217};
218
219static struct intc_mask_reg mask_registers[] __initdata = {
220	{ 0xfffe0808, 0, 16, /* PINTER */
221	  { 0, 0, 0, 0, 0, 0, 0, 0,
222	    PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
223};
224
225static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups,
226			 mask_registers, prio_registers, NULL);
227
228static struct plat_sci_port scif0_platform_data = {
229	.flags		= UPF_BOOT_AUTOCONF,
230	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
231			  SCSCR_REIE | SCSCR_TOIE,
232	.type		= PORT_SCIF,
233	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
234};
235
236static struct resource scif0_resources[] = {
237	DEFINE_RES_MEM(0xfffe8000, 0x100),
238	DEFINE_RES_IRQ(233),
239	DEFINE_RES_IRQ(234),
240	DEFINE_RES_IRQ(235),
241	DEFINE_RES_IRQ(232),
242};
243
244static struct platform_device scif0_device = {
245	.name		= "sh-sci",
246	.id		= 0,
247	.resource	= scif0_resources,
248	.num_resources	= ARRAY_SIZE(scif0_resources),
249	.dev		= {
250		.platform_data	= &scif0_platform_data,
251	},
252};
253
254static struct plat_sci_port scif1_platform_data = {
255	.flags		= UPF_BOOT_AUTOCONF,
256	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
257			  SCSCR_REIE | SCSCR_TOIE,
258	.type		= PORT_SCIF,
259	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
260};
261
262static struct resource scif1_resources[] = {
263	DEFINE_RES_MEM(0xfffe8800, 0x100),
264	DEFINE_RES_IRQ(237),
265	DEFINE_RES_IRQ(238),
266	DEFINE_RES_IRQ(239),
267	DEFINE_RES_IRQ(236),
268};
269
270static struct platform_device scif1_device = {
271	.name		= "sh-sci",
272	.id		= 1,
273	.resource	= scif1_resources,
274	.num_resources	= ARRAY_SIZE(scif1_resources),
275	.dev		= {
276		.platform_data	= &scif1_platform_data,
277	},
278};
279
280static struct plat_sci_port scif2_platform_data = {
281	.flags		= UPF_BOOT_AUTOCONF,
282	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
283			  SCSCR_REIE | SCSCR_TOIE,
284	.type		= PORT_SCIF,
285	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
286};
287
288static struct resource scif2_resources[] = {
289	DEFINE_RES_MEM(0xfffe9000, 0x100),
290	DEFINE_RES_IRQ(241),
291	DEFINE_RES_IRQ(242),
292	DEFINE_RES_IRQ(243),
293	DEFINE_RES_IRQ(240),
294};
295
296static struct platform_device scif2_device = {
297	.name		= "sh-sci",
298	.id		= 2,
299	.resource	= scif2_resources,
300	.num_resources	= ARRAY_SIZE(scif2_resources),
301	.dev		= {
302		.platform_data	= &scif2_platform_data,
303	},
304};
305
306static struct plat_sci_port scif3_platform_data = {
307	.flags		= UPF_BOOT_AUTOCONF,
308	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
309			  SCSCR_REIE | SCSCR_TOIE,
310	.type		= PORT_SCIF,
311	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
312};
313
314static struct resource scif3_resources[] = {
315	DEFINE_RES_MEM(0xfffe9800, 0x100),
316	DEFINE_RES_IRQ(245),
317	DEFINE_RES_IRQ(246),
318	DEFINE_RES_IRQ(247),
319	DEFINE_RES_IRQ(244),
320};
321
322static struct platform_device scif3_device = {
323	.name		= "sh-sci",
324	.id		= 3,
325	.resource	= scif3_resources,
326	.num_resources	= ARRAY_SIZE(scif3_resources),
327	.dev		= {
328		.platform_data	= &scif3_platform_data,
329	},
330};
331
332static struct plat_sci_port scif4_platform_data = {
333	.flags		= UPF_BOOT_AUTOCONF,
334	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
335			  SCSCR_REIE | SCSCR_TOIE,
336	.type		= PORT_SCIF,
337	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
338};
339
340static struct resource scif4_resources[] = {
341	DEFINE_RES_MEM(0xfffea000, 0x100),
342	DEFINE_RES_IRQ(249),
343	DEFINE_RES_IRQ(250),
344	DEFINE_RES_IRQ(251),
345	DEFINE_RES_IRQ(248),
346};
347
348static struct platform_device scif4_device = {
349	.name		= "sh-sci",
350	.id		= 4,
351	.resource	= scif4_resources,
352	.num_resources	= ARRAY_SIZE(scif4_resources),
353	.dev		= {
354		.platform_data	= &scif4_platform_data,
355	},
356};
357
358static struct plat_sci_port scif5_platform_data = {
359	.flags		= UPF_BOOT_AUTOCONF,
360	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
361			  SCSCR_REIE | SCSCR_TOIE,
362	.type		= PORT_SCIF,
363	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
364};
365
366static struct resource scif5_resources[] = {
367	DEFINE_RES_MEM(0xfffea800, 0x100),
368	DEFINE_RES_IRQ(253),
369	DEFINE_RES_IRQ(254),
370	DEFINE_RES_IRQ(255),
371	DEFINE_RES_IRQ(252),
372};
373
374static struct platform_device scif5_device = {
375	.name		= "sh-sci",
376	.id		= 5,
377	.resource	= scif5_resources,
378	.num_resources	= ARRAY_SIZE(scif5_resources),
379	.dev		= {
380		.platform_data	= &scif5_platform_data,
381	},
382};
383
384static struct plat_sci_port scif6_platform_data = {
385	.flags		= UPF_BOOT_AUTOCONF,
386	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
387			  SCSCR_REIE | SCSCR_TOIE,
388	.type		= PORT_SCIF,
389	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
390};
391
392static struct resource scif6_resources[] = {
393	DEFINE_RES_MEM(0xfffeb000, 0x100),
394	DEFINE_RES_IRQ(257),
395	DEFINE_RES_IRQ(258),
396	DEFINE_RES_IRQ(259),
397	DEFINE_RES_IRQ(256),
398};
399
400static struct platform_device scif6_device = {
401	.name		= "sh-sci",
402	.id		= 6,
403	.resource	= scif6_resources,
404	.num_resources	= ARRAY_SIZE(scif6_resources),
405	.dev		= {
406		.platform_data	= &scif6_platform_data,
407	},
408};
409
410static struct plat_sci_port scif7_platform_data = {
411	.flags		= UPF_BOOT_AUTOCONF,
412	.scscr		= SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
413			  SCSCR_REIE | SCSCR_TOIE,
414	.type		= PORT_SCIF,
415	.regtype	= SCIx_SH2_SCIF_FIFODATA_REGTYPE,
416};
417
418static struct resource scif7_resources[] = {
419	DEFINE_RES_MEM(0xfffeb800, 0x100),
420	DEFINE_RES_IRQ(261),
421	DEFINE_RES_IRQ(262),
422	DEFINE_RES_IRQ(263),
423	DEFINE_RES_IRQ(260),
424};
425
426static struct platform_device scif7_device = {
427	.name		= "sh-sci",
428	.id		= 7,
429	.resource	= scif7_resources,
430	.num_resources	= ARRAY_SIZE(scif7_resources),
431	.dev		= {
432		.platform_data	= &scif7_platform_data,
433	},
434};
435
436static struct sh_timer_config cmt0_platform_data = {
437	.channel_offset = 0x02,
438	.timer_bit = 0,
439	.clockevent_rating = 125,
440	.clocksource_rating = 0, /* disabled due to code generation issues */
441};
442
443static struct resource cmt0_resources[] = {
444	[0] = {
445		.name	= "CMT0",
446		.start	= 0xfffec002,
447		.end	= 0xfffec007,
448		.flags	= IORESOURCE_MEM,
449	},
450	[1] = {
451		.start	= 175,
452		.flags	= IORESOURCE_IRQ,
453	},
454};
455
456static struct platform_device cmt0_device = {
457	.name		= "sh_cmt",
458	.id		= 0,
459	.dev = {
460		.platform_data	= &cmt0_platform_data,
461	},
462	.resource	= cmt0_resources,
463	.num_resources	= ARRAY_SIZE(cmt0_resources),
464};
465
466static struct sh_timer_config cmt1_platform_data = {
467	.name = "CMT1",
468	.channel_offset = 0x08,
469	.timer_bit = 1,
470	.clockevent_rating = 125,
471	.clocksource_rating = 0, /* disabled due to code generation issues */
472};
473
474static struct resource cmt1_resources[] = {
475	[0] = {
476		.name	= "CMT1",
477		.start	= 0xfffec008,
478		.end	= 0xfffec00d,
479		.flags	= IORESOURCE_MEM,
480	},
481	[1] = {
482		.start	= 176,
483		.flags	= IORESOURCE_IRQ,
484	},
485};
486
487static struct platform_device cmt1_device = {
488	.name		= "sh_cmt",
489	.id		= 1,
490	.dev = {
491		.platform_data	= &cmt1_platform_data,
492	},
493	.resource	= cmt1_resources,
494	.num_resources	= ARRAY_SIZE(cmt1_resources),
495};
496
497static struct sh_timer_config mtu2_0_platform_data = {
498	.name = "MTU2_0",
499	.channel_offset = -0x80,
500	.timer_bit = 0,
501	.clockevent_rating = 200,
502};
503
504static struct resource mtu2_0_resources[] = {
505	[0] = {
506		.name	= "MTU2_0",
507		.start	= 0xfffe4300,
508		.end	= 0xfffe4326,
509		.flags	= IORESOURCE_MEM,
510	},
511	[1] = {
512		.start	= 179,
513		.flags	= IORESOURCE_IRQ,
514	},
515};
516
517static struct platform_device mtu2_0_device = {
518	.name		= "sh_mtu2",
519	.id		= 0,
520	.dev = {
521		.platform_data	= &mtu2_0_platform_data,
522	},
523	.resource	= mtu2_0_resources,
524	.num_resources	= ARRAY_SIZE(mtu2_0_resources),
525};
526
527static struct sh_timer_config mtu2_1_platform_data = {
528	.name = "MTU2_1",
529	.channel_offset = -0x100,
530	.timer_bit = 1,
531	.clockevent_rating = 200,
532};
533
534static struct resource mtu2_1_resources[] = {
535	[0] = {
536		.name	= "MTU2_1",
537		.start	= 0xfffe4380,
538		.end	= 0xfffe4390,
539		.flags	= IORESOURCE_MEM,
540	},
541	[1] = {
542		.start	= 186,
543		.flags	= IORESOURCE_IRQ,
544	},
545};
546
547static struct platform_device mtu2_1_device = {
548	.name		= "sh_mtu2",
549	.id		= 1,
550	.dev = {
551		.platform_data	= &mtu2_1_platform_data,
552	},
553	.resource	= mtu2_1_resources,
554	.num_resources	= ARRAY_SIZE(mtu2_1_resources),
555};
556
557static struct resource rtc_resources[] = {
558	[0] = {
559		.start	= 0xfffe6000,
560		.end	= 0xfffe6000 + 0x30 - 1,
561		.flags	= IORESOURCE_IO,
562	},
563	[1] = {
564		/* Shared Period/Carry/Alarm IRQ */
565		.start	= 296,
566		.flags	= IORESOURCE_IRQ,
567	},
568};
569
570static struct platform_device rtc_device = {
571	.name		= "sh-rtc",
572	.id		= -1,
573	.num_resources	= ARRAY_SIZE(rtc_resources),
574	.resource	= rtc_resources,
575};
576
577/* USB Host */
578static void usb_port_power(int port, int power)
579{
580	__raw_writew(0x200 , 0xffffc0c2) ; /* Initialise UACS25 */
581}
582
583static struct r8a66597_platdata r8a66597_data = {
584	.on_chip = 1,
585	.endian = 1,
586	.port_power = usb_port_power,
587};
588
589static struct resource r8a66597_usb_host_resources[] = {
590	[0] = {
591		.start	= 0xffffc000,
592		.end	= 0xffffc0e4,
593		.flags	= IORESOURCE_MEM,
594	},
595	[1] = {
596		.start	= 170,
597		.end	= 170,
598		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
599	},
600};
601
602static struct platform_device r8a66597_usb_host_device = {
603	.name		= "r8a66597_hcd",
604	.id		= 0,
605	.dev = {
606		.dma_mask		= NULL,         /*  not use dma */
607		.coherent_dma_mask	= 0xffffffff,
608		.platform_data		= &r8a66597_data,
609	},
610	.num_resources	= ARRAY_SIZE(r8a66597_usb_host_resources),
611	.resource	= r8a66597_usb_host_resources,
612};
613
614static struct platform_device *sh7264_devices[] __initdata = {
615	&scif0_device,
616	&scif1_device,
617	&scif2_device,
618	&scif3_device,
619	&scif4_device,
620	&scif5_device,
621	&scif6_device,
622	&scif7_device,
623	&cmt0_device,
624	&cmt1_device,
625	&mtu2_0_device,
626	&mtu2_1_device,
627	&rtc_device,
628	&r8a66597_usb_host_device,
629};
630
631static int __init sh7264_devices_setup(void)
632{
633	return platform_add_devices(sh7264_devices,
634				    ARRAY_SIZE(sh7264_devices));
635}
636arch_initcall(sh7264_devices_setup);
637
638void __init plat_irq_setup(void)
639{
640	register_intc_controller(&intc_desc);
641}
642
643static struct platform_device *sh7264_early_devices[] __initdata = {
644	&scif0_device,
645	&scif1_device,
646	&scif2_device,
647	&scif3_device,
648	&scif4_device,
649	&scif5_device,
650	&scif6_device,
651	&scif7_device,
652	&cmt0_device,
653	&cmt1_device,
654	&mtu2_0_device,
655	&mtu2_1_device,
656};
657
658void __init plat_early_device_setup(void)
659{
660	early_platform_add_devices(sh7264_early_devices,
661				   ARRAY_SIZE(sh7264_early_devices));
662}