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1#ifndef _ASM_IA64_IO_H
2#define _ASM_IA64_IO_H
3
4/*
5 * This file contains the definitions for the emulated IO instructions
6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
8 * versions of the single-IO instructions (inb_p/inw_p/..).
9 *
10 * This file is not meant to be obfuscating: it's just complicated to
11 * (a) handle it all in a way that makes gcc able to optimize it as
12 * well as possible and (b) trying to avoid writing the same thing
13 * over and over again with slight variations and possibly making a
14 * mistake somewhere.
15 *
16 * Copyright (C) 1998-2003 Hewlett-Packard Co
17 * David Mosberger-Tang <davidm@hpl.hp.com>
18 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
19 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
20 */
21
22#include <asm/unaligned.h>
23
24/* We don't use IO slowdowns on the ia64, but.. */
25#define __SLOW_DOWN_IO do { } while (0)
26#define SLOW_DOWN_IO do { } while (0)
27
28#define __IA64_UNCACHED_OFFSET RGN_BASE(RGN_UNCACHED)
29
30/*
31 * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
32 * large machines may have multiple other I/O spaces so we can't place any a priori limit
33 * on IO_SPACE_LIMIT. These additional spaces are described in ACPI.
34 */
35#define IO_SPACE_LIMIT 0xffffffffffffffffUL
36
37#define MAX_IO_SPACES_BITS 8
38#define MAX_IO_SPACES (1UL << MAX_IO_SPACES_BITS)
39#define IO_SPACE_BITS 24
40#define IO_SPACE_SIZE (1UL << IO_SPACE_BITS)
41
42#define IO_SPACE_NR(port) ((port) >> IO_SPACE_BITS)
43#define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS)
44#define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1))
45
46#define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | ((p) & 0xfff))
47
48struct io_space {
49 unsigned long mmio_base; /* base in MMIO space */
50 int sparse;
51};
52
53extern struct io_space io_space[];
54extern unsigned int num_io_spaces;
55
56# ifdef __KERNEL__
57
58/*
59 * All MMIO iomem cookies are in region 6; anything less is a PIO cookie:
60 * 0xCxxxxxxxxxxxxxxx MMIO cookie (return from ioremap)
61 * 0x000000001SPPPPPP PIO cookie (S=space number, P..P=port)
62 *
63 * ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch
64 * code that uses bare port numbers without the prerequisite pci_iomap().
65 */
66#define PIO_OFFSET (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS))
67#define PIO_MASK (PIO_OFFSET - 1)
68#define PIO_RESERVED __IA64_UNCACHED_OFFSET
69#define HAVE_ARCH_PIO_SIZE
70
71#include <asm/intrinsics.h>
72#include <asm/machvec.h>
73#include <asm/page.h>
74#include <asm-generic/iomap.h>
75
76/*
77 * Change virtual addresses to physical addresses and vv.
78 */
79static inline unsigned long
80virt_to_phys (volatile void *address)
81{
82 return (unsigned long) address - PAGE_OFFSET;
83}
84
85static inline void*
86phys_to_virt (unsigned long address)
87{
88 return (void *) (address + PAGE_OFFSET);
89}
90
91#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
92extern u64 kern_mem_attribute (unsigned long phys_addr, unsigned long size);
93extern int valid_phys_addr_range (phys_addr_t addr, size_t count); /* efi.c */
94extern int valid_mmap_phys_addr_range (unsigned long pfn, size_t count);
95
96/*
97 * The following two macros are deprecated and scheduled for removal.
98 * Please use the PCI-DMA interface defined in <asm/pci.h> instead.
99 */
100#define bus_to_virt phys_to_virt
101#define virt_to_bus virt_to_phys
102#define page_to_bus page_to_phys
103
104# endif /* KERNEL */
105
106/*
107 * Memory fence w/accept. This should never be used in code that is
108 * not IA-64 specific.
109 */
110#define __ia64_mf_a() ia64_mfa()
111
112/**
113 * ___ia64_mmiowb - I/O write barrier
114 *
115 * Ensure ordering of I/O space writes. This will make sure that writes
116 * following the barrier will arrive after all previous writes. For most
117 * ia64 platforms, this is a simple 'mf.a' instruction.
118 *
119 * See Documentation/DocBook/deviceiobook.tmpl for more information.
120 */
121static inline void ___ia64_mmiowb(void)
122{
123 ia64_mfa();
124}
125
126static inline void*
127__ia64_mk_io_addr (unsigned long port)
128{
129 struct io_space *space;
130 unsigned long offset;
131
132 space = &io_space[IO_SPACE_NR(port)];
133 port = IO_SPACE_PORT(port);
134 if (space->sparse)
135 offset = IO_SPACE_SPARSE_ENCODING(port);
136 else
137 offset = port;
138
139 return (void *) (space->mmio_base | offset);
140}
141
142#define __ia64_inb ___ia64_inb
143#define __ia64_inw ___ia64_inw
144#define __ia64_inl ___ia64_inl
145#define __ia64_outb ___ia64_outb
146#define __ia64_outw ___ia64_outw
147#define __ia64_outl ___ia64_outl
148#define __ia64_readb ___ia64_readb
149#define __ia64_readw ___ia64_readw
150#define __ia64_readl ___ia64_readl
151#define __ia64_readq ___ia64_readq
152#define __ia64_readb_relaxed ___ia64_readb
153#define __ia64_readw_relaxed ___ia64_readw
154#define __ia64_readl_relaxed ___ia64_readl
155#define __ia64_readq_relaxed ___ia64_readq
156#define __ia64_writeb ___ia64_writeb
157#define __ia64_writew ___ia64_writew
158#define __ia64_writel ___ia64_writel
159#define __ia64_writeq ___ia64_writeq
160#define __ia64_mmiowb ___ia64_mmiowb
161
162/*
163 * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
164 * that the access has completed before executing other I/O accesses. Since we're doing
165 * the accesses through an uncachable (UC) translation, the CPU will execute them in
166 * program order. However, we still need to tell the compiler not to shuffle them around
167 * during optimization, which is why we use "volatile" pointers.
168 */
169
170static inline unsigned int
171___ia64_inb (unsigned long port)
172{
173 volatile unsigned char *addr = __ia64_mk_io_addr(port);
174 unsigned char ret;
175
176 ret = *addr;
177 __ia64_mf_a();
178 return ret;
179}
180
181static inline unsigned int
182___ia64_inw (unsigned long port)
183{
184 volatile unsigned short *addr = __ia64_mk_io_addr(port);
185 unsigned short ret;
186
187 ret = *addr;
188 __ia64_mf_a();
189 return ret;
190}
191
192static inline unsigned int
193___ia64_inl (unsigned long port)
194{
195 volatile unsigned int *addr = __ia64_mk_io_addr(port);
196 unsigned int ret;
197
198 ret = *addr;
199 __ia64_mf_a();
200 return ret;
201}
202
203static inline void
204___ia64_outb (unsigned char val, unsigned long port)
205{
206 volatile unsigned char *addr = __ia64_mk_io_addr(port);
207
208 *addr = val;
209 __ia64_mf_a();
210}
211
212static inline void
213___ia64_outw (unsigned short val, unsigned long port)
214{
215 volatile unsigned short *addr = __ia64_mk_io_addr(port);
216
217 *addr = val;
218 __ia64_mf_a();
219}
220
221static inline void
222___ia64_outl (unsigned int val, unsigned long port)
223{
224 volatile unsigned int *addr = __ia64_mk_io_addr(port);
225
226 *addr = val;
227 __ia64_mf_a();
228}
229
230static inline void
231__insb (unsigned long port, void *dst, unsigned long count)
232{
233 unsigned char *dp = dst;
234
235 while (count--)
236 *dp++ = platform_inb(port);
237}
238
239static inline void
240__insw (unsigned long port, void *dst, unsigned long count)
241{
242 unsigned short *dp = dst;
243
244 while (count--)
245 put_unaligned(platform_inw(port), dp++);
246}
247
248static inline void
249__insl (unsigned long port, void *dst, unsigned long count)
250{
251 unsigned int *dp = dst;
252
253 while (count--)
254 put_unaligned(platform_inl(port), dp++);
255}
256
257static inline void
258__outsb (unsigned long port, const void *src, unsigned long count)
259{
260 const unsigned char *sp = src;
261
262 while (count--)
263 platform_outb(*sp++, port);
264}
265
266static inline void
267__outsw (unsigned long port, const void *src, unsigned long count)
268{
269 const unsigned short *sp = src;
270
271 while (count--)
272 platform_outw(get_unaligned(sp++), port);
273}
274
275static inline void
276__outsl (unsigned long port, const void *src, unsigned long count)
277{
278 const unsigned int *sp = src;
279
280 while (count--)
281 platform_outl(get_unaligned(sp++), port);
282}
283
284/*
285 * Unfortunately, some platforms are broken and do not follow the IA-64 architecture
286 * specification regarding legacy I/O support. Thus, we have to make these operations
287 * platform dependent...
288 */
289#define __inb platform_inb
290#define __inw platform_inw
291#define __inl platform_inl
292#define __outb platform_outb
293#define __outw platform_outw
294#define __outl platform_outl
295#define __mmiowb platform_mmiowb
296
297#define inb(p) __inb(p)
298#define inw(p) __inw(p)
299#define inl(p) __inl(p)
300#define insb(p,d,c) __insb(p,d,c)
301#define insw(p,d,c) __insw(p,d,c)
302#define insl(p,d,c) __insl(p,d,c)
303#define outb(v,p) __outb(v,p)
304#define outw(v,p) __outw(v,p)
305#define outl(v,p) __outl(v,p)
306#define outsb(p,s,c) __outsb(p,s,c)
307#define outsw(p,s,c) __outsw(p,s,c)
308#define outsl(p,s,c) __outsl(p,s,c)
309#define mmiowb() __mmiowb()
310
311/*
312 * The address passed to these functions are ioremap()ped already.
313 *
314 * We need these to be machine vectors since some platforms don't provide
315 * DMA coherence via PIO reads (PCI drivers and the spec imply that this is
316 * a good idea). Writes are ok though for all existing ia64 platforms (and
317 * hopefully it'll stay that way).
318 */
319static inline unsigned char
320___ia64_readb (const volatile void __iomem *addr)
321{
322 return *(volatile unsigned char __force *)addr;
323}
324
325static inline unsigned short
326___ia64_readw (const volatile void __iomem *addr)
327{
328 return *(volatile unsigned short __force *)addr;
329}
330
331static inline unsigned int
332___ia64_readl (const volatile void __iomem *addr)
333{
334 return *(volatile unsigned int __force *) addr;
335}
336
337static inline unsigned long
338___ia64_readq (const volatile void __iomem *addr)
339{
340 return *(volatile unsigned long __force *) addr;
341}
342
343static inline void
344__writeb (unsigned char val, volatile void __iomem *addr)
345{
346 *(volatile unsigned char __force *) addr = val;
347}
348
349static inline void
350__writew (unsigned short val, volatile void __iomem *addr)
351{
352 *(volatile unsigned short __force *) addr = val;
353}
354
355static inline void
356__writel (unsigned int val, volatile void __iomem *addr)
357{
358 *(volatile unsigned int __force *) addr = val;
359}
360
361static inline void
362__writeq (unsigned long val, volatile void __iomem *addr)
363{
364 *(volatile unsigned long __force *) addr = val;
365}
366
367#define __readb platform_readb
368#define __readw platform_readw
369#define __readl platform_readl
370#define __readq platform_readq
371#define __readb_relaxed platform_readb_relaxed
372#define __readw_relaxed platform_readw_relaxed
373#define __readl_relaxed platform_readl_relaxed
374#define __readq_relaxed platform_readq_relaxed
375
376#define readb(a) __readb((a))
377#define readw(a) __readw((a))
378#define readl(a) __readl((a))
379#define readq(a) __readq((a))
380#define readb_relaxed(a) __readb_relaxed((a))
381#define readw_relaxed(a) __readw_relaxed((a))
382#define readl_relaxed(a) __readl_relaxed((a))
383#define readq_relaxed(a) __readq_relaxed((a))
384#define __raw_readb readb
385#define __raw_readw readw
386#define __raw_readl readl
387#define __raw_readq readq
388#define __raw_readb_relaxed readb_relaxed
389#define __raw_readw_relaxed readw_relaxed
390#define __raw_readl_relaxed readl_relaxed
391#define __raw_readq_relaxed readq_relaxed
392#define writeb(v,a) __writeb((v), (a))
393#define writew(v,a) __writew((v), (a))
394#define writel(v,a) __writel((v), (a))
395#define writeq(v,a) __writeq((v), (a))
396#define __raw_writeb writeb
397#define __raw_writew writew
398#define __raw_writel writel
399#define __raw_writeq writeq
400
401#ifndef inb_p
402# define inb_p inb
403#endif
404#ifndef inw_p
405# define inw_p inw
406#endif
407#ifndef inl_p
408# define inl_p inl
409#endif
410
411#ifndef outb_p
412# define outb_p outb
413#endif
414#ifndef outw_p
415# define outw_p outw
416#endif
417#ifndef outl_p
418# define outl_p outl
419#endif
420
421# ifdef __KERNEL__
422
423extern void __iomem * ioremap(unsigned long offset, unsigned long size);
424extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size);
425extern void iounmap (volatile void __iomem *addr);
426extern void __iomem * early_ioremap (unsigned long phys_addr, unsigned long size);
427#define early_memremap(phys_addr, size) early_ioremap(phys_addr, size)
428extern void early_iounmap (volatile void __iomem *addr, unsigned long size);
429static inline void __iomem * ioremap_cache (unsigned long phys_addr, unsigned long size)
430{
431 return ioremap(phys_addr, size);
432}
433
434
435/*
436 * String version of IO memory access ops:
437 */
438extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n);
439extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n);
440extern void memset_io(volatile void __iomem *s, int c, long n);
441
442# endif /* __KERNEL__ */
443
444#endif /* _ASM_IA64_IO_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_IA64_IO_H
3#define _ASM_IA64_IO_H
4
5/*
6 * This file contains the definitions for the emulated IO instructions
7 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
8 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
9 * versions of the single-IO instructions (inb_p/inw_p/..).
10 *
11 * This file is not meant to be obfuscating: it's just complicated to
12 * (a) handle it all in a way that makes gcc able to optimize it as
13 * well as possible and (b) trying to avoid writing the same thing
14 * over and over again with slight variations and possibly making a
15 * mistake somewhere.
16 *
17 * Copyright (C) 1998-2003 Hewlett-Packard Co
18 * David Mosberger-Tang <davidm@hpl.hp.com>
19 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
20 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
21 */
22
23#include <asm/unaligned.h>
24#include <asm/early_ioremap.h>
25
26/* We don't use IO slowdowns on the ia64, but.. */
27#define __SLOW_DOWN_IO do { } while (0)
28#define SLOW_DOWN_IO do { } while (0)
29
30#define __IA64_UNCACHED_OFFSET RGN_BASE(RGN_UNCACHED)
31
32/*
33 * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
34 * large machines may have multiple other I/O spaces so we can't place any a priori limit
35 * on IO_SPACE_LIMIT. These additional spaces are described in ACPI.
36 */
37#define IO_SPACE_LIMIT 0xffffffffffffffffUL
38
39#define MAX_IO_SPACES_BITS 8
40#define MAX_IO_SPACES (1UL << MAX_IO_SPACES_BITS)
41#define IO_SPACE_BITS 24
42#define IO_SPACE_SIZE (1UL << IO_SPACE_BITS)
43
44#define IO_SPACE_NR(port) ((port) >> IO_SPACE_BITS)
45#define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS)
46#define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1))
47
48#define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | ((p) & 0xfff))
49
50struct io_space {
51 unsigned long mmio_base; /* base in MMIO space */
52 int sparse;
53};
54
55extern struct io_space io_space[];
56extern unsigned int num_io_spaces;
57
58# ifdef __KERNEL__
59
60/*
61 * All MMIO iomem cookies are in region 6; anything less is a PIO cookie:
62 * 0xCxxxxxxxxxxxxxxx MMIO cookie (return from ioremap)
63 * 0x000000001SPPPPPP PIO cookie (S=space number, P..P=port)
64 *
65 * ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch
66 * code that uses bare port numbers without the prerequisite pci_iomap().
67 */
68#define PIO_OFFSET (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS))
69#define PIO_MASK (PIO_OFFSET - 1)
70#define PIO_RESERVED __IA64_UNCACHED_OFFSET
71#define HAVE_ARCH_PIO_SIZE
72
73#include <asm/intrinsics.h>
74#include <asm/machvec.h>
75#include <asm/page.h>
76#include <asm-generic/iomap.h>
77
78/*
79 * Change virtual addresses to physical addresses and vv.
80 */
81static inline unsigned long
82virt_to_phys (volatile void *address)
83{
84 return (unsigned long) address - PAGE_OFFSET;
85}
86
87static inline void*
88phys_to_virt (unsigned long address)
89{
90 return (void *) (address + PAGE_OFFSET);
91}
92
93#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
94extern u64 kern_mem_attribute (unsigned long phys_addr, unsigned long size);
95extern int valid_phys_addr_range (phys_addr_t addr, size_t count); /* efi.c */
96extern int valid_mmap_phys_addr_range (unsigned long pfn, size_t count);
97
98/*
99 * The following two macros are deprecated and scheduled for removal.
100 * Please use the PCI-DMA interface defined in <asm/pci.h> instead.
101 */
102#define bus_to_virt phys_to_virt
103#define virt_to_bus virt_to_phys
104#define page_to_bus page_to_phys
105
106# endif /* KERNEL */
107
108/*
109 * Memory fence w/accept. This should never be used in code that is
110 * not IA-64 specific.
111 */
112#define __ia64_mf_a() ia64_mfa()
113
114/**
115 * ___ia64_mmiowb - I/O write barrier
116 *
117 * Ensure ordering of I/O space writes. This will make sure that writes
118 * following the barrier will arrive after all previous writes. For most
119 * ia64 platforms, this is a simple 'mf.a' instruction.
120 *
121 * See Documentation/driver-api/device-io.rst for more information.
122 */
123static inline void ___ia64_mmiowb(void)
124{
125 ia64_mfa();
126}
127
128static inline void*
129__ia64_mk_io_addr (unsigned long port)
130{
131 struct io_space *space;
132 unsigned long offset;
133
134 space = &io_space[IO_SPACE_NR(port)];
135 port = IO_SPACE_PORT(port);
136 if (space->sparse)
137 offset = IO_SPACE_SPARSE_ENCODING(port);
138 else
139 offset = port;
140
141 return (void *) (space->mmio_base | offset);
142}
143
144#define __ia64_inb ___ia64_inb
145#define __ia64_inw ___ia64_inw
146#define __ia64_inl ___ia64_inl
147#define __ia64_outb ___ia64_outb
148#define __ia64_outw ___ia64_outw
149#define __ia64_outl ___ia64_outl
150#define __ia64_readb ___ia64_readb
151#define __ia64_readw ___ia64_readw
152#define __ia64_readl ___ia64_readl
153#define __ia64_readq ___ia64_readq
154#define __ia64_readb_relaxed ___ia64_readb
155#define __ia64_readw_relaxed ___ia64_readw
156#define __ia64_readl_relaxed ___ia64_readl
157#define __ia64_readq_relaxed ___ia64_readq
158#define __ia64_writeb ___ia64_writeb
159#define __ia64_writew ___ia64_writew
160#define __ia64_writel ___ia64_writel
161#define __ia64_writeq ___ia64_writeq
162#define __ia64_mmiowb ___ia64_mmiowb
163
164/*
165 * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
166 * that the access has completed before executing other I/O accesses. Since we're doing
167 * the accesses through an uncachable (UC) translation, the CPU will execute them in
168 * program order. However, we still need to tell the compiler not to shuffle them around
169 * during optimization, which is why we use "volatile" pointers.
170 */
171
172static inline unsigned int
173___ia64_inb (unsigned long port)
174{
175 volatile unsigned char *addr = __ia64_mk_io_addr(port);
176 unsigned char ret;
177
178 ret = *addr;
179 __ia64_mf_a();
180 return ret;
181}
182
183static inline unsigned int
184___ia64_inw (unsigned long port)
185{
186 volatile unsigned short *addr = __ia64_mk_io_addr(port);
187 unsigned short ret;
188
189 ret = *addr;
190 __ia64_mf_a();
191 return ret;
192}
193
194static inline unsigned int
195___ia64_inl (unsigned long port)
196{
197 volatile unsigned int *addr = __ia64_mk_io_addr(port);
198 unsigned int ret;
199
200 ret = *addr;
201 __ia64_mf_a();
202 return ret;
203}
204
205static inline void
206___ia64_outb (unsigned char val, unsigned long port)
207{
208 volatile unsigned char *addr = __ia64_mk_io_addr(port);
209
210 *addr = val;
211 __ia64_mf_a();
212}
213
214static inline void
215___ia64_outw (unsigned short val, unsigned long port)
216{
217 volatile unsigned short *addr = __ia64_mk_io_addr(port);
218
219 *addr = val;
220 __ia64_mf_a();
221}
222
223static inline void
224___ia64_outl (unsigned int val, unsigned long port)
225{
226 volatile unsigned int *addr = __ia64_mk_io_addr(port);
227
228 *addr = val;
229 __ia64_mf_a();
230}
231
232static inline void
233__insb (unsigned long port, void *dst, unsigned long count)
234{
235 unsigned char *dp = dst;
236
237 while (count--)
238 *dp++ = platform_inb(port);
239}
240
241static inline void
242__insw (unsigned long port, void *dst, unsigned long count)
243{
244 unsigned short *dp = dst;
245
246 while (count--)
247 put_unaligned(platform_inw(port), dp++);
248}
249
250static inline void
251__insl (unsigned long port, void *dst, unsigned long count)
252{
253 unsigned int *dp = dst;
254
255 while (count--)
256 put_unaligned(platform_inl(port), dp++);
257}
258
259static inline void
260__outsb (unsigned long port, const void *src, unsigned long count)
261{
262 const unsigned char *sp = src;
263
264 while (count--)
265 platform_outb(*sp++, port);
266}
267
268static inline void
269__outsw (unsigned long port, const void *src, unsigned long count)
270{
271 const unsigned short *sp = src;
272
273 while (count--)
274 platform_outw(get_unaligned(sp++), port);
275}
276
277static inline void
278__outsl (unsigned long port, const void *src, unsigned long count)
279{
280 const unsigned int *sp = src;
281
282 while (count--)
283 platform_outl(get_unaligned(sp++), port);
284}
285
286/*
287 * Unfortunately, some platforms are broken and do not follow the IA-64 architecture
288 * specification regarding legacy I/O support. Thus, we have to make these operations
289 * platform dependent...
290 */
291#define __inb platform_inb
292#define __inw platform_inw
293#define __inl platform_inl
294#define __outb platform_outb
295#define __outw platform_outw
296#define __outl platform_outl
297#define __mmiowb platform_mmiowb
298
299#define inb(p) __inb(p)
300#define inw(p) __inw(p)
301#define inl(p) __inl(p)
302#define insb(p,d,c) __insb(p,d,c)
303#define insw(p,d,c) __insw(p,d,c)
304#define insl(p,d,c) __insl(p,d,c)
305#define outb(v,p) __outb(v,p)
306#define outw(v,p) __outw(v,p)
307#define outl(v,p) __outl(v,p)
308#define outsb(p,s,c) __outsb(p,s,c)
309#define outsw(p,s,c) __outsw(p,s,c)
310#define outsl(p,s,c) __outsl(p,s,c)
311#define mmiowb() __mmiowb()
312
313/*
314 * The address passed to these functions are ioremap()ped already.
315 *
316 * We need these to be machine vectors since some platforms don't provide
317 * DMA coherence via PIO reads (PCI drivers and the spec imply that this is
318 * a good idea). Writes are ok though for all existing ia64 platforms (and
319 * hopefully it'll stay that way).
320 */
321static inline unsigned char
322___ia64_readb (const volatile void __iomem *addr)
323{
324 return *(volatile unsigned char __force *)addr;
325}
326
327static inline unsigned short
328___ia64_readw (const volatile void __iomem *addr)
329{
330 return *(volatile unsigned short __force *)addr;
331}
332
333static inline unsigned int
334___ia64_readl (const volatile void __iomem *addr)
335{
336 return *(volatile unsigned int __force *) addr;
337}
338
339static inline unsigned long
340___ia64_readq (const volatile void __iomem *addr)
341{
342 return *(volatile unsigned long __force *) addr;
343}
344
345static inline void
346__writeb (unsigned char val, volatile void __iomem *addr)
347{
348 *(volatile unsigned char __force *) addr = val;
349}
350
351static inline void
352__writew (unsigned short val, volatile void __iomem *addr)
353{
354 *(volatile unsigned short __force *) addr = val;
355}
356
357static inline void
358__writel (unsigned int val, volatile void __iomem *addr)
359{
360 *(volatile unsigned int __force *) addr = val;
361}
362
363static inline void
364__writeq (unsigned long val, volatile void __iomem *addr)
365{
366 *(volatile unsigned long __force *) addr = val;
367}
368
369#define __readb platform_readb
370#define __readw platform_readw
371#define __readl platform_readl
372#define __readq platform_readq
373#define __readb_relaxed platform_readb_relaxed
374#define __readw_relaxed platform_readw_relaxed
375#define __readl_relaxed platform_readl_relaxed
376#define __readq_relaxed platform_readq_relaxed
377
378#define readb(a) __readb((a))
379#define readw(a) __readw((a))
380#define readl(a) __readl((a))
381#define readq(a) __readq((a))
382#define readb_relaxed(a) __readb_relaxed((a))
383#define readw_relaxed(a) __readw_relaxed((a))
384#define readl_relaxed(a) __readl_relaxed((a))
385#define readq_relaxed(a) __readq_relaxed((a))
386#define __raw_readb readb
387#define __raw_readw readw
388#define __raw_readl readl
389#define __raw_readq readq
390#define __raw_readb_relaxed readb_relaxed
391#define __raw_readw_relaxed readw_relaxed
392#define __raw_readl_relaxed readl_relaxed
393#define __raw_readq_relaxed readq_relaxed
394#define writeb(v,a) __writeb((v), (a))
395#define writew(v,a) __writew((v), (a))
396#define writel(v,a) __writel((v), (a))
397#define writeq(v,a) __writeq((v), (a))
398#define writeb_relaxed(v,a) __writeb((v), (a))
399#define writew_relaxed(v,a) __writew((v), (a))
400#define writel_relaxed(v,a) __writel((v), (a))
401#define writeq_relaxed(v,a) __writeq((v), (a))
402#define __raw_writeb writeb
403#define __raw_writew writew
404#define __raw_writel writel
405#define __raw_writeq writeq
406
407#ifndef inb_p
408# define inb_p inb
409#endif
410#ifndef inw_p
411# define inw_p inw
412#endif
413#ifndef inl_p
414# define inl_p inl
415#endif
416
417#ifndef outb_p
418# define outb_p outb
419#endif
420#ifndef outw_p
421# define outw_p outw
422#endif
423#ifndef outl_p
424# define outl_p outl
425#endif
426
427# ifdef __KERNEL__
428
429extern void __iomem * ioremap(unsigned long offset, unsigned long size);
430extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size);
431extern void iounmap (volatile void __iomem *addr);
432static inline void __iomem * ioremap_cache (unsigned long phys_addr, unsigned long size)
433{
434 return ioremap(phys_addr, size);
435}
436#define ioremap_cache ioremap_cache
437#define ioremap_uc ioremap_nocache
438
439
440/*
441 * String version of IO memory access ops:
442 */
443extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n);
444extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n);
445extern void memset_io(volatile void __iomem *s, int c, long n);
446
447# endif /* __KERNEL__ */
448
449#endif /* _ASM_IA64_IO_H */