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1/*
2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19#ifndef __ARM_KVM_MMU_H__
20#define __ARM_KVM_MMU_H__
21
22#include <asm/memory.h>
23#include <asm/page.h>
24
25/*
26 * We directly use the kernel VA for the HYP, as we can directly share
27 * the mapping (HTTBR "covers" TTBR1).
28 */
29#define HYP_PAGE_OFFSET_MASK UL(~0)
30#define HYP_PAGE_OFFSET PAGE_OFFSET
31#define KERN_TO_HYP(kva) (kva)
32
33/*
34 * Our virtual mapping for the boot-time MMU-enable code. Must be
35 * shared across all the page-tables. Conveniently, we use the vectors
36 * page, where no kernel data will ever be shared with HYP.
37 */
38#define TRAMPOLINE_VA UL(CONFIG_VECTORS_BASE)
39
40#ifndef __ASSEMBLY__
41
42#include <asm/cacheflush.h>
43#include <asm/pgalloc.h>
44
45int create_hyp_mappings(void *from, void *to);
46int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
47void free_boot_hyp_pgd(void);
48void free_hyp_pgds(void);
49
50int kvm_alloc_stage2_pgd(struct kvm *kvm);
51void kvm_free_stage2_pgd(struct kvm *kvm);
52int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
53 phys_addr_t pa, unsigned long size);
54
55int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
56
57void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
58
59phys_addr_t kvm_mmu_get_httbr(void);
60phys_addr_t kvm_mmu_get_boot_httbr(void);
61phys_addr_t kvm_get_idmap_vector(void);
62int kvm_mmu_init(void);
63void kvm_clear_hyp_idmap(void);
64
65static inline void kvm_set_pmd(pmd_t *pmd, pmd_t new_pmd)
66{
67 *pmd = new_pmd;
68 flush_pmd_entry(pmd);
69}
70
71static inline void kvm_set_pte(pte_t *pte, pte_t new_pte)
72{
73 *pte = new_pte;
74 /*
75 * flush_pmd_entry just takes a void pointer and cleans the necessary
76 * cache entries, so we can reuse the function for ptes.
77 */
78 flush_pmd_entry(pte);
79}
80
81static inline bool kvm_is_write_fault(unsigned long hsr)
82{
83 unsigned long hsr_ec = hsr >> HSR_EC_SHIFT;
84 if (hsr_ec == HSR_EC_IABT)
85 return false;
86 else if ((hsr & HSR_ISV) && !(hsr & HSR_WNR))
87 return false;
88 else
89 return true;
90}
91
92static inline void kvm_clean_pgd(pgd_t *pgd)
93{
94 clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
95}
96
97static inline void kvm_clean_pmd_entry(pmd_t *pmd)
98{
99 clean_pmd_entry(pmd);
100}
101
102static inline void kvm_clean_pte(pte_t *pte)
103{
104 clean_pte_table(pte);
105}
106
107static inline void kvm_set_s2pte_writable(pte_t *pte)
108{
109 pte_val(*pte) |= L_PTE_S2_RDWR;
110}
111
112static inline void kvm_set_s2pmd_writable(pmd_t *pmd)
113{
114 pmd_val(*pmd) |= L_PMD_S2_RDWR;
115}
116
117/* Open coded p*d_addr_end that can deal with 64bit addresses */
118#define kvm_pgd_addr_end(addr, end) \
119({ u64 __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
120 (__boundary - 1 < (end) - 1)? __boundary: (end); \
121})
122
123#define kvm_pud_addr_end(addr,end) (end)
124
125#define kvm_pmd_addr_end(addr, end) \
126({ u64 __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
127 (__boundary - 1 < (end) - 1)? __boundary: (end); \
128})
129
130struct kvm;
131
132#define kvm_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l))
133
134static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
135{
136 return (vcpu->arch.cp15[c1_SCTLR] & 0b101) == 0b101;
137}
138
139static inline void coherent_cache_guest_page(struct kvm_vcpu *vcpu, hva_t hva,
140 unsigned long size)
141{
142 if (!vcpu_has_cache_enabled(vcpu))
143 kvm_flush_dcache_to_poc((void *)hva, size);
144
145 /*
146 * If we are going to insert an instruction page and the icache is
147 * either VIPT or PIPT, there is a potential problem where the host
148 * (or another VM) may have used the same page as this guest, and we
149 * read incorrect data from the icache. If we're using a PIPT cache,
150 * we can invalidate just that page, but if we are using a VIPT cache
151 * we need to invalidate the entire icache - damn shame - as written
152 * in the ARM ARM (DDI 0406C.b - Page B3-1393).
153 *
154 * VIVT caches are tagged using both the ASID and the VMID and doesn't
155 * need any kind of flushing (DDI 0406C.b - Page B3-1392).
156 */
157 if (icache_is_pipt()) {
158 __cpuc_coherent_user_range(hva, hva + size);
159 } else if (!icache_is_vivt_asid_tagged()) {
160 /* any kind of VIPT cache */
161 __flush_icache_all();
162 }
163}
164
165#define kvm_virt_to_phys(x) virt_to_idmap((unsigned long)(x))
166
167void stage2_flush_vm(struct kvm *kvm);
168
169#endif /* !__ASSEMBLY__ */
170
171#endif /* __ARM_KVM_MMU_H__ */
1/*
2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19#ifndef __ARM_KVM_MMU_H__
20#define __ARM_KVM_MMU_H__
21
22#include <asm/memory.h>
23#include <asm/page.h>
24
25/*
26 * We directly use the kernel VA for the HYP, as we can directly share
27 * the mapping (HTTBR "covers" TTBR1).
28 */
29#define kern_hyp_va(kva) (kva)
30
31/* Contrary to arm64, there is no need to generate a PC-relative address */
32#define hyp_symbol_addr(s) \
33 ({ \
34 typeof(s) *addr = &(s); \
35 addr; \
36 })
37
38/*
39 * KVM_MMU_CACHE_MIN_PAGES is the number of stage2 page table translation levels.
40 */
41#define KVM_MMU_CACHE_MIN_PAGES 2
42
43#ifndef __ASSEMBLY__
44
45#include <linux/highmem.h>
46#include <asm/cacheflush.h>
47#include <asm/cputype.h>
48#include <asm/kvm_hyp.h>
49#include <asm/pgalloc.h>
50#include <asm/stage2_pgtable.h>
51
52/* Ensure compatibility with arm64 */
53#define VA_BITS 32
54
55int create_hyp_mappings(void *from, void *to, pgprot_t prot);
56int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size,
57 void __iomem **kaddr,
58 void __iomem **haddr);
59int create_hyp_exec_mappings(phys_addr_t phys_addr, size_t size,
60 void **haddr);
61void free_hyp_pgds(void);
62
63void stage2_unmap_vm(struct kvm *kvm);
64int kvm_alloc_stage2_pgd(struct kvm *kvm);
65void kvm_free_stage2_pgd(struct kvm *kvm);
66int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
67 phys_addr_t pa, unsigned long size, bool writable);
68
69int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
70
71void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
72
73phys_addr_t kvm_mmu_get_httbr(void);
74phys_addr_t kvm_get_idmap_vector(void);
75int kvm_mmu_init(void);
76void kvm_clear_hyp_idmap(void);
77
78static inline void kvm_set_pmd(pmd_t *pmd, pmd_t new_pmd)
79{
80 *pmd = new_pmd;
81 dsb(ishst);
82}
83
84static inline void kvm_set_pte(pte_t *pte, pte_t new_pte)
85{
86 *pte = new_pte;
87 dsb(ishst);
88}
89
90static inline pte_t kvm_s2pte_mkwrite(pte_t pte)
91{
92 pte_val(pte) |= L_PTE_S2_RDWR;
93 return pte;
94}
95
96static inline pmd_t kvm_s2pmd_mkwrite(pmd_t pmd)
97{
98 pmd_val(pmd) |= L_PMD_S2_RDWR;
99 return pmd;
100}
101
102static inline pte_t kvm_s2pte_mkexec(pte_t pte)
103{
104 pte_val(pte) &= ~L_PTE_XN;
105 return pte;
106}
107
108static inline pmd_t kvm_s2pmd_mkexec(pmd_t pmd)
109{
110 pmd_val(pmd) &= ~PMD_SECT_XN;
111 return pmd;
112}
113
114static inline void kvm_set_s2pte_readonly(pte_t *pte)
115{
116 pte_val(*pte) = (pte_val(*pte) & ~L_PTE_S2_RDWR) | L_PTE_S2_RDONLY;
117}
118
119static inline bool kvm_s2pte_readonly(pte_t *pte)
120{
121 return (pte_val(*pte) & L_PTE_S2_RDWR) == L_PTE_S2_RDONLY;
122}
123
124static inline bool kvm_s2pte_exec(pte_t *pte)
125{
126 return !(pte_val(*pte) & L_PTE_XN);
127}
128
129static inline void kvm_set_s2pmd_readonly(pmd_t *pmd)
130{
131 pmd_val(*pmd) = (pmd_val(*pmd) & ~L_PMD_S2_RDWR) | L_PMD_S2_RDONLY;
132}
133
134static inline bool kvm_s2pmd_readonly(pmd_t *pmd)
135{
136 return (pmd_val(*pmd) & L_PMD_S2_RDWR) == L_PMD_S2_RDONLY;
137}
138
139static inline bool kvm_s2pmd_exec(pmd_t *pmd)
140{
141 return !(pmd_val(*pmd) & PMD_SECT_XN);
142}
143
144static inline bool kvm_page_empty(void *ptr)
145{
146 struct page *ptr_page = virt_to_page(ptr);
147 return page_count(ptr_page) == 1;
148}
149
150#define kvm_pte_table_empty(kvm, ptep) kvm_page_empty(ptep)
151#define kvm_pmd_table_empty(kvm, pmdp) kvm_page_empty(pmdp)
152#define kvm_pud_table_empty(kvm, pudp) false
153
154#define hyp_pte_table_empty(ptep) kvm_page_empty(ptep)
155#define hyp_pmd_table_empty(pmdp) kvm_page_empty(pmdp)
156#define hyp_pud_table_empty(pudp) false
157
158struct kvm;
159
160#define kvm_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l))
161
162static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
163{
164 return (vcpu_cp15(vcpu, c1_SCTLR) & 0b101) == 0b101;
165}
166
167static inline void __clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size)
168{
169 /*
170 * Clean the dcache to the Point of Coherency.
171 *
172 * We need to do this through a kernel mapping (using the
173 * user-space mapping has proved to be the wrong
174 * solution). For that, we need to kmap one page at a time,
175 * and iterate over the range.
176 */
177
178 VM_BUG_ON(size & ~PAGE_MASK);
179
180 while (size) {
181 void *va = kmap_atomic_pfn(pfn);
182
183 kvm_flush_dcache_to_poc(va, PAGE_SIZE);
184
185 size -= PAGE_SIZE;
186 pfn++;
187
188 kunmap_atomic(va);
189 }
190}
191
192static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn,
193 unsigned long size)
194{
195 u32 iclsz;
196
197 /*
198 * If we are going to insert an instruction page and the icache is
199 * either VIPT or PIPT, there is a potential problem where the host
200 * (or another VM) may have used the same page as this guest, and we
201 * read incorrect data from the icache. If we're using a PIPT cache,
202 * we can invalidate just that page, but if we are using a VIPT cache
203 * we need to invalidate the entire icache - damn shame - as written
204 * in the ARM ARM (DDI 0406C.b - Page B3-1393).
205 *
206 * VIVT caches are tagged using both the ASID and the VMID and doesn't
207 * need any kind of flushing (DDI 0406C.b - Page B3-1392).
208 */
209
210 VM_BUG_ON(size & ~PAGE_MASK);
211
212 if (icache_is_vivt_asid_tagged())
213 return;
214
215 if (!icache_is_pipt()) {
216 /* any kind of VIPT cache */
217 __flush_icache_all();
218 return;
219 }
220
221 /*
222 * CTR IminLine contains Log2 of the number of words in the
223 * cache line, so we can get the number of words as
224 * 2 << (IminLine - 1). To get the number of bytes, we
225 * multiply by 4 (the number of bytes in a 32-bit word), and
226 * get 4 << (IminLine).
227 */
228 iclsz = 4 << (read_cpuid(CPUID_CACHETYPE) & 0xf);
229
230 while (size) {
231 void *va = kmap_atomic_pfn(pfn);
232 void *end = va + PAGE_SIZE;
233 void *addr = va;
234
235 do {
236 write_sysreg(addr, ICIMVAU);
237 addr += iclsz;
238 } while (addr < end);
239
240 dsb(ishst);
241 isb();
242
243 size -= PAGE_SIZE;
244 pfn++;
245
246 kunmap_atomic(va);
247 }
248
249 /* Check if we need to invalidate the BTB */
250 if ((read_cpuid_ext(CPUID_EXT_MMFR1) >> 28) != 4) {
251 write_sysreg(0, BPIALLIS);
252 dsb(ishst);
253 isb();
254 }
255}
256
257static inline void __kvm_flush_dcache_pte(pte_t pte)
258{
259 void *va = kmap_atomic(pte_page(pte));
260
261 kvm_flush_dcache_to_poc(va, PAGE_SIZE);
262
263 kunmap_atomic(va);
264}
265
266static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
267{
268 unsigned long size = PMD_SIZE;
269 kvm_pfn_t pfn = pmd_pfn(pmd);
270
271 while (size) {
272 void *va = kmap_atomic_pfn(pfn);
273
274 kvm_flush_dcache_to_poc(va, PAGE_SIZE);
275
276 pfn++;
277 size -= PAGE_SIZE;
278
279 kunmap_atomic(va);
280 }
281}
282
283static inline void __kvm_flush_dcache_pud(pud_t pud)
284{
285}
286
287#define kvm_virt_to_phys(x) virt_to_idmap((unsigned long)(x))
288
289void kvm_set_way_flush(struct kvm_vcpu *vcpu);
290void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
291
292static inline bool __kvm_cpu_uses_extended_idmap(void)
293{
294 return false;
295}
296
297static inline unsigned long __kvm_idmap_ptrs_per_pgd(void)
298{
299 return PTRS_PER_PGD;
300}
301
302static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd,
303 pgd_t *hyp_pgd,
304 pgd_t *merged_hyp_pgd,
305 unsigned long hyp_idmap_start) { }
306
307static inline unsigned int kvm_get_vmid_bits(void)
308{
309 return 8;
310}
311
312/*
313 * We are not in the kvm->srcu critical section most of the time, so we take
314 * the SRCU read lock here. Since we copy the data from the user page, we
315 * can immediately drop the lock again.
316 */
317static inline int kvm_read_guest_lock(struct kvm *kvm,
318 gpa_t gpa, void *data, unsigned long len)
319{
320 int srcu_idx = srcu_read_lock(&kvm->srcu);
321 int ret = kvm_read_guest(kvm, gpa, data, len);
322
323 srcu_read_unlock(&kvm->srcu, srcu_idx);
324
325 return ret;
326}
327
328static inline void *kvm_get_hyp_vector(void)
329{
330 return kvm_ksym_ref(__kvm_hyp_vector);
331}
332
333static inline int kvm_map_vectors(void)
334{
335 return 0;
336}
337
338#define kvm_phys_to_vttbr(addr) (addr)
339
340#endif /* !__ASSEMBLY__ */
341
342#endif /* __ARM_KVM_MMU_H__ */