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1/*
2 * R-Car SYSC Power management support
3 *
4 * Copyright (C) 2014 Magnus Damm
5 * Copyright (C) 2015-2016 Glider bvba
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/clk/renesas.h>
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/mm.h>
16#include <linux/of_address.h>
17#include <linux/pm_domain.h>
18#include <linux/slab.h>
19#include <linux/spinlock.h>
20#include <linux/io.h>
21#include <linux/soc/renesas/rcar-sysc.h>
22
23#include "rcar-sysc.h"
24
25/* SYSC Common */
26#define SYSCSR 0x00 /* SYSC Status Register */
27#define SYSCISR 0x04 /* Interrupt Status Register */
28#define SYSCISCR 0x08 /* Interrupt Status Clear Register */
29#define SYSCIER 0x0c /* Interrupt Enable Register */
30#define SYSCIMR 0x10 /* Interrupt Mask Register */
31
32/* SYSC Status Register */
33#define SYSCSR_PONENB 1 /* Ready for power resume requests */
34#define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
35
36/*
37 * Power Control Register Offsets inside the register block for each domain
38 * Note: The "CR" registers for ARM cores exist on H1 only
39 * Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
40 * Use PSCI on R-Car Gen3
41 */
42#define PWRSR_OFFS 0x00 /* Power Status Register */
43#define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
44#define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
45#define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
46#define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
47#define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
48
49
50#define SYSCSR_RETRIES 100
51#define SYSCSR_DELAY_US 1
52
53#define PWRER_RETRIES 100
54#define PWRER_DELAY_US 1
55
56#define SYSCISR_RETRIES 1000
57#define SYSCISR_DELAY_US 1
58
59#define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */
60
61static void __iomem *rcar_sysc_base;
62static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
63
64static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
65{
66 unsigned int sr_bit, reg_offs;
67 int k;
68
69 if (on) {
70 sr_bit = SYSCSR_PONENB;
71 reg_offs = PWRONCR_OFFS;
72 } else {
73 sr_bit = SYSCSR_POFFENB;
74 reg_offs = PWROFFCR_OFFS;
75 }
76
77 /* Wait until SYSC is ready to accept a power request */
78 for (k = 0; k < SYSCSR_RETRIES; k++) {
79 if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
80 break;
81 udelay(SYSCSR_DELAY_US);
82 }
83
84 if (k == SYSCSR_RETRIES)
85 return -EAGAIN;
86
87 /* Submit power shutoff or power resume request */
88 iowrite32(BIT(sysc_ch->chan_bit),
89 rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
90
91 return 0;
92}
93
94static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
95{
96 unsigned int isr_mask = BIT(sysc_ch->isr_bit);
97 unsigned int chan_mask = BIT(sysc_ch->chan_bit);
98 unsigned int status;
99 unsigned long flags;
100 int ret = 0;
101 int k;
102
103 spin_lock_irqsave(&rcar_sysc_lock, flags);
104
105 iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
106
107 /* Submit power shutoff or resume request until it was accepted */
108 for (k = 0; k < PWRER_RETRIES; k++) {
109 ret = rcar_sysc_pwr_on_off(sysc_ch, on);
110 if (ret)
111 goto out;
112
113 status = ioread32(rcar_sysc_base +
114 sysc_ch->chan_offs + PWRER_OFFS);
115 if (!(status & chan_mask))
116 break;
117
118 udelay(PWRER_DELAY_US);
119 }
120
121 if (k == PWRER_RETRIES) {
122 ret = -EIO;
123 goto out;
124 }
125
126 /* Wait until the power shutoff or resume request has completed * */
127 for (k = 0; k < SYSCISR_RETRIES; k++) {
128 if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
129 break;
130 udelay(SYSCISR_DELAY_US);
131 }
132
133 if (k == SYSCISR_RETRIES)
134 ret = -EIO;
135
136 iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
137
138 out:
139 spin_unlock_irqrestore(&rcar_sysc_lock, flags);
140
141 pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
142 sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
143 return ret;
144}
145
146int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch)
147{
148 return rcar_sysc_power(sysc_ch, false);
149}
150
151int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch)
152{
153 return rcar_sysc_power(sysc_ch, true);
154}
155
156static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
157{
158 unsigned int st;
159
160 st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
161 if (st & BIT(sysc_ch->chan_bit))
162 return true;
163
164 return false;
165}
166
167struct rcar_sysc_pd {
168 struct generic_pm_domain genpd;
169 struct rcar_sysc_ch ch;
170 unsigned int flags;
171 char name[0];
172};
173
174static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d)
175{
176 return container_of(d, struct rcar_sysc_pd, genpd);
177}
178
179static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
180{
181 struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
182
183 pr_debug("%s: %s\n", __func__, genpd->name);
184
185 if (pd->flags & PD_NO_CR) {
186 pr_debug("%s: Cannot control %s\n", __func__, genpd->name);
187 return -EBUSY;
188 }
189
190 if (pd->flags & PD_BUSY) {
191 pr_debug("%s: %s busy\n", __func__, genpd->name);
192 return -EBUSY;
193 }
194
195 return rcar_sysc_power_down(&pd->ch);
196}
197
198static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
199{
200 struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
201
202 pr_debug("%s: %s\n", __func__, genpd->name);
203
204 if (pd->flags & PD_NO_CR) {
205 pr_debug("%s: Cannot control %s\n", __func__, genpd->name);
206 return 0;
207 }
208
209 return rcar_sysc_power_up(&pd->ch);
210}
211
212static bool has_cpg_mstp;
213
214static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
215{
216 struct generic_pm_domain *genpd = &pd->genpd;
217 const char *name = pd->genpd.name;
218 struct dev_power_governor *gov = &simple_qos_governor;
219
220 if (pd->flags & PD_CPU) {
221 /*
222 * This domain contains a CPU core and therefore it should
223 * only be turned off if the CPU is not in use.
224 */
225 pr_debug("PM domain %s contains %s\n", name, "CPU");
226 pd->flags |= PD_BUSY;
227 gov = &pm_domain_always_on_gov;
228 } else if (pd->flags & PD_SCU) {
229 /*
230 * This domain contains an SCU and cache-controller, and
231 * therefore it should only be turned off if the CPU cores are
232 * not in use.
233 */
234 pr_debug("PM domain %s contains %s\n", name, "SCU");
235 pd->flags |= PD_BUSY;
236 gov = &pm_domain_always_on_gov;
237 } else if (pd->flags & PD_NO_CR) {
238 /*
239 * This domain cannot be turned off.
240 */
241 pd->flags |= PD_BUSY;
242 gov = &pm_domain_always_on_gov;
243 }
244
245 if (!(pd->flags & (PD_CPU | PD_SCU))) {
246 /* Enable Clock Domain for I/O devices */
247 genpd->flags = GENPD_FLAG_PM_CLK;
248 if (has_cpg_mstp) {
249 genpd->attach_dev = cpg_mstp_attach_dev;
250 genpd->detach_dev = cpg_mstp_detach_dev;
251 } else {
252 genpd->attach_dev = cpg_mssr_attach_dev;
253 genpd->detach_dev = cpg_mssr_detach_dev;
254 }
255 }
256
257 genpd->power_off = rcar_sysc_pd_power_off;
258 genpd->power_on = rcar_sysc_pd_power_on;
259
260 if (pd->flags & (PD_CPU | PD_NO_CR)) {
261 /* Skip CPUs (handled by SMP code) and areas without control */
262 pr_debug("%s: Not touching %s\n", __func__, genpd->name);
263 goto finalize;
264 }
265
266 if (!rcar_sysc_power_is_off(&pd->ch)) {
267 pr_debug("%s: %s is already powered\n", __func__, genpd->name);
268 goto finalize;
269 }
270
271 rcar_sysc_power_up(&pd->ch);
272
273finalize:
274 pm_genpd_init(genpd, gov, false);
275}
276
277static const struct of_device_id rcar_sysc_matches[] = {
278#ifdef CONFIG_ARCH_R8A7743
279 { .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
280#endif
281#ifdef CONFIG_ARCH_R8A7745
282 { .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
283#endif
284#ifdef CONFIG_ARCH_R8A7779
285 { .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
286#endif
287#ifdef CONFIG_ARCH_R8A7790
288 { .compatible = "renesas,r8a7790-sysc", .data = &r8a7790_sysc_info },
289#endif
290#ifdef CONFIG_ARCH_R8A7791
291 { .compatible = "renesas,r8a7791-sysc", .data = &r8a7791_sysc_info },
292#endif
293#ifdef CONFIG_ARCH_R8A7792
294 { .compatible = "renesas,r8a7792-sysc", .data = &r8a7792_sysc_info },
295#endif
296#ifdef CONFIG_ARCH_R8A7793
297 /* R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. */
298 { .compatible = "renesas,r8a7793-sysc", .data = &r8a7791_sysc_info },
299#endif
300#ifdef CONFIG_ARCH_R8A7794
301 { .compatible = "renesas,r8a7794-sysc", .data = &r8a7794_sysc_info },
302#endif
303#ifdef CONFIG_ARCH_R8A7795
304 { .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
305#endif
306#ifdef CONFIG_ARCH_R8A7796
307 { .compatible = "renesas,r8a7796-sysc", .data = &r8a7796_sysc_info },
308#endif
309 { /* sentinel */ }
310};
311
312struct rcar_pm_domains {
313 struct genpd_onecell_data onecell_data;
314 struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1];
315};
316
317static int __init rcar_sysc_pd_init(void)
318{
319 const struct rcar_sysc_info *info;
320 const struct of_device_id *match;
321 struct rcar_pm_domains *domains;
322 struct device_node *np;
323 u32 syscier, syscimr;
324 void __iomem *base;
325 unsigned int i;
326 int error;
327
328 if (rcar_sysc_base)
329 return 0;
330
331 np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match);
332 if (!np)
333 return -ENODEV;
334
335 info = match->data;
336
337 has_cpg_mstp = of_find_compatible_node(NULL, NULL,
338 "renesas,cpg-mstp-clocks");
339
340 base = of_iomap(np, 0);
341 if (!base) {
342 pr_warn("%s: Cannot map regs\n", np->full_name);
343 error = -ENOMEM;
344 goto out_put;
345 }
346
347 rcar_sysc_base = base;
348
349 domains = kzalloc(sizeof(*domains), GFP_KERNEL);
350 if (!domains) {
351 error = -ENOMEM;
352 goto out_put;
353 }
354
355 domains->onecell_data.domains = domains->domains;
356 domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
357
358 for (i = 0, syscier = 0; i < info->num_areas; i++)
359 syscier |= BIT(info->areas[i].isr_bit);
360
361 /*
362 * Mask all interrupt sources to prevent the CPU from receiving them.
363 * Make sure not to clear reserved bits that were set before.
364 */
365 syscimr = ioread32(base + SYSCIMR);
366 syscimr |= syscier;
367 pr_debug("%s: syscimr = 0x%08x\n", np->full_name, syscimr);
368 iowrite32(syscimr, base + SYSCIMR);
369
370 /*
371 * SYSC needs all interrupt sources enabled to control power.
372 */
373 pr_debug("%s: syscier = 0x%08x\n", np->full_name, syscier);
374 iowrite32(syscier, base + SYSCIER);
375
376 for (i = 0; i < info->num_areas; i++) {
377 const struct rcar_sysc_area *area = &info->areas[i];
378 struct rcar_sysc_pd *pd;
379
380 pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
381 if (!pd) {
382 error = -ENOMEM;
383 goto out_put;
384 }
385
386 strcpy(pd->name, area->name);
387 pd->genpd.name = pd->name;
388 pd->ch.chan_offs = area->chan_offs;
389 pd->ch.chan_bit = area->chan_bit;
390 pd->ch.isr_bit = area->isr_bit;
391 pd->flags = area->flags;
392
393 rcar_sysc_pd_setup(pd);
394 if (area->parent >= 0)
395 pm_genpd_add_subdomain(domains->domains[area->parent],
396 &pd->genpd);
397
398 domains->domains[area->isr_bit] = &pd->genpd;
399 }
400
401 error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
402
403out_put:
404 of_node_put(np);
405 return error;
406}
407early_initcall(rcar_sysc_pd_init);
408
409void __init rcar_sysc_init(phys_addr_t base, u32 syscier)
410{
411 u32 syscimr;
412
413 if (!rcar_sysc_pd_init())
414 return;
415
416 rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
417
418 /*
419 * Mask all interrupt sources to prevent the CPU from receiving them.
420 * Make sure not to clear reserved bits that were set before.
421 */
422 syscimr = ioread32(rcar_sysc_base + SYSCIMR);
423 syscimr |= syscier;
424 pr_debug("%s: syscimr = 0x%08x\n", __func__, syscimr);
425 iowrite32(syscimr, rcar_sysc_base + SYSCIMR);
426
427 /*
428 * SYSC needs all interrupt sources enabled to control power.
429 */
430 pr_debug("%s: syscier = 0x%08x\n", __func__, syscier);
431 iowrite32(syscier, rcar_sysc_base + SYSCIER);
432}