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1/*
2 * PS3 Platfom gelic network driver.
3 *
4 * Copyright (C) 2007 Sony Computer Entertainment Inc.
5 * Copyright 2006, 2007 Sony Corporation.
6 *
7 * This file is based on: spider_net.h
8 *
9 * (C) Copyright IBM Corp. 2005
10 *
11 * Authors : Utz Bacher <utz.bacher@de.ibm.com>
12 * Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2, or (at your option)
17 * any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28#ifndef _GELIC_NET_H
29#define _GELIC_NET_H
30
31/* descriptors */
32#define GELIC_NET_RX_DESCRIPTORS 128 /* num of descriptors */
33#define GELIC_NET_TX_DESCRIPTORS 128 /* num of descriptors */
34
35#define GELIC_NET_MAX_MTU VLAN_ETH_FRAME_LEN
36#define GELIC_NET_MIN_MTU VLAN_ETH_ZLEN
37#define GELIC_NET_RXBUF_ALIGN 128
38#define GELIC_CARD_RX_CSUM_DEFAULT 1 /* hw chksum */
39#define GELIC_NET_WATCHDOG_TIMEOUT 5*HZ
40#define GELIC_NET_BROADCAST_ADDR 0xffffffffffffL
41
42#define GELIC_NET_MC_COUNT_MAX 32 /* multicast address list */
43
44/* virtual interrupt status register bits */
45 /* INT1 */
46#define GELIC_CARD_TX_RAM_FULL_ERR 0x0000000000000001L
47#define GELIC_CARD_RX_RAM_FULL_ERR 0x0000000000000002L
48#define GELIC_CARD_TX_SHORT_FRAME_ERR 0x0000000000000004L
49#define GELIC_CARD_TX_INVALID_DESCR_ERR 0x0000000000000008L
50#define GELIC_CARD_RX_FIFO_FULL_ERR 0x0000000000002000L
51#define GELIC_CARD_RX_DESCR_CHAIN_END 0x0000000000004000L
52#define GELIC_CARD_RX_INVALID_DESCR_ERR 0x0000000000008000L
53#define GELIC_CARD_TX_RESPONCE_ERR 0x0000000000010000L
54#define GELIC_CARD_RX_RESPONCE_ERR 0x0000000000100000L
55#define GELIC_CARD_TX_PROTECTION_ERR 0x0000000000400000L
56#define GELIC_CARD_RX_PROTECTION_ERR 0x0000000004000000L
57#define GELIC_CARD_TX_TCP_UDP_CHECKSUM_ERR 0x0000000008000000L
58#define GELIC_CARD_PORT_STATUS_CHANGED 0x0000000020000000L
59#define GELIC_CARD_WLAN_EVENT_RECEIVED 0x0000000040000000L
60#define GELIC_CARD_WLAN_COMMAND_COMPLETED 0x0000000080000000L
61 /* INT 0 */
62#define GELIC_CARD_TX_FLAGGED_DESCR 0x0004000000000000L
63#define GELIC_CARD_RX_FLAGGED_DESCR 0x0040000000000000L
64#define GELIC_CARD_TX_TRANSFER_END 0x0080000000000000L
65#define GELIC_CARD_TX_DESCR_CHAIN_END 0x0100000000000000L
66#define GELIC_CARD_NUMBER_OF_RX_FRAME 0x1000000000000000L
67#define GELIC_CARD_ONE_TIME_COUNT_TIMER 0x4000000000000000L
68#define GELIC_CARD_FREE_RUN_COUNT_TIMER 0x8000000000000000L
69
70/* initial interrupt mask */
71#define GELIC_CARD_TXINT GELIC_CARD_TX_DESCR_CHAIN_END
72
73#define GELIC_CARD_RXINT (GELIC_CARD_RX_DESCR_CHAIN_END | \
74 GELIC_CARD_NUMBER_OF_RX_FRAME)
75
76 /* RX descriptor data_status bits */
77enum gelic_descr_rx_status {
78 GELIC_DESCR_RXDMADU = 0x80000000, /* destination MAC addr unknown */
79 GELIC_DESCR_RXLSTFBF = 0x40000000, /* last frame buffer */
80 GELIC_DESCR_RXIPCHK = 0x20000000, /* IP checksum performed */
81 GELIC_DESCR_RXTCPCHK = 0x10000000, /* TCP/UDP checksup performed */
82 GELIC_DESCR_RXWTPKT = 0x00C00000, /*
83 * wakeup trigger packet
84 * 01: Magic Packet (TM)
85 * 10: ARP packet
86 * 11: Multicast MAC addr
87 */
88 GELIC_DESCR_RXVLNPKT = 0x00200000, /* VLAN packet */
89 /* bit 20..16 reserved */
90 GELIC_DESCR_RXRRECNUM = 0x0000ff00, /* reception receipt number */
91 /* bit 7..0 reserved */
92};
93
94#define GELIC_DESCR_DATA_STATUS_CHK_MASK \
95 (GELIC_DESCR_RXIPCHK | GELIC_DESCR_RXTCPCHK)
96
97 /* TX descriptor data_status bits */
98enum gelic_descr_tx_status {
99 GELIC_DESCR_TX_TAIL = 0x00000001, /* gelic treated this
100 * descriptor was end of
101 * a tx frame
102 */
103};
104
105/* RX descriptor data error bits */
106enum gelic_descr_rx_error {
107 /* bit 31 reserved */
108 GELIC_DESCR_RXALNERR = 0x40000000, /* alignement error 10/100M */
109 GELIC_DESCR_RXOVERERR = 0x20000000, /* oversize error */
110 GELIC_DESCR_RXRNTERR = 0x10000000, /* Runt error */
111 GELIC_DESCR_RXIPCHKERR = 0x08000000, /* IP checksum error */
112 GELIC_DESCR_RXTCPCHKERR = 0x04000000, /* TCP/UDP checksum error */
113 GELIC_DESCR_RXDRPPKT = 0x00100000, /* drop packet */
114 GELIC_DESCR_RXIPFMTERR = 0x00080000, /* IP packet format error */
115 /* bit 18 reserved */
116 GELIC_DESCR_RXDATAERR = 0x00020000, /* IP packet format error */
117 GELIC_DESCR_RXCALERR = 0x00010000, /* cariier extension length
118 * error */
119 GELIC_DESCR_RXCREXERR = 0x00008000, /* carrier extension error */
120 GELIC_DESCR_RXMLTCST = 0x00004000, /* multicast address frame */
121 /* bit 13..0 reserved */
122};
123#define GELIC_DESCR_DATA_ERROR_CHK_MASK \
124 (GELIC_DESCR_RXIPCHKERR | GELIC_DESCR_RXTCPCHKERR)
125
126/* DMA command and status (RX and TX)*/
127enum gelic_descr_dma_status {
128 GELIC_DESCR_DMA_COMPLETE = 0x00000000, /* used in tx */
129 GELIC_DESCR_DMA_BUFFER_FULL = 0x00000000, /* used in rx */
130 GELIC_DESCR_DMA_RESPONSE_ERROR = 0x10000000, /* used in rx, tx */
131 GELIC_DESCR_DMA_PROTECTION_ERROR = 0x20000000, /* used in rx, tx */
132 GELIC_DESCR_DMA_FRAME_END = 0x40000000, /* used in rx */
133 GELIC_DESCR_DMA_FORCE_END = 0x50000000, /* used in rx, tx */
134 GELIC_DESCR_DMA_CARDOWNED = 0xa0000000, /* used in rx, tx */
135 GELIC_DESCR_DMA_NOT_IN_USE = 0xb0000000, /* any other value */
136};
137
138#define GELIC_DESCR_DMA_STAT_MASK (0xf0000000)
139
140/* tx descriptor command and status */
141enum gelic_descr_tx_dma_status {
142 /* [19] */
143 GELIC_DESCR_TX_DMA_IKE = 0x00080000, /* IPSEC off */
144 /* [18] */
145 GELIC_DESCR_TX_DMA_FRAME_TAIL = 0x00040000, /* last descriptor of
146 * the packet
147 */
148 /* [17..16] */
149 GELIC_DESCR_TX_DMA_TCP_CHKSUM = 0x00020000, /* TCP packet */
150 GELIC_DESCR_TX_DMA_UDP_CHKSUM = 0x00030000, /* UDP packet */
151 GELIC_DESCR_TX_DMA_NO_CHKSUM = 0x00000000, /* no checksum */
152
153 /* [1] */
154 GELIC_DESCR_TX_DMA_CHAIN_END = 0x00000002, /* DMA terminated
155 * due to chain end
156 */
157};
158
159#define GELIC_DESCR_DMA_CMD_NO_CHKSUM \
160 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
161 GELIC_DESCR_TX_DMA_NO_CHKSUM)
162
163#define GELIC_DESCR_DMA_CMD_TCP_CHKSUM \
164 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
165 GELIC_DESCR_TX_DMA_TCP_CHKSUM)
166
167#define GELIC_DESCR_DMA_CMD_UDP_CHKSUM \
168 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
169 GELIC_DESCR_TX_DMA_UDP_CHKSUM)
170
171enum gelic_descr_rx_dma_status {
172 /* [ 1 ] */
173 GELIC_DESCR_RX_DMA_CHAIN_END = 0x00000002, /* DMA terminated
174 * due to chain end
175 */
176};
177
178/* for lv1_net_control */
179enum gelic_lv1_net_control_code {
180 GELIC_LV1_GET_MAC_ADDRESS = 1,
181 GELIC_LV1_GET_ETH_PORT_STATUS = 2,
182 GELIC_LV1_SET_NEGOTIATION_MODE = 3,
183 GELIC_LV1_GET_VLAN_ID = 4,
184 GELIC_LV1_SET_WOL = 5,
185 GELIC_LV1_GET_CHANNEL = 6,
186 GELIC_LV1_POST_WLAN_CMD = 9,
187 GELIC_LV1_GET_WLAN_CMD_RESULT = 10,
188 GELIC_LV1_GET_WLAN_EVENT = 11,
189};
190
191/* for GELIC_LV1_SET_WOL */
192enum gelic_lv1_wol_command {
193 GELIC_LV1_WOL_MAGIC_PACKET = 1,
194 GELIC_LV1_WOL_ADD_MATCH_ADDR = 6,
195 GELIC_LV1_WOL_DELETE_MATCH_ADDR = 7,
196};
197
198/* for GELIC_LV1_WOL_MAGIC_PACKET */
199enum gelic_lv1_wol_mp_arg {
200 GELIC_LV1_WOL_MP_DISABLE = 0,
201 GELIC_LV1_WOL_MP_ENABLE = 1,
202};
203
204/* for GELIC_LV1_WOL_{ADD,DELETE}_MATCH_ADDR */
205enum gelic_lv1_wol_match_arg {
206 GELIC_LV1_WOL_MATCH_INDIVIDUAL = 0,
207 GELIC_LV1_WOL_MATCH_ALL = 1,
208};
209
210/* status returened from GET_ETH_PORT_STATUS */
211enum gelic_lv1_ether_port_status {
212 GELIC_LV1_ETHER_LINK_UP = 0x0000000000000001L,
213 GELIC_LV1_ETHER_FULL_DUPLEX = 0x0000000000000002L,
214 GELIC_LV1_ETHER_AUTO_NEG = 0x0000000000000004L,
215
216 GELIC_LV1_ETHER_SPEED_10 = 0x0000000000000010L,
217 GELIC_LV1_ETHER_SPEED_100 = 0x0000000000000020L,
218 GELIC_LV1_ETHER_SPEED_1000 = 0x0000000000000040L,
219 GELIC_LV1_ETHER_SPEED_MASK = 0x0000000000000070L,
220};
221
222enum gelic_lv1_vlan_index {
223 /* for outgoing packets */
224 GELIC_LV1_VLAN_TX_ETHERNET_0 = 0x0000000000000002L,
225 GELIC_LV1_VLAN_TX_WIRELESS = 0x0000000000000003L,
226
227 /* for incoming packets */
228 GELIC_LV1_VLAN_RX_ETHERNET_0 = 0x0000000000000012L,
229 GELIC_LV1_VLAN_RX_WIRELESS = 0x0000000000000013L,
230};
231
232enum gelic_lv1_phy {
233 GELIC_LV1_PHY_ETHERNET_0 = 0x0000000000000002L,
234};
235
236/* size of hardware part of gelic descriptor */
237#define GELIC_DESCR_SIZE (32)
238
239enum gelic_port_type {
240 GELIC_PORT_ETHERNET_0 = 0,
241 GELIC_PORT_WIRELESS = 1,
242 GELIC_PORT_MAX
243};
244
245struct gelic_descr {
246 /* as defined by the hardware */
247 __be32 buf_addr;
248 __be32 buf_size;
249 __be32 next_descr_addr;
250 __be32 dmac_cmd_status;
251 __be32 result_size;
252 __be32 valid_size; /* all zeroes for tx */
253 __be32 data_status;
254 __be32 data_error; /* all zeroes for tx */
255
256 /* used in the driver */
257 struct sk_buff *skb;
258 dma_addr_t bus_addr;
259 struct gelic_descr *next;
260 struct gelic_descr *prev;
261} __attribute__((aligned(32)));
262
263struct gelic_descr_chain {
264 /* we walk from tail to head */
265 struct gelic_descr *head;
266 struct gelic_descr *tail;
267};
268
269struct gelic_vlan_id {
270 u16 tx;
271 u16 rx;
272};
273
274struct gelic_card {
275 struct napi_struct napi;
276 struct net_device *netdev[GELIC_PORT_MAX];
277 /*
278 * hypervisor requires irq_status should be
279 * 8 bytes aligned, but u64 member is
280 * always disposed in that manner
281 */
282 u64 irq_status;
283 u64 irq_mask;
284
285 struct ps3_system_bus_device *dev;
286 struct gelic_vlan_id vlan[GELIC_PORT_MAX];
287 int vlan_required;
288
289 struct gelic_descr_chain tx_chain;
290 struct gelic_descr_chain rx_chain;
291 /*
292 * tx_lock guards tx descriptor list and
293 * tx_dma_progress.
294 */
295 spinlock_t tx_lock;
296 int tx_dma_progress;
297
298 struct work_struct tx_timeout_task;
299 atomic_t tx_timeout_task_counter;
300 wait_queue_head_t waitq;
301
302 /* only first user should up the card */
303 struct mutex updown_lock;
304 atomic_t users;
305
306 u64 ether_port_status;
307 int link_mode;
308
309 /* original address returned by kzalloc */
310 void *unalign;
311
312 /*
313 * each netdevice has copy of irq
314 */
315 unsigned int irq;
316 struct gelic_descr *tx_top, *rx_top;
317 struct gelic_descr descr[0]; /* must be the last */
318};
319
320struct gelic_port {
321 struct gelic_card *card;
322 struct net_device *netdev;
323 enum gelic_port_type type;
324 long priv[0]; /* long for alignment */
325};
326
327static inline struct gelic_card *port_to_card(struct gelic_port *p)
328{
329 return p->card;
330}
331static inline struct net_device *port_to_netdev(struct gelic_port *p)
332{
333 return p->netdev;
334}
335static inline struct gelic_card *netdev_card(struct net_device *d)
336{
337 return ((struct gelic_port *)netdev_priv(d))->card;
338}
339static inline struct gelic_port *netdev_port(struct net_device *d)
340{
341 return (struct gelic_port *)netdev_priv(d);
342}
343static inline struct device *ctodev(struct gelic_card *card)
344{
345 return &card->dev->core;
346}
347static inline u64 bus_id(struct gelic_card *card)
348{
349 return card->dev->bus_id;
350}
351static inline u64 dev_id(struct gelic_card *card)
352{
353 return card->dev->dev_id;
354}
355
356static inline void *port_priv(struct gelic_port *port)
357{
358 return port->priv;
359}
360
361#ifdef CONFIG_PPC_EARLY_DEBUG_PS3GELIC
362void udbg_shutdown_ps3gelic(void);
363#else
364static inline void udbg_shutdown_ps3gelic(void) {}
365#endif
366
367int gelic_card_set_irq_mask(struct gelic_card *card, u64 mask);
368/* shared netdev ops */
369void gelic_card_up(struct gelic_card *card);
370void gelic_card_down(struct gelic_card *card);
371int gelic_net_open(struct net_device *netdev);
372int gelic_net_stop(struct net_device *netdev);
373int gelic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
374void gelic_net_set_multi(struct net_device *netdev);
375void gelic_net_tx_timeout(struct net_device *netdev);
376int gelic_net_change_mtu(struct net_device *netdev, int new_mtu);
377int gelic_net_setup_netdev(struct net_device *netdev, struct gelic_card *card);
378
379/* shared ethtool ops */
380void gelic_net_get_drvinfo(struct net_device *netdev,
381 struct ethtool_drvinfo *info);
382void gelic_net_poll_controller(struct net_device *netdev);
383
384#endif /* _GELIC_NET_H */
1/*
2 * PS3 Platfom gelic network driver.
3 *
4 * Copyright (C) 2007 Sony Computer Entertainment Inc.
5 * Copyright 2006, 2007 Sony Corporation.
6 *
7 * This file is based on: spider_net.h
8 *
9 * (C) Copyright IBM Corp. 2005
10 *
11 * Authors : Utz Bacher <utz.bacher@de.ibm.com>
12 * Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2, or (at your option)
17 * any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28#ifndef _GELIC_NET_H
29#define _GELIC_NET_H
30
31/* descriptors */
32#define GELIC_NET_RX_DESCRIPTORS 128 /* num of descriptors */
33#define GELIC_NET_TX_DESCRIPTORS 128 /* num of descriptors */
34
35#define GELIC_NET_MAX_MTU VLAN_ETH_FRAME_LEN
36#define GELIC_NET_MIN_MTU VLAN_ETH_ZLEN
37#define GELIC_NET_RXBUF_ALIGN 128
38#define GELIC_CARD_RX_CSUM_DEFAULT 1 /* hw chksum */
39#define GELIC_NET_WATCHDOG_TIMEOUT 5*HZ
40#define GELIC_NET_BROADCAST_ADDR 0xffffffffffffL
41
42#define GELIC_NET_MC_COUNT_MAX 32 /* multicast address list */
43
44/* virtual interrupt status register bits */
45 /* INT1 */
46#define GELIC_CARD_TX_RAM_FULL_ERR 0x0000000000000001L
47#define GELIC_CARD_RX_RAM_FULL_ERR 0x0000000000000002L
48#define GELIC_CARD_TX_SHORT_FRAME_ERR 0x0000000000000004L
49#define GELIC_CARD_TX_INVALID_DESCR_ERR 0x0000000000000008L
50#define GELIC_CARD_RX_FIFO_FULL_ERR 0x0000000000002000L
51#define GELIC_CARD_RX_DESCR_CHAIN_END 0x0000000000004000L
52#define GELIC_CARD_RX_INVALID_DESCR_ERR 0x0000000000008000L
53#define GELIC_CARD_TX_RESPONCE_ERR 0x0000000000010000L
54#define GELIC_CARD_RX_RESPONCE_ERR 0x0000000000100000L
55#define GELIC_CARD_TX_PROTECTION_ERR 0x0000000000400000L
56#define GELIC_CARD_RX_PROTECTION_ERR 0x0000000004000000L
57#define GELIC_CARD_TX_TCP_UDP_CHECKSUM_ERR 0x0000000008000000L
58#define GELIC_CARD_PORT_STATUS_CHANGED 0x0000000020000000L
59#define GELIC_CARD_WLAN_EVENT_RECEIVED 0x0000000040000000L
60#define GELIC_CARD_WLAN_COMMAND_COMPLETED 0x0000000080000000L
61 /* INT 0 */
62#define GELIC_CARD_TX_FLAGGED_DESCR 0x0004000000000000L
63#define GELIC_CARD_RX_FLAGGED_DESCR 0x0040000000000000L
64#define GELIC_CARD_TX_TRANSFER_END 0x0080000000000000L
65#define GELIC_CARD_TX_DESCR_CHAIN_END 0x0100000000000000L
66#define GELIC_CARD_NUMBER_OF_RX_FRAME 0x1000000000000000L
67#define GELIC_CARD_ONE_TIME_COUNT_TIMER 0x4000000000000000L
68#define GELIC_CARD_FREE_RUN_COUNT_TIMER 0x8000000000000000L
69
70/* initial interrupt mask */
71#define GELIC_CARD_TXINT GELIC_CARD_TX_DESCR_CHAIN_END
72
73#define GELIC_CARD_RXINT (GELIC_CARD_RX_DESCR_CHAIN_END | \
74 GELIC_CARD_NUMBER_OF_RX_FRAME)
75
76 /* RX descriptor data_status bits */
77enum gelic_descr_rx_status {
78 GELIC_DESCR_RXDMADU = 0x80000000, /* destination MAC addr unknown */
79 GELIC_DESCR_RXLSTFBF = 0x40000000, /* last frame buffer */
80 GELIC_DESCR_RXIPCHK = 0x20000000, /* IP checksum performed */
81 GELIC_DESCR_RXTCPCHK = 0x10000000, /* TCP/UDP checksup performed */
82 GELIC_DESCR_RXWTPKT = 0x00C00000, /*
83 * wakeup trigger packet
84 * 01: Magic Packet (TM)
85 * 10: ARP packet
86 * 11: Multicast MAC addr
87 */
88 GELIC_DESCR_RXVLNPKT = 0x00200000, /* VLAN packet */
89 /* bit 20..16 reserved */
90 GELIC_DESCR_RXRRECNUM = 0x0000ff00, /* reception receipt number */
91 /* bit 7..0 reserved */
92};
93
94#define GELIC_DESCR_DATA_STATUS_CHK_MASK \
95 (GELIC_DESCR_RXIPCHK | GELIC_DESCR_RXTCPCHK)
96
97 /* TX descriptor data_status bits */
98enum gelic_descr_tx_status {
99 GELIC_DESCR_TX_TAIL = 0x00000001, /* gelic treated this
100 * descriptor was end of
101 * a tx frame
102 */
103};
104
105/* RX descriptor data error bits */
106enum gelic_descr_rx_error {
107 /* bit 31 reserved */
108 GELIC_DESCR_RXALNERR = 0x40000000, /* alignement error 10/100M */
109 GELIC_DESCR_RXOVERERR = 0x20000000, /* oversize error */
110 GELIC_DESCR_RXRNTERR = 0x10000000, /* Runt error */
111 GELIC_DESCR_RXIPCHKERR = 0x08000000, /* IP checksum error */
112 GELIC_DESCR_RXTCPCHKERR = 0x04000000, /* TCP/UDP checksum error */
113 GELIC_DESCR_RXDRPPKT = 0x00100000, /* drop packet */
114 GELIC_DESCR_RXIPFMTERR = 0x00080000, /* IP packet format error */
115 /* bit 18 reserved */
116 GELIC_DESCR_RXDATAERR = 0x00020000, /* IP packet format error */
117 GELIC_DESCR_RXCALERR = 0x00010000, /* cariier extension length
118 * error */
119 GELIC_DESCR_RXCREXERR = 0x00008000, /* carrier extension error */
120 GELIC_DESCR_RXMLTCST = 0x00004000, /* multicast address frame */
121 /* bit 13..0 reserved */
122};
123#define GELIC_DESCR_DATA_ERROR_CHK_MASK \
124 (GELIC_DESCR_RXIPCHKERR | GELIC_DESCR_RXTCPCHKERR)
125
126/* DMA command and status (RX and TX)*/
127enum gelic_descr_dma_status {
128 GELIC_DESCR_DMA_COMPLETE = 0x00000000, /* used in tx */
129 GELIC_DESCR_DMA_BUFFER_FULL = 0x00000000, /* used in rx */
130 GELIC_DESCR_DMA_RESPONSE_ERROR = 0x10000000, /* used in rx, tx */
131 GELIC_DESCR_DMA_PROTECTION_ERROR = 0x20000000, /* used in rx, tx */
132 GELIC_DESCR_DMA_FRAME_END = 0x40000000, /* used in rx */
133 GELIC_DESCR_DMA_FORCE_END = 0x50000000, /* used in rx, tx */
134 GELIC_DESCR_DMA_CARDOWNED = 0xa0000000, /* used in rx, tx */
135 GELIC_DESCR_DMA_NOT_IN_USE = 0xb0000000, /* any other value */
136};
137
138#define GELIC_DESCR_DMA_STAT_MASK (0xf0000000)
139
140/* tx descriptor command and status */
141enum gelic_descr_tx_dma_status {
142 /* [19] */
143 GELIC_DESCR_TX_DMA_IKE = 0x00080000, /* IPSEC off */
144 /* [18] */
145 GELIC_DESCR_TX_DMA_FRAME_TAIL = 0x00040000, /* last descriptor of
146 * the packet
147 */
148 /* [17..16] */
149 GELIC_DESCR_TX_DMA_TCP_CHKSUM = 0x00020000, /* TCP packet */
150 GELIC_DESCR_TX_DMA_UDP_CHKSUM = 0x00030000, /* UDP packet */
151 GELIC_DESCR_TX_DMA_NO_CHKSUM = 0x00000000, /* no checksum */
152
153 /* [1] */
154 GELIC_DESCR_TX_DMA_CHAIN_END = 0x00000002, /* DMA terminated
155 * due to chain end
156 */
157};
158
159#define GELIC_DESCR_DMA_CMD_NO_CHKSUM \
160 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
161 GELIC_DESCR_TX_DMA_NO_CHKSUM)
162
163#define GELIC_DESCR_DMA_CMD_TCP_CHKSUM \
164 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
165 GELIC_DESCR_TX_DMA_TCP_CHKSUM)
166
167#define GELIC_DESCR_DMA_CMD_UDP_CHKSUM \
168 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
169 GELIC_DESCR_TX_DMA_UDP_CHKSUM)
170
171enum gelic_descr_rx_dma_status {
172 /* [ 1 ] */
173 GELIC_DESCR_RX_DMA_CHAIN_END = 0x00000002, /* DMA terminated
174 * due to chain end
175 */
176};
177
178/* for lv1_net_control */
179enum gelic_lv1_net_control_code {
180 GELIC_LV1_GET_MAC_ADDRESS = 1,
181 GELIC_LV1_GET_ETH_PORT_STATUS = 2,
182 GELIC_LV1_SET_NEGOTIATION_MODE = 3,
183 GELIC_LV1_GET_VLAN_ID = 4,
184 GELIC_LV1_SET_WOL = 5,
185 GELIC_LV1_GET_CHANNEL = 6,
186 GELIC_LV1_POST_WLAN_CMD = 9,
187 GELIC_LV1_GET_WLAN_CMD_RESULT = 10,
188 GELIC_LV1_GET_WLAN_EVENT = 11,
189};
190
191/* for GELIC_LV1_SET_WOL */
192enum gelic_lv1_wol_command {
193 GELIC_LV1_WOL_MAGIC_PACKET = 1,
194 GELIC_LV1_WOL_ADD_MATCH_ADDR = 6,
195 GELIC_LV1_WOL_DELETE_MATCH_ADDR = 7,
196};
197
198/* for GELIC_LV1_WOL_MAGIC_PACKET */
199enum gelic_lv1_wol_mp_arg {
200 GELIC_LV1_WOL_MP_DISABLE = 0,
201 GELIC_LV1_WOL_MP_ENABLE = 1,
202};
203
204/* for GELIC_LV1_WOL_{ADD,DELETE}_MATCH_ADDR */
205enum gelic_lv1_wol_match_arg {
206 GELIC_LV1_WOL_MATCH_INDIVIDUAL = 0,
207 GELIC_LV1_WOL_MATCH_ALL = 1,
208};
209
210/* status returened from GET_ETH_PORT_STATUS */
211enum gelic_lv1_ether_port_status {
212 GELIC_LV1_ETHER_LINK_UP = 0x0000000000000001L,
213 GELIC_LV1_ETHER_FULL_DUPLEX = 0x0000000000000002L,
214 GELIC_LV1_ETHER_AUTO_NEG = 0x0000000000000004L,
215
216 GELIC_LV1_ETHER_SPEED_10 = 0x0000000000000010L,
217 GELIC_LV1_ETHER_SPEED_100 = 0x0000000000000020L,
218 GELIC_LV1_ETHER_SPEED_1000 = 0x0000000000000040L,
219 GELIC_LV1_ETHER_SPEED_MASK = 0x0000000000000070L,
220};
221
222enum gelic_lv1_vlan_index {
223 /* for outgoing packets */
224 GELIC_LV1_VLAN_TX_ETHERNET_0 = 0x0000000000000002L,
225 GELIC_LV1_VLAN_TX_WIRELESS = 0x0000000000000003L,
226
227 /* for incoming packets */
228 GELIC_LV1_VLAN_RX_ETHERNET_0 = 0x0000000000000012L,
229 GELIC_LV1_VLAN_RX_WIRELESS = 0x0000000000000013L,
230};
231
232enum gelic_lv1_phy {
233 GELIC_LV1_PHY_ETHERNET_0 = 0x0000000000000002L,
234};
235
236/* size of hardware part of gelic descriptor */
237#define GELIC_DESCR_SIZE (32)
238
239enum gelic_port_type {
240 GELIC_PORT_ETHERNET_0 = 0,
241 GELIC_PORT_WIRELESS = 1,
242 GELIC_PORT_MAX
243};
244
245struct gelic_descr {
246 /* as defined by the hardware */
247 __be32 buf_addr;
248 __be32 buf_size;
249 __be32 next_descr_addr;
250 __be32 dmac_cmd_status;
251 __be32 result_size;
252 __be32 valid_size; /* all zeroes for tx */
253 __be32 data_status;
254 __be32 data_error; /* all zeroes for tx */
255
256 /* used in the driver */
257 struct sk_buff *skb;
258 dma_addr_t bus_addr;
259 struct gelic_descr *next;
260 struct gelic_descr *prev;
261} __attribute__((aligned(32)));
262
263struct gelic_descr_chain {
264 /* we walk from tail to head */
265 struct gelic_descr *head;
266 struct gelic_descr *tail;
267};
268
269struct gelic_vlan_id {
270 u16 tx;
271 u16 rx;
272};
273
274struct gelic_card {
275 struct napi_struct napi;
276 struct net_device *netdev[GELIC_PORT_MAX];
277 /*
278 * hypervisor requires irq_status should be
279 * 8 bytes aligned, but u64 member is
280 * always disposed in that manner
281 */
282 u64 irq_status;
283 u64 irq_mask;
284
285 struct ps3_system_bus_device *dev;
286 struct gelic_vlan_id vlan[GELIC_PORT_MAX];
287 int vlan_required;
288
289 struct gelic_descr_chain tx_chain;
290 struct gelic_descr_chain rx_chain;
291 /*
292 * tx_lock guards tx descriptor list and
293 * tx_dma_progress.
294 */
295 spinlock_t tx_lock;
296 int tx_dma_progress;
297
298 struct work_struct tx_timeout_task;
299 atomic_t tx_timeout_task_counter;
300 wait_queue_head_t waitq;
301
302 /* only first user should up the card */
303 struct mutex updown_lock;
304 atomic_t users;
305
306 u64 ether_port_status;
307 int link_mode;
308
309 /* original address returned by kzalloc */
310 void *unalign;
311
312 /*
313 * each netdevice has copy of irq
314 */
315 unsigned int irq;
316 struct gelic_descr *tx_top, *rx_top;
317 struct gelic_descr descr[0]; /* must be the last */
318};
319
320struct gelic_port {
321 struct gelic_card *card;
322 struct net_device *netdev;
323 enum gelic_port_type type;
324 long priv[0]; /* long for alignment */
325};
326
327static inline struct gelic_card *port_to_card(struct gelic_port *p)
328{
329 return p->card;
330}
331static inline struct net_device *port_to_netdev(struct gelic_port *p)
332{
333 return p->netdev;
334}
335static inline struct gelic_card *netdev_card(struct net_device *d)
336{
337 return ((struct gelic_port *)netdev_priv(d))->card;
338}
339static inline struct gelic_port *netdev_port(struct net_device *d)
340{
341 return (struct gelic_port *)netdev_priv(d);
342}
343static inline struct device *ctodev(struct gelic_card *card)
344{
345 return &card->dev->core;
346}
347static inline u64 bus_id(struct gelic_card *card)
348{
349 return card->dev->bus_id;
350}
351static inline u64 dev_id(struct gelic_card *card)
352{
353 return card->dev->dev_id;
354}
355
356static inline void *port_priv(struct gelic_port *port)
357{
358 return port->priv;
359}
360
361#ifdef CONFIG_PPC_EARLY_DEBUG_PS3GELIC
362void udbg_shutdown_ps3gelic(void);
363#else
364static inline void udbg_shutdown_ps3gelic(void) {}
365#endif
366
367int gelic_card_set_irq_mask(struct gelic_card *card, u64 mask);
368/* shared netdev ops */
369void gelic_card_up(struct gelic_card *card);
370void gelic_card_down(struct gelic_card *card);
371int gelic_net_open(struct net_device *netdev);
372int gelic_net_stop(struct net_device *netdev);
373int gelic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
374void gelic_net_set_multi(struct net_device *netdev);
375void gelic_net_tx_timeout(struct net_device *netdev);
376int gelic_net_setup_netdev(struct net_device *netdev, struct gelic_card *card);
377
378/* shared ethtool ops */
379void gelic_net_get_drvinfo(struct net_device *netdev,
380 struct ethtool_drvinfo *info);
381void gelic_net_poll_controller(struct net_device *netdev);
382
383#endif /* _GELIC_NET_H */