1/*
  2 * Broadcom Starfighter2 private context
  3 *
  4 * Copyright (C) 2014, Broadcom Corporation
  5 *
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License as published by
  8 * the Free Software Foundation; either version 2 of the License, or
  9 * (at your option) any later version.
 10 */
 11
 12#ifndef __BCM_SF2_H
 13#define __BCM_SF2_H
 14
 15#include <linux/platform_device.h>
 16#include <linux/kernel.h>
 17#include <linux/io.h>
 18#include <linux/spinlock.h>
 19#include <linux/mutex.h>
 20#include <linux/mii.h>
 21#include <linux/ethtool.h>
 22#include <linux/types.h>
 23#include <linux/bitops.h>
 24#include <linux/if_vlan.h>
 25
 26#include <net/dsa.h>
 27
 28#include "bcm_sf2_regs.h"
 29#include "b53/b53_priv.h"
 30
 31struct bcm_sf2_hw_params {
 32	u16	top_rev;
 33	u16	core_rev;
 34	u16	gphy_rev;
 35	u32	num_gphy;
 36	u8	num_acb_queue;
 37	u8	num_rgmii;
 38	u8	num_ports;
 39	u8	fcb_pause_override:1;
 40	u8	acb_packets_inflight:1;
 41};
 42
 43#define BCM_SF2_REGS_NAME {\
 44	"core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \
 45}
 46
 47#define BCM_SF2_REGS_NUM	6
 48
 49struct bcm_sf2_port_status {
 50	unsigned int link;
 51
 52	struct ethtool_eee eee;
 53};
 54
 55struct bcm_sf2_priv {
 56	/* Base registers, keep those in order with BCM_SF2_REGS_NAME */
 57	void __iomem			*core;
 58	void __iomem			*reg;
 59	void __iomem			*intrl2_0;
 60	void __iomem			*intrl2_1;
 61	void __iomem			*fcb;
 62	void __iomem			*acb;
 63
 64	/* spinlock protecting access to the indirect registers */
 65	spinlock_t			indir_lock;
 66
 67	int				irq0;
 68	int				irq1;
 69	u32				irq0_stat;
 70	u32				irq0_mask;
 71	u32				irq1_stat;
 72	u32				irq1_mask;
 73
 74	/* Backing b53_device */
 75	struct b53_device		*dev;
 76
 77	/* Mutex protecting access to the MIB counters */
 78	struct mutex			stats_mutex;
 79
 80	struct bcm_sf2_hw_params	hw_params;
 81
 82	struct bcm_sf2_port_status	port_sts[DSA_MAX_PORTS];
 83
 84	/* Mask of ports enabled for Wake-on-LAN */
 85	u32				wol_ports_mask;
 86
 87	/* MoCA port location */
 88	int				moca_port;
 89
 90	/* Bitmask of ports having an integrated PHY */
 91	unsigned int			int_phy_mask;
 92
 93	/* Master and slave MDIO bus controller */
 94	unsigned int			indir_phy_mask;
 95	struct device_node		*master_mii_dn;
 96	struct mii_bus			*slave_mii_bus;
 97	struct mii_bus			*master_mii_bus;
 98};
 99
100static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds)
101{
102	struct b53_device *dev = ds->priv;
103
104	return dev->priv;
105}
106
107#define SF2_IO_MACRO(name) \
108static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off)	\
109{									\
110	return __raw_readl(priv->name + off);				\
111}									\
112static inline void name##_writel(struct bcm_sf2_priv *priv,		\
113				  u32 val, u32 off)			\
114{									\
115	__raw_writel(val, priv->name + off);				\
116}									\
117
118/* Accesses to 64-bits register requires us to latch the hi/lo pairs
119 * using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
120 * spinlock is automatically grabbed and released to provide relative
121 * atomiticy with latched reads/writes.
122 */
123#define SF2_IO64_MACRO(name) \
124static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off)	\
125{									\
126	u32 indir, dir;							\
127	spin_lock(&priv->indir_lock);					\
128	dir = __raw_readl(priv->name + off);				\
129	indir = reg_readl(priv, REG_DIR_DATA_READ);			\
130	spin_unlock(&priv->indir_lock);					\
131	return (u64)indir << 32 | dir;					\
132}									\
133static inline void name##_writeq(struct bcm_sf2_priv *priv, u64 val,	\
134							u32 off)	\
135{									\
136	spin_lock(&priv->indir_lock);					\
137	reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE);	\
138	__raw_writel(lower_32_bits(val), priv->name + off);		\
139	spin_unlock(&priv->indir_lock);					\
140}
141
142#define SWITCH_INTR_L2(which)						\
143static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
144						u32 mask)		\
145{									\
146	priv->irq##which##_mask &= ~(mask);				\
147	intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR);	\
148}									\
149static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
150						u32 mask)		\
151{									\
152	intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET);	\
153	priv->irq##which##_mask |= (mask);				\
154}									\
155
156SF2_IO_MACRO(core);
157SF2_IO_MACRO(reg);
158SF2_IO64_MACRO(core);
159SF2_IO_MACRO(intrl2_0);
160SF2_IO_MACRO(intrl2_1);
161SF2_IO_MACRO(fcb);
162SF2_IO_MACRO(acb);
163
164SWITCH_INTR_L2(0);
165SWITCH_INTR_L2(1);
166
167#endif /* __BCM_SF2_H */