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1/*
2 * Marvell Armada 370 and Armada XP SoC IRQ handling
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/irqchip/chained_irq.h>
22#include <linux/io.h>
23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25#include <linux/of_pci.h>
26#include <linux/irqdomain.h>
27#include <linux/slab.h>
28#include <linux/msi.h>
29#include <asm/mach/arch.h>
30#include <asm/exception.h>
31#include <asm/smp_plat.h>
32#include <asm/mach/irq.h>
33
34#include "irqchip.h"
35
36/* Interrupt Controller Registers Map */
37#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
38#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
39
40#define ARMADA_370_XP_INT_CONTROL (0x00)
41#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
42#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
43#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
44#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
45
46#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
47#define ARMADA_375_PPI_CAUSE (0x10)
48
49#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
50#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
51#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
52
53#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
54
55#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
56
57#define IPI_DOORBELL_START (0)
58#define IPI_DOORBELL_END (8)
59#define IPI_DOORBELL_MASK 0xFF
60#define PCI_MSI_DOORBELL_START (16)
61#define PCI_MSI_DOORBELL_NR (16)
62#define PCI_MSI_DOORBELL_END (32)
63#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
64
65static void __iomem *per_cpu_int_base;
66static void __iomem *main_int_base;
67static struct irq_domain *armada_370_xp_mpic_domain;
68#ifdef CONFIG_PCI_MSI
69static struct irq_domain *armada_370_xp_msi_domain;
70static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
71static DEFINE_MUTEX(msi_used_lock);
72static phys_addr_t msi_doorbell_addr;
73#endif
74
75/*
76 * In SMP mode:
77 * For shared global interrupts, mask/unmask global enable bit
78 * For CPU interrupts, mask/unmask the calling CPU's bit
79 */
80static void armada_370_xp_irq_mask(struct irq_data *d)
81{
82 irq_hw_number_t hwirq = irqd_to_hwirq(d);
83
84 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
85 writel(hwirq, main_int_base +
86 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
87 else
88 writel(hwirq, per_cpu_int_base +
89 ARMADA_370_XP_INT_SET_MASK_OFFS);
90}
91
92static void armada_370_xp_irq_unmask(struct irq_data *d)
93{
94 irq_hw_number_t hwirq = irqd_to_hwirq(d);
95
96 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
97 writel(hwirq, main_int_base +
98 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
99 else
100 writel(hwirq, per_cpu_int_base +
101 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
102}
103
104#ifdef CONFIG_PCI_MSI
105
106static int armada_370_xp_alloc_msi(void)
107{
108 int hwirq;
109
110 mutex_lock(&msi_used_lock);
111 hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
112 if (hwirq >= PCI_MSI_DOORBELL_NR)
113 hwirq = -ENOSPC;
114 else
115 set_bit(hwirq, msi_used);
116 mutex_unlock(&msi_used_lock);
117
118 return hwirq;
119}
120
121static void armada_370_xp_free_msi(int hwirq)
122{
123 mutex_lock(&msi_used_lock);
124 if (!test_bit(hwirq, msi_used))
125 pr_err("trying to free unused MSI#%d\n", hwirq);
126 else
127 clear_bit(hwirq, msi_used);
128 mutex_unlock(&msi_used_lock);
129}
130
131static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,
132 struct pci_dev *pdev,
133 struct msi_desc *desc)
134{
135 struct msi_msg msg;
136 int virq, hwirq;
137
138 hwirq = armada_370_xp_alloc_msi();
139 if (hwirq < 0)
140 return hwirq;
141
142 virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
143 if (!virq) {
144 armada_370_xp_free_msi(hwirq);
145 return -EINVAL;
146 }
147
148 irq_set_msi_desc(virq, desc);
149
150 msg.address_lo = msi_doorbell_addr;
151 msg.address_hi = 0;
152 msg.data = 0xf00 | (hwirq + 16);
153
154 write_msi_msg(virq, &msg);
155 return 0;
156}
157
158static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,
159 unsigned int irq)
160{
161 struct irq_data *d = irq_get_irq_data(irq);
162 unsigned long hwirq = d->hwirq;
163
164 irq_dispose_mapping(irq);
165 armada_370_xp_free_msi(hwirq);
166}
167
168static int armada_370_xp_check_msi_device(struct msi_chip *chip, struct pci_dev *dev,
169 int nvec, int type)
170{
171 /* We support MSI, but not MSI-X */
172 if (type == PCI_CAP_ID_MSI)
173 return 0;
174 return -EINVAL;
175}
176
177static struct irq_chip armada_370_xp_msi_irq_chip = {
178 .name = "armada_370_xp_msi_irq",
179 .irq_enable = unmask_msi_irq,
180 .irq_disable = mask_msi_irq,
181 .irq_mask = mask_msi_irq,
182 .irq_unmask = unmask_msi_irq,
183};
184
185static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
186 irq_hw_number_t hw)
187{
188 irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
189 handle_simple_irq);
190 set_irq_flags(virq, IRQF_VALID);
191
192 return 0;
193}
194
195static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
196 .map = armada_370_xp_msi_map,
197};
198
199static int armada_370_xp_msi_init(struct device_node *node,
200 phys_addr_t main_int_phys_base)
201{
202 struct msi_chip *msi_chip;
203 u32 reg;
204 int ret;
205
206 msi_doorbell_addr = main_int_phys_base +
207 ARMADA_370_XP_SW_TRIG_INT_OFFS;
208
209 msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
210 if (!msi_chip)
211 return -ENOMEM;
212
213 msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
214 msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
215 msi_chip->check_device = armada_370_xp_check_msi_device;
216 msi_chip->of_node = node;
217
218 armada_370_xp_msi_domain =
219 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
220 &armada_370_xp_msi_irq_ops,
221 NULL);
222 if (!armada_370_xp_msi_domain) {
223 kfree(msi_chip);
224 return -ENOMEM;
225 }
226
227 ret = of_pci_msi_chip_add(msi_chip);
228 if (ret < 0) {
229 irq_domain_remove(armada_370_xp_msi_domain);
230 kfree(msi_chip);
231 return ret;
232 }
233
234 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
235 | PCI_MSI_DOORBELL_MASK;
236
237 writel(reg, per_cpu_int_base +
238 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
239
240 /* Unmask IPI interrupt */
241 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
242
243 return 0;
244}
245#else
246static inline int armada_370_xp_msi_init(struct device_node *node,
247 phys_addr_t main_int_phys_base)
248{
249 return 0;
250}
251#endif
252
253#ifdef CONFIG_SMP
254static DEFINE_RAW_SPINLOCK(irq_controller_lock);
255
256static int armada_xp_set_affinity(struct irq_data *d,
257 const struct cpumask *mask_val, bool force)
258{
259 irq_hw_number_t hwirq = irqd_to_hwirq(d);
260 unsigned long reg, mask;
261 int cpu;
262
263 /* Select a single core from the affinity mask which is online */
264 cpu = cpumask_any_and(mask_val, cpu_online_mask);
265 mask = 1UL << cpu_logical_map(cpu);
266
267 raw_spin_lock(&irq_controller_lock);
268 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
269 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
270 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
271 raw_spin_unlock(&irq_controller_lock);
272
273 return 0;
274}
275#endif
276
277static struct irq_chip armada_370_xp_irq_chip = {
278 .name = "armada_370_xp_irq",
279 .irq_mask = armada_370_xp_irq_mask,
280 .irq_mask_ack = armada_370_xp_irq_mask,
281 .irq_unmask = armada_370_xp_irq_unmask,
282#ifdef CONFIG_SMP
283 .irq_set_affinity = armada_xp_set_affinity,
284#endif
285};
286
287static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
288 unsigned int virq, irq_hw_number_t hw)
289{
290 armada_370_xp_irq_mask(irq_get_irq_data(virq));
291 if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
292 writel(hw, per_cpu_int_base +
293 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
294 else
295 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
296 irq_set_status_flags(virq, IRQ_LEVEL);
297
298 if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
299 irq_set_percpu_devid(virq);
300 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
301 handle_percpu_devid_irq);
302
303 } else {
304 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
305 handle_level_irq);
306 }
307 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
308
309 return 0;
310}
311
312#ifdef CONFIG_SMP
313void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq)
314{
315 int cpu;
316 unsigned long map = 0;
317
318 /* Convert our logical CPU mask into a physical one. */
319 for_each_cpu(cpu, mask)
320 map |= 1 << cpu_logical_map(cpu);
321
322 /*
323 * Ensure that stores to Normal memory are visible to the
324 * other CPUs before issuing the IPI.
325 */
326 dsb();
327
328 /* submit softirq */
329 writel((map << 8) | irq, main_int_base +
330 ARMADA_370_XP_SW_TRIG_INT_OFFS);
331}
332
333void armada_xp_mpic_smp_cpu_init(void)
334{
335 /* Clear pending IPIs */
336 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
337
338 /* Enable first 8 IPIs */
339 writel(IPI_DOORBELL_MASK, per_cpu_int_base +
340 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
341
342 /* Unmask IPI interrupt */
343 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
344}
345#endif /* CONFIG_SMP */
346
347static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
348 .map = armada_370_xp_mpic_irq_map,
349 .xlate = irq_domain_xlate_onecell,
350};
351
352#ifdef CONFIG_PCI_MSI
353static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
354{
355 u32 msimask, msinr;
356
357 msimask = readl_relaxed(per_cpu_int_base +
358 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
359 & PCI_MSI_DOORBELL_MASK;
360
361 writel(~msimask, per_cpu_int_base +
362 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
363
364 for (msinr = PCI_MSI_DOORBELL_START;
365 msinr < PCI_MSI_DOORBELL_END; msinr++) {
366 int irq;
367
368 if (!(msimask & BIT(msinr)))
369 continue;
370
371 irq = irq_find_mapping(armada_370_xp_msi_domain,
372 msinr - 16);
373
374 if (is_chained)
375 generic_handle_irq(irq);
376 else
377 handle_IRQ(irq, regs);
378 }
379}
380#else
381static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
382#endif
383
384static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
385 struct irq_desc *desc)
386{
387 struct irq_chip *chip = irq_get_chip(irq);
388 unsigned long irqmap, irqn;
389 unsigned int cascade_irq;
390
391 chained_irq_enter(chip, desc);
392
393 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
394
395 if (irqmap & BIT(0)) {
396 armada_370_xp_handle_msi_irq(NULL, true);
397 irqmap &= ~BIT(0);
398 }
399
400 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
401 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
402 generic_handle_irq(cascade_irq);
403 }
404
405 chained_irq_exit(chip, desc);
406}
407
408static void __exception_irq_entry
409armada_370_xp_handle_irq(struct pt_regs *regs)
410{
411 u32 irqstat, irqnr;
412
413 do {
414 irqstat = readl_relaxed(per_cpu_int_base +
415 ARMADA_370_XP_CPU_INTACK_OFFS);
416 irqnr = irqstat & 0x3FF;
417
418 if (irqnr > 1022)
419 break;
420
421 if (irqnr > 1) {
422 irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
423 irqnr);
424 handle_IRQ(irqnr, regs);
425 continue;
426 }
427
428 /* MSI handling */
429 if (irqnr == 1)
430 armada_370_xp_handle_msi_irq(regs, false);
431
432#ifdef CONFIG_SMP
433 /* IPI Handling */
434 if (irqnr == 0) {
435 u32 ipimask, ipinr;
436
437 ipimask = readl_relaxed(per_cpu_int_base +
438 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
439 & IPI_DOORBELL_MASK;
440
441 writel(~ipimask, per_cpu_int_base +
442 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
443
444 /* Handle all pending doorbells */
445 for (ipinr = IPI_DOORBELL_START;
446 ipinr < IPI_DOORBELL_END; ipinr++) {
447 if (ipimask & (0x1 << ipinr))
448 handle_IPI(ipinr, regs);
449 }
450 continue;
451 }
452#endif
453
454 } while (1);
455}
456
457static int __init armada_370_xp_mpic_of_init(struct device_node *node,
458 struct device_node *parent)
459{
460 struct resource main_int_res, per_cpu_int_res;
461 int parent_irq;
462 u32 control;
463
464 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
465 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
466
467 BUG_ON(!request_mem_region(main_int_res.start,
468 resource_size(&main_int_res),
469 node->full_name));
470 BUG_ON(!request_mem_region(per_cpu_int_res.start,
471 resource_size(&per_cpu_int_res),
472 node->full_name));
473
474 main_int_base = ioremap(main_int_res.start,
475 resource_size(&main_int_res));
476 BUG_ON(!main_int_base);
477
478 per_cpu_int_base = ioremap(per_cpu_int_res.start,
479 resource_size(&per_cpu_int_res));
480 BUG_ON(!per_cpu_int_base);
481
482 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
483
484 armada_370_xp_mpic_domain =
485 irq_domain_add_linear(node, (control >> 2) & 0x3ff,
486 &armada_370_xp_mpic_irq_ops, NULL);
487
488 BUG_ON(!armada_370_xp_mpic_domain);
489
490#ifdef CONFIG_SMP
491 armada_xp_mpic_smp_cpu_init();
492#endif
493
494 armada_370_xp_msi_init(node, main_int_res.start);
495
496 parent_irq = irq_of_parse_and_map(node, 0);
497 if (parent_irq <= 0) {
498 irq_set_default_host(armada_370_xp_mpic_domain);
499 set_handle_irq(armada_370_xp_handle_irq);
500 } else {
501 irq_set_chained_handler(parent_irq,
502 armada_370_xp_mpic_handle_cascade_irq);
503 }
504
505 return 0;
506}
507
508IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
1/*
2 * Marvell Armada 370 and Armada XP SoC IRQ handling
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/irqchip.h>
22#include <linux/irqchip/chained_irq.h>
23#include <linux/cpu.h>
24#include <linux/io.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/of_pci.h>
28#include <linux/irqdomain.h>
29#include <linux/slab.h>
30#include <linux/syscore_ops.h>
31#include <linux/msi.h>
32#include <asm/mach/arch.h>
33#include <asm/exception.h>
34#include <asm/smp_plat.h>
35#include <asm/mach/irq.h>
36
37/* Interrupt Controller Registers Map */
38#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
39#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
40#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
41#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
42
43#define ARMADA_370_XP_INT_CONTROL (0x00)
44#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
45#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
46#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
47#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
48#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
49
50#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
51#define ARMADA_375_PPI_CAUSE (0x10)
52
53#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
54#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
55#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
56
57#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
58
59#define IPI_DOORBELL_START (0)
60#define IPI_DOORBELL_END (8)
61#define IPI_DOORBELL_MASK 0xFF
62#define PCI_MSI_DOORBELL_START (16)
63#define PCI_MSI_DOORBELL_NR (16)
64#define PCI_MSI_DOORBELL_END (32)
65#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
66
67static void __iomem *per_cpu_int_base;
68static void __iomem *main_int_base;
69static struct irq_domain *armada_370_xp_mpic_domain;
70static u32 doorbell_mask_reg;
71static int parent_irq;
72#ifdef CONFIG_PCI_MSI
73static struct irq_domain *armada_370_xp_msi_domain;
74static struct irq_domain *armada_370_xp_msi_inner_domain;
75static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
76static DEFINE_MUTEX(msi_used_lock);
77static phys_addr_t msi_doorbell_addr;
78#endif
79
80static inline bool is_percpu_irq(irq_hw_number_t irq)
81{
82 if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
83 return true;
84
85 return false;
86}
87
88/*
89 * In SMP mode:
90 * For shared global interrupts, mask/unmask global enable bit
91 * For CPU interrupts, mask/unmask the calling CPU's bit
92 */
93static void armada_370_xp_irq_mask(struct irq_data *d)
94{
95 irq_hw_number_t hwirq = irqd_to_hwirq(d);
96
97 if (!is_percpu_irq(hwirq))
98 writel(hwirq, main_int_base +
99 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
100 else
101 writel(hwirq, per_cpu_int_base +
102 ARMADA_370_XP_INT_SET_MASK_OFFS);
103}
104
105static void armada_370_xp_irq_unmask(struct irq_data *d)
106{
107 irq_hw_number_t hwirq = irqd_to_hwirq(d);
108
109 if (!is_percpu_irq(hwirq))
110 writel(hwirq, main_int_base +
111 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
112 else
113 writel(hwirq, per_cpu_int_base +
114 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
115}
116
117#ifdef CONFIG_PCI_MSI
118
119static struct irq_chip armada_370_xp_msi_irq_chip = {
120 .name = "MPIC MSI",
121 .irq_mask = pci_msi_mask_irq,
122 .irq_unmask = pci_msi_unmask_irq,
123};
124
125static struct msi_domain_info armada_370_xp_msi_domain_info = {
126 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
127 MSI_FLAG_MULTI_PCI_MSI),
128 .chip = &armada_370_xp_msi_irq_chip,
129};
130
131static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
132{
133 msg->address_lo = lower_32_bits(msi_doorbell_addr);
134 msg->address_hi = upper_32_bits(msi_doorbell_addr);
135 msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START);
136}
137
138static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
139 const struct cpumask *mask, bool force)
140{
141 return -EINVAL;
142}
143
144static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
145 .name = "MPIC MSI",
146 .irq_compose_msi_msg = armada_370_xp_compose_msi_msg,
147 .irq_set_affinity = armada_370_xp_msi_set_affinity,
148};
149
150static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
151 unsigned int nr_irqs, void *args)
152{
153 int hwirq, i;
154
155 mutex_lock(&msi_used_lock);
156
157 hwirq = bitmap_find_next_zero_area(msi_used, PCI_MSI_DOORBELL_NR,
158 0, nr_irqs, 0);
159 if (hwirq >= PCI_MSI_DOORBELL_NR) {
160 mutex_unlock(&msi_used_lock);
161 return -ENOSPC;
162 }
163
164 bitmap_set(msi_used, hwirq, nr_irqs);
165 mutex_unlock(&msi_used_lock);
166
167 for (i = 0; i < nr_irqs; i++) {
168 irq_domain_set_info(domain, virq + i, hwirq + i,
169 &armada_370_xp_msi_bottom_irq_chip,
170 domain->host_data, handle_simple_irq,
171 NULL, NULL);
172 }
173
174 return hwirq;
175}
176
177static void armada_370_xp_msi_free(struct irq_domain *domain,
178 unsigned int virq, unsigned int nr_irqs)
179{
180 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
181
182 mutex_lock(&msi_used_lock);
183 bitmap_clear(msi_used, d->hwirq, nr_irqs);
184 mutex_unlock(&msi_used_lock);
185}
186
187static const struct irq_domain_ops armada_370_xp_msi_domain_ops = {
188 .alloc = armada_370_xp_msi_alloc,
189 .free = armada_370_xp_msi_free,
190};
191
192static int armada_370_xp_msi_init(struct device_node *node,
193 phys_addr_t main_int_phys_base)
194{
195 u32 reg;
196
197 msi_doorbell_addr = main_int_phys_base +
198 ARMADA_370_XP_SW_TRIG_INT_OFFS;
199
200 armada_370_xp_msi_inner_domain =
201 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
202 &armada_370_xp_msi_domain_ops, NULL);
203 if (!armada_370_xp_msi_inner_domain)
204 return -ENOMEM;
205
206 armada_370_xp_msi_domain =
207 pci_msi_create_irq_domain(of_node_to_fwnode(node),
208 &armada_370_xp_msi_domain_info,
209 armada_370_xp_msi_inner_domain);
210 if (!armada_370_xp_msi_domain) {
211 irq_domain_remove(armada_370_xp_msi_inner_domain);
212 return -ENOMEM;
213 }
214
215 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
216 | PCI_MSI_DOORBELL_MASK;
217
218 writel(reg, per_cpu_int_base +
219 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
220
221 /* Unmask IPI interrupt */
222 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
223
224 return 0;
225}
226#else
227static inline int armada_370_xp_msi_init(struct device_node *node,
228 phys_addr_t main_int_phys_base)
229{
230 return 0;
231}
232#endif
233
234#ifdef CONFIG_SMP
235static DEFINE_RAW_SPINLOCK(irq_controller_lock);
236
237static int armada_xp_set_affinity(struct irq_data *d,
238 const struct cpumask *mask_val, bool force)
239{
240 irq_hw_number_t hwirq = irqd_to_hwirq(d);
241 unsigned long reg, mask;
242 int cpu;
243
244 /* Select a single core from the affinity mask which is online */
245 cpu = cpumask_any_and(mask_val, cpu_online_mask);
246 mask = 1UL << cpu_logical_map(cpu);
247
248 raw_spin_lock(&irq_controller_lock);
249 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
250 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
251 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
252 raw_spin_unlock(&irq_controller_lock);
253
254 return IRQ_SET_MASK_OK;
255}
256#endif
257
258static struct irq_chip armada_370_xp_irq_chip = {
259 .name = "MPIC",
260 .irq_mask = armada_370_xp_irq_mask,
261 .irq_mask_ack = armada_370_xp_irq_mask,
262 .irq_unmask = armada_370_xp_irq_unmask,
263#ifdef CONFIG_SMP
264 .irq_set_affinity = armada_xp_set_affinity,
265#endif
266 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
267};
268
269static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
270 unsigned int virq, irq_hw_number_t hw)
271{
272 armada_370_xp_irq_mask(irq_get_irq_data(virq));
273 if (!is_percpu_irq(hw))
274 writel(hw, per_cpu_int_base +
275 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
276 else
277 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
278 irq_set_status_flags(virq, IRQ_LEVEL);
279
280 if (is_percpu_irq(hw)) {
281 irq_set_percpu_devid(virq);
282 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
283 handle_percpu_devid_irq);
284
285 } else {
286 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
287 handle_level_irq);
288 }
289 irq_set_probe(virq);
290 irq_clear_status_flags(virq, IRQ_NOAUTOEN);
291
292 return 0;
293}
294
295static void armada_xp_mpic_smp_cpu_init(void)
296{
297 u32 control;
298 int nr_irqs, i;
299
300 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
301 nr_irqs = (control >> 2) & 0x3ff;
302
303 for (i = 0; i < nr_irqs; i++)
304 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
305
306 /* Clear pending IPIs */
307 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
308
309 /* Enable first 8 IPIs */
310 writel(IPI_DOORBELL_MASK, per_cpu_int_base +
311 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
312
313 /* Unmask IPI interrupt */
314 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
315}
316
317static void armada_xp_mpic_perf_init(void)
318{
319 unsigned long cpuid = cpu_logical_map(smp_processor_id());
320
321 /* Enable Performance Counter Overflow interrupts */
322 writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
323 per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
324}
325
326#ifdef CONFIG_SMP
327static void armada_mpic_send_doorbell(const struct cpumask *mask,
328 unsigned int irq)
329{
330 int cpu;
331 unsigned long map = 0;
332
333 /* Convert our logical CPU mask into a physical one. */
334 for_each_cpu(cpu, mask)
335 map |= 1 << cpu_logical_map(cpu);
336
337 /*
338 * Ensure that stores to Normal memory are visible to the
339 * other CPUs before issuing the IPI.
340 */
341 dsb();
342
343 /* submit softirq */
344 writel((map << 8) | irq, main_int_base +
345 ARMADA_370_XP_SW_TRIG_INT_OFFS);
346}
347
348static int armada_xp_mpic_starting_cpu(unsigned int cpu)
349{
350 armada_xp_mpic_perf_init();
351 armada_xp_mpic_smp_cpu_init();
352 return 0;
353}
354
355static int mpic_cascaded_starting_cpu(unsigned int cpu)
356{
357 armada_xp_mpic_perf_init();
358 enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
359 return 0;
360}
361#endif
362
363static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
364 .map = armada_370_xp_mpic_irq_map,
365 .xlate = irq_domain_xlate_onecell,
366};
367
368#ifdef CONFIG_PCI_MSI
369static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
370{
371 u32 msimask, msinr;
372
373 msimask = readl_relaxed(per_cpu_int_base +
374 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
375 & PCI_MSI_DOORBELL_MASK;
376
377 writel(~msimask, per_cpu_int_base +
378 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
379
380 for (msinr = PCI_MSI_DOORBELL_START;
381 msinr < PCI_MSI_DOORBELL_END; msinr++) {
382 int irq;
383
384 if (!(msimask & BIT(msinr)))
385 continue;
386
387 if (is_chained) {
388 irq = irq_find_mapping(armada_370_xp_msi_inner_domain,
389 msinr - PCI_MSI_DOORBELL_START);
390 generic_handle_irq(irq);
391 } else {
392 irq = msinr - PCI_MSI_DOORBELL_START;
393 handle_domain_irq(armada_370_xp_msi_inner_domain,
394 irq, regs);
395 }
396 }
397}
398#else
399static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
400#endif
401
402static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
403{
404 struct irq_chip *chip = irq_desc_get_chip(desc);
405 unsigned long irqmap, irqn, irqsrc, cpuid;
406 unsigned int cascade_irq;
407
408 chained_irq_enter(chip, desc);
409
410 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
411 cpuid = cpu_logical_map(smp_processor_id());
412
413 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
414 irqsrc = readl_relaxed(main_int_base +
415 ARMADA_370_XP_INT_SOURCE_CTL(irqn));
416
417 /* Check if the interrupt is not masked on current CPU.
418 * Test IRQ (0-1) and FIQ (8-9) mask bits.
419 */
420 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
421 continue;
422
423 if (irqn == 1) {
424 armada_370_xp_handle_msi_irq(NULL, true);
425 continue;
426 }
427
428 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
429 generic_handle_irq(cascade_irq);
430 }
431
432 chained_irq_exit(chip, desc);
433}
434
435static void __exception_irq_entry
436armada_370_xp_handle_irq(struct pt_regs *regs)
437{
438 u32 irqstat, irqnr;
439
440 do {
441 irqstat = readl_relaxed(per_cpu_int_base +
442 ARMADA_370_XP_CPU_INTACK_OFFS);
443 irqnr = irqstat & 0x3FF;
444
445 if (irqnr > 1022)
446 break;
447
448 if (irqnr > 1) {
449 handle_domain_irq(armada_370_xp_mpic_domain,
450 irqnr, regs);
451 continue;
452 }
453
454 /* MSI handling */
455 if (irqnr == 1)
456 armada_370_xp_handle_msi_irq(regs, false);
457
458#ifdef CONFIG_SMP
459 /* IPI Handling */
460 if (irqnr == 0) {
461 u32 ipimask, ipinr;
462
463 ipimask = readl_relaxed(per_cpu_int_base +
464 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
465 & IPI_DOORBELL_MASK;
466
467 writel(~ipimask, per_cpu_int_base +
468 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
469
470 /* Handle all pending doorbells */
471 for (ipinr = IPI_DOORBELL_START;
472 ipinr < IPI_DOORBELL_END; ipinr++) {
473 if (ipimask & (0x1 << ipinr))
474 handle_IPI(ipinr, regs);
475 }
476 continue;
477 }
478#endif
479
480 } while (1);
481}
482
483static int armada_370_xp_mpic_suspend(void)
484{
485 doorbell_mask_reg = readl(per_cpu_int_base +
486 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
487 return 0;
488}
489
490static void armada_370_xp_mpic_resume(void)
491{
492 int nirqs;
493 irq_hw_number_t irq;
494
495 /* Re-enable interrupts */
496 nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
497 for (irq = 0; irq < nirqs; irq++) {
498 struct irq_data *data;
499 int virq;
500
501 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
502 if (virq == 0)
503 continue;
504
505 if (!is_percpu_irq(irq))
506 writel(irq, per_cpu_int_base +
507 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
508 else
509 writel(irq, main_int_base +
510 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
511
512 data = irq_get_irq_data(virq);
513 if (!irqd_irq_disabled(data))
514 armada_370_xp_irq_unmask(data);
515 }
516
517 /* Reconfigure doorbells for IPIs and MSIs */
518 writel(doorbell_mask_reg,
519 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
520 if (doorbell_mask_reg & IPI_DOORBELL_MASK)
521 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
522 if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
523 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
524}
525
526static struct syscore_ops armada_370_xp_mpic_syscore_ops = {
527 .suspend = armada_370_xp_mpic_suspend,
528 .resume = armada_370_xp_mpic_resume,
529};
530
531static int __init armada_370_xp_mpic_of_init(struct device_node *node,
532 struct device_node *parent)
533{
534 struct resource main_int_res, per_cpu_int_res;
535 int nr_irqs, i;
536 u32 control;
537
538 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
539 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
540
541 BUG_ON(!request_mem_region(main_int_res.start,
542 resource_size(&main_int_res),
543 node->full_name));
544 BUG_ON(!request_mem_region(per_cpu_int_res.start,
545 resource_size(&per_cpu_int_res),
546 node->full_name));
547
548 main_int_base = ioremap(main_int_res.start,
549 resource_size(&main_int_res));
550 BUG_ON(!main_int_base);
551
552 per_cpu_int_base = ioremap(per_cpu_int_res.start,
553 resource_size(&per_cpu_int_res));
554 BUG_ON(!per_cpu_int_base);
555
556 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
557 nr_irqs = (control >> 2) & 0x3ff;
558
559 for (i = 0; i < nr_irqs; i++)
560 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
561
562 armada_370_xp_mpic_domain =
563 irq_domain_add_linear(node, nr_irqs,
564 &armada_370_xp_mpic_irq_ops, NULL);
565 BUG_ON(!armada_370_xp_mpic_domain);
566 armada_370_xp_mpic_domain->bus_token = DOMAIN_BUS_WIRED;
567
568 /* Setup for the boot CPU */
569 armada_xp_mpic_perf_init();
570 armada_xp_mpic_smp_cpu_init();
571
572 armada_370_xp_msi_init(node, main_int_res.start);
573
574 parent_irq = irq_of_parse_and_map(node, 0);
575 if (parent_irq <= 0) {
576 irq_set_default_host(armada_370_xp_mpic_domain);
577 set_handle_irq(armada_370_xp_handle_irq);
578#ifdef CONFIG_SMP
579 set_smp_cross_call(armada_mpic_send_doorbell);
580 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
581 "irqchip/armada/ipi:starting",
582 armada_xp_mpic_starting_cpu, NULL);
583#endif
584 } else {
585#ifdef CONFIG_SMP
586 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
587 "irqchip/armada/cascade:starting",
588 mpic_cascaded_starting_cpu, NULL);
589#endif
590 irq_set_chained_handler(parent_irq,
591 armada_370_xp_mpic_handle_cascade_irq);
592 }
593
594 register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
595
596 return 0;
597}
598
599IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);