1/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
  2 *
  3 * Description: CoreSight Trace Memory Controller driver
  4 *
  5 * This program is free software; you can redistribute it and/or modify
  6 * it under the terms of the GNU General Public License version 2 and
  7 * only version 2 as published by the Free Software Foundation.
  8 *
  9 * This program is distributed in the hope that it will be useful,
 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12 * GNU General Public License for more details.
 13 */
 14
 15#include <linux/kernel.h>
 16#include <linux/init.h>
 17#include <linux/types.h>
 18#include <linux/device.h>
 19#include <linux/io.h>
 20#include <linux/err.h>
 21#include <linux/fs.h>
 22#include <linux/miscdevice.h>
 23#include <linux/uaccess.h>
 24#include <linux/slab.h>
 25#include <linux/dma-mapping.h>
 26#include <linux/spinlock.h>
 27#include <linux/pm_runtime.h>
 28#include <linux/of.h>
 29#include <linux/coresight.h>
 30#include <linux/amba/bus.h>
 31
 32#include "coresight-priv.h"
 33#include "coresight-tmc.h"
 34
 35void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
 36{
 37	/* Ensure formatter, unformatter and hardware fifo are empty */
 38	if (coresight_timeout(drvdata->base,
 39			      TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
 40		dev_err(drvdata->dev,
 41			"timeout while waiting for TMC to be Ready\n");
 42	}
 43}
 44
 45void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
 46{
 47	u32 ffcr;
 48
 49	ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
 50	ffcr |= TMC_FFCR_STOP_ON_FLUSH;
 51	writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
 52	ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT);
 53	writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
 54	/* Ensure flush completes */
 55	if (coresight_timeout(drvdata->base,
 56			      TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
 57		dev_err(drvdata->dev,
 58		"timeout while waiting for completion of Manual Flush\n");
 59	}
 60
 61	tmc_wait_for_tmcready(drvdata);
 62}
 63
 64void tmc_enable_hw(struct tmc_drvdata *drvdata)
 65{
 66	writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
 67}
 68
 69void tmc_disable_hw(struct tmc_drvdata *drvdata)
 70{
 71	writel_relaxed(0x0, drvdata->base + TMC_CTL);
 72}
 73
 74static int tmc_read_prepare(struct tmc_drvdata *drvdata)
 75{
 76	int ret = 0;
 77
 78	switch (drvdata->config_type) {
 79	case TMC_CONFIG_TYPE_ETB:
 80	case TMC_CONFIG_TYPE_ETF:
 81		ret = tmc_read_prepare_etb(drvdata);
 82		break;
 83	case TMC_CONFIG_TYPE_ETR:
 84		ret = tmc_read_prepare_etr(drvdata);
 85		break;
 86	default:
 87		ret = -EINVAL;
 88	}
 89
 90	if (!ret)
 91		dev_info(drvdata->dev, "TMC read start\n");
 92
 93	return ret;
 94}
 95
 96static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
 97{
 98	int ret = 0;
 99
100	switch (drvdata->config_type) {
101	case TMC_CONFIG_TYPE_ETB:
102	case TMC_CONFIG_TYPE_ETF:
103		ret = tmc_read_unprepare_etb(drvdata);
104		break;
105	case TMC_CONFIG_TYPE_ETR:
106		ret = tmc_read_unprepare_etr(drvdata);
107		break;
108	default:
109		ret = -EINVAL;
110	}
111
112	if (!ret)
113		dev_info(drvdata->dev, "TMC read end\n");
114
115	return ret;
116}
117
118static int tmc_open(struct inode *inode, struct file *file)
119{
120	int ret;
121	struct tmc_drvdata *drvdata = container_of(file->private_data,
122						   struct tmc_drvdata, miscdev);
123
124	ret = tmc_read_prepare(drvdata);
125	if (ret)
126		return ret;
127
128	nonseekable_open(inode, file);
129
130	dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
131	return 0;
132}
133
134static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
135			loff_t *ppos)
136{
137	struct tmc_drvdata *drvdata = container_of(file->private_data,
138						   struct tmc_drvdata, miscdev);
139	char *bufp = drvdata->buf + *ppos;
140
141	if (*ppos + len > drvdata->len)
142		len = drvdata->len - *ppos;
143
144	if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
145		if (bufp == (char *)(drvdata->vaddr + drvdata->size))
146			bufp = drvdata->vaddr;
147		else if (bufp > (char *)(drvdata->vaddr + drvdata->size))
148			bufp -= drvdata->size;
149		if ((bufp + len) > (char *)(drvdata->vaddr + drvdata->size))
150			len = (char *)(drvdata->vaddr + drvdata->size) - bufp;
151	}
152
153	if (copy_to_user(data, bufp, len)) {
154		dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
155		return -EFAULT;
156	}
157
158	*ppos += len;
159
160	dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
161		__func__, len, (int)(drvdata->len - *ppos));
162	return len;
163}
164
165static int tmc_release(struct inode *inode, struct file *file)
166{
167	int ret;
168	struct tmc_drvdata *drvdata = container_of(file->private_data,
169						   struct tmc_drvdata, miscdev);
170
171	ret = tmc_read_unprepare(drvdata);
172	if (ret)
173		return ret;
174
175	dev_dbg(drvdata->dev, "%s: released\n", __func__);
176	return 0;
177}
178
179static const struct file_operations tmc_fops = {
180	.owner		= THIS_MODULE,
181	.open		= tmc_open,
182	.read		= tmc_read,
183	.release	= tmc_release,
184	.llseek		= no_llseek,
185};
186
187static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
188{
189	enum tmc_mem_intf_width memwidth;
190
191	/*
192	 * Excerpt from the TRM:
193	 *
194	 * DEVID::MEMWIDTH[10:8]
195	 * 0x2 Memory interface databus is 32 bits wide.
196	 * 0x3 Memory interface databus is 64 bits wide.
197	 * 0x4 Memory interface databus is 128 bits wide.
198	 * 0x5 Memory interface databus is 256 bits wide.
199	 */
200	switch (BMVAL(devid, 8, 10)) {
201	case 0x2:
202		memwidth = TMC_MEM_INTF_WIDTH_32BITS;
203		break;
204	case 0x3:
205		memwidth = TMC_MEM_INTF_WIDTH_64BITS;
206		break;
207	case 0x4:
208		memwidth = TMC_MEM_INTF_WIDTH_128BITS;
209		break;
210	case 0x5:
211		memwidth = TMC_MEM_INTF_WIDTH_256BITS;
212		break;
213	default:
214		memwidth = 0;
215	}
216
217	return memwidth;
218}
219
220#define coresight_tmc_simple_func(name, offset)			\
221	coresight_simple_func(struct tmc_drvdata, NULL, name, offset)
222
223coresight_tmc_simple_func(rsz, TMC_RSZ);
224coresight_tmc_simple_func(sts, TMC_STS);
225coresight_tmc_simple_func(rrp, TMC_RRP);
226coresight_tmc_simple_func(rwp, TMC_RWP);
227coresight_tmc_simple_func(trg, TMC_TRG);
228coresight_tmc_simple_func(ctl, TMC_CTL);
229coresight_tmc_simple_func(ffsr, TMC_FFSR);
230coresight_tmc_simple_func(ffcr, TMC_FFCR);
231coresight_tmc_simple_func(mode, TMC_MODE);
232coresight_tmc_simple_func(pscr, TMC_PSCR);
233coresight_tmc_simple_func(devid, CORESIGHT_DEVID);
234
235static struct attribute *coresight_tmc_mgmt_attrs[] = {
236	&dev_attr_rsz.attr,
237	&dev_attr_sts.attr,
238	&dev_attr_rrp.attr,
239	&dev_attr_rwp.attr,
240	&dev_attr_trg.attr,
241	&dev_attr_ctl.attr,
242	&dev_attr_ffsr.attr,
243	&dev_attr_ffcr.attr,
244	&dev_attr_mode.attr,
245	&dev_attr_pscr.attr,
246	&dev_attr_devid.attr,
247	NULL,
248};
249
250static ssize_t trigger_cntr_show(struct device *dev,
251				 struct device_attribute *attr, char *buf)
252{
253	struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
254	unsigned long val = drvdata->trigger_cntr;
255
256	return sprintf(buf, "%#lx\n", val);
257}
258
259static ssize_t trigger_cntr_store(struct device *dev,
260			     struct device_attribute *attr,
261			     const char *buf, size_t size)
262{
263	int ret;
264	unsigned long val;
265	struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
266
267	ret = kstrtoul(buf, 16, &val);
268	if (ret)
269		return ret;
270
271	drvdata->trigger_cntr = val;
272	return size;
273}
274static DEVICE_ATTR_RW(trigger_cntr);
275
276static struct attribute *coresight_tmc_attrs[] = {
277	&dev_attr_trigger_cntr.attr,
278	NULL,
279};
280
281static const struct attribute_group coresight_tmc_group = {
282	.attrs = coresight_tmc_attrs,
283};
284
285static const struct attribute_group coresight_tmc_mgmt_group = {
286	.attrs = coresight_tmc_mgmt_attrs,
287	.name = "mgmt",
288};
289
290const struct attribute_group *coresight_tmc_groups[] = {
291	&coresight_tmc_group,
292	&coresight_tmc_mgmt_group,
293	NULL,
294};
295
296static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
297{
298	int ret = 0;
299	u32 devid;
300	void __iomem *base;
301	struct device *dev = &adev->dev;
302	struct coresight_platform_data *pdata = NULL;
303	struct tmc_drvdata *drvdata;
304	struct resource *res = &adev->res;
305	struct coresight_desc desc = { 0 };
306	struct device_node *np = adev->dev.of_node;
307
308	if (np) {
309		pdata = of_get_coresight_platform_data(dev, np);
310		if (IS_ERR(pdata)) {
311			ret = PTR_ERR(pdata);
312			goto out;
313		}
314		adev->dev.platform_data = pdata;
315	}
316
317	ret = -ENOMEM;
318	drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
319	if (!drvdata)
320		goto out;
321
322	drvdata->dev = &adev->dev;
323	dev_set_drvdata(dev, drvdata);
324
325	/* Validity for the resource is already checked by the AMBA core */
326	base = devm_ioremap_resource(dev, res);
327	if (IS_ERR(base)) {
328		ret = PTR_ERR(base);
329		goto out;
330	}
331
332	drvdata->base = base;
333
334	spin_lock_init(&drvdata->spinlock);
335
336	devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
337	drvdata->config_type = BMVAL(devid, 6, 7);
338	drvdata->memwidth = tmc_get_memwidth(devid);
339
340	if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
341		if (np)
342			ret = of_property_read_u32(np,
343						   "arm,buffer-size",
344						   &drvdata->size);
345		if (ret)
346			drvdata->size = SZ_1M;
347	} else {
348		drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
349	}
350
351	pm_runtime_put(&adev->dev);
352
353	desc.pdata = pdata;
354	desc.dev = dev;
355	desc.groups = coresight_tmc_groups;
356
357	if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
358		desc.type = CORESIGHT_DEV_TYPE_SINK;
359		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
360		desc.ops = &tmc_etb_cs_ops;
361	} else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
362		desc.type = CORESIGHT_DEV_TYPE_SINK;
363		desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
364		desc.ops = &tmc_etr_cs_ops;
365	} else {
366		desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
367		desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
368		desc.ops = &tmc_etf_cs_ops;
369	}
370
371	drvdata->csdev = coresight_register(&desc);
372	if (IS_ERR(drvdata->csdev)) {
373		ret = PTR_ERR(drvdata->csdev);
374		goto out;
375	}
376
377	drvdata->miscdev.name = pdata->name;
378	drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
379	drvdata->miscdev.fops = &tmc_fops;
380	ret = misc_register(&drvdata->miscdev);
381	if (ret)
382		coresight_unregister(drvdata->csdev);
383out:
384	return ret;
385}
386
387static struct amba_id tmc_ids[] = {
388	{
389		.id     = 0x0003b961,
390		.mask   = 0x0003ffff,
391	},
392	{ 0, 0},
393};
394
395static struct amba_driver tmc_driver = {
396	.drv = {
397		.name   = "coresight-tmc",
398		.owner  = THIS_MODULE,
399		.suppress_bind_attrs = true,
400	},
401	.probe		= tmc_probe,
402	.id_table	= tmc_ids,
403};
404builtin_amba_driver(tmc_driver);