Loading...
Note: File does not exist in v3.15.
1/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/types.h>
17#include <linux/device.h>
18#include <linux/io.h>
19#include <linux/err.h>
20#include <linux/fs.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/smp.h>
24#include <linux/sysfs.h>
25#include <linux/stat.h>
26#include <linux/clk.h>
27#include <linux/cpu.h>
28#include <linux/coresight.h>
29#include <linux/coresight-pmu.h>
30#include <linux/pm_wakeup.h>
31#include <linux/amba/bus.h>
32#include <linux/seq_file.h>
33#include <linux/uaccess.h>
34#include <linux/perf_event.h>
35#include <linux/pm_runtime.h>
36#include <asm/sections.h>
37#include <asm/local.h>
38
39#include "coresight-etm4x.h"
40#include "coresight-etm-perf.h"
41
42static int boot_enable;
43module_param_named(boot_enable, boot_enable, int, S_IRUGO);
44
45/* The number of ETMv4 currently registered */
46static int etm4_count;
47static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
48static void etm4_set_default_config(struct etmv4_config *config);
49static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
50 struct perf_event *event);
51
52static enum cpuhp_state hp_online;
53
54static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
55{
56 /* Writing any value to ETMOSLAR unlocks the trace registers */
57 writel_relaxed(0x0, drvdata->base + TRCOSLAR);
58 drvdata->os_unlock = true;
59 isb();
60}
61
62static bool etm4_arch_supported(u8 arch)
63{
64 switch (arch) {
65 case ETM_ARCH_V4:
66 break;
67 default:
68 return false;
69 }
70 return true;
71}
72
73static int etm4_cpu_id(struct coresight_device *csdev)
74{
75 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
76
77 return drvdata->cpu;
78}
79
80static int etm4_trace_id(struct coresight_device *csdev)
81{
82 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
83
84 return drvdata->trcid;
85}
86
87static void etm4_enable_hw(void *info)
88{
89 int i;
90 struct etmv4_drvdata *drvdata = info;
91 struct etmv4_config *config = &drvdata->config;
92
93 CS_UNLOCK(drvdata->base);
94
95 etm4_os_unlock(drvdata);
96
97 /* Disable the trace unit before programming trace registers */
98 writel_relaxed(0, drvdata->base + TRCPRGCTLR);
99
100 /* wait for TRCSTATR.IDLE to go up */
101 if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
102 dev_err(drvdata->dev,
103 "timeout while waiting for Idle Trace Status\n");
104
105 writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR);
106 writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR);
107 /* nothing specific implemented */
108 writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
109 writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R);
110 writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R);
111 writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
112 writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR);
113 writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR);
114 writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR);
115 writel_relaxed(config->bb_ctrl, drvdata->base + TRCBBCTLR);
116 writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
117 writel_relaxed(config->vinst_ctrl, drvdata->base + TRCVICTLR);
118 writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR);
119 writel_relaxed(config->vissctlr,
120 drvdata->base + TRCVISSCTLR);
121 writel_relaxed(config->vipcssctlr,
122 drvdata->base + TRCVIPCSSCTLR);
123 for (i = 0; i < drvdata->nrseqstate - 1; i++)
124 writel_relaxed(config->seq_ctrl[i],
125 drvdata->base + TRCSEQEVRn(i));
126 writel_relaxed(config->seq_rst, drvdata->base + TRCSEQRSTEVR);
127 writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR);
128 writel_relaxed(config->ext_inp, drvdata->base + TRCEXTINSELR);
129 for (i = 0; i < drvdata->nr_cntr; i++) {
130 writel_relaxed(config->cntrldvr[i],
131 drvdata->base + TRCCNTRLDVRn(i));
132 writel_relaxed(config->cntr_ctrl[i],
133 drvdata->base + TRCCNTCTLRn(i));
134 writel_relaxed(config->cntr_val[i],
135 drvdata->base + TRCCNTVRn(i));
136 }
137
138 /* Resource selector pair 0 is always implemented and reserved */
139 for (i = 0; i < drvdata->nr_resource * 2; i++)
140 writel_relaxed(config->res_ctrl[i],
141 drvdata->base + TRCRSCTLRn(i));
142
143 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
144 writel_relaxed(config->ss_ctrl[i],
145 drvdata->base + TRCSSCCRn(i));
146 writel_relaxed(config->ss_status[i],
147 drvdata->base + TRCSSCSRn(i));
148 writel_relaxed(config->ss_pe_cmp[i],
149 drvdata->base + TRCSSPCICRn(i));
150 }
151 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
152 writeq_relaxed(config->addr_val[i],
153 drvdata->base + TRCACVRn(i));
154 writeq_relaxed(config->addr_acc[i],
155 drvdata->base + TRCACATRn(i));
156 }
157 for (i = 0; i < drvdata->numcidc; i++)
158 writeq_relaxed(config->ctxid_pid[i],
159 drvdata->base + TRCCIDCVRn(i));
160 writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
161 writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
162
163 for (i = 0; i < drvdata->numvmidc; i++)
164 writeq_relaxed(config->vmid_val[i],
165 drvdata->base + TRCVMIDCVRn(i));
166 writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
167 writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
168
169 /*
170 * Request to keep the trace unit powered and also
171 * emulation of powerdown
172 */
173 writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
174 drvdata->base + TRCPDCR);
175
176 /* Enable the trace unit */
177 writel_relaxed(1, drvdata->base + TRCPRGCTLR);
178
179 /* wait for TRCSTATR.IDLE to go back down to '0' */
180 if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
181 dev_err(drvdata->dev,
182 "timeout while waiting for Idle Trace Status\n");
183
184 CS_LOCK(drvdata->base);
185
186 dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
187}
188
189static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
190 struct perf_event *event)
191{
192 int ret = 0;
193 struct etmv4_config *config = &drvdata->config;
194 struct perf_event_attr *attr = &event->attr;
195
196 if (!attr) {
197 ret = -EINVAL;
198 goto out;
199 }
200
201 /* Clear configuration from previous run */
202 memset(config, 0, sizeof(struct etmv4_config));
203
204 if (attr->exclude_kernel)
205 config->mode = ETM_MODE_EXCL_KERN;
206
207 if (attr->exclude_user)
208 config->mode = ETM_MODE_EXCL_USER;
209
210 /* Always start from the default config */
211 etm4_set_default_config(config);
212
213 /* Configure filters specified on the perf cmd line, if any. */
214 ret = etm4_set_event_filters(drvdata, event);
215 if (ret)
216 goto out;
217
218 /* Go from generic option to ETMv4 specifics */
219 if (attr->config & BIT(ETM_OPT_CYCACC))
220 config->cfg |= ETMv4_MODE_CYCACC;
221 if (attr->config & BIT(ETM_OPT_TS))
222 config->cfg |= ETMv4_MODE_TIMESTAMP;
223
224out:
225 return ret;
226}
227
228static int etm4_enable_perf(struct coresight_device *csdev,
229 struct perf_event *event)
230{
231 int ret = 0;
232 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
233
234 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
235 ret = -EINVAL;
236 goto out;
237 }
238
239 /* Configure the tracer based on the session's specifics */
240 ret = etm4_parse_event_config(drvdata, event);
241 if (ret)
242 goto out;
243 /* And enable it */
244 etm4_enable_hw(drvdata);
245
246out:
247 return ret;
248}
249
250static int etm4_enable_sysfs(struct coresight_device *csdev)
251{
252 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
253 int ret;
254
255 spin_lock(&drvdata->spinlock);
256
257 /*
258 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
259 * ensures that register writes occur when cpu is powered.
260 */
261 ret = smp_call_function_single(drvdata->cpu,
262 etm4_enable_hw, drvdata, 1);
263 if (ret)
264 goto err;
265
266 drvdata->sticky_enable = true;
267 spin_unlock(&drvdata->spinlock);
268
269 dev_info(drvdata->dev, "ETM tracing enabled\n");
270 return 0;
271
272err:
273 spin_unlock(&drvdata->spinlock);
274 return ret;
275}
276
277static int etm4_enable(struct coresight_device *csdev,
278 struct perf_event *event, u32 mode)
279{
280 int ret;
281 u32 val;
282 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
283
284 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
285
286 /* Someone is already using the tracer */
287 if (val)
288 return -EBUSY;
289
290 switch (mode) {
291 case CS_MODE_SYSFS:
292 ret = etm4_enable_sysfs(csdev);
293 break;
294 case CS_MODE_PERF:
295 ret = etm4_enable_perf(csdev, event);
296 break;
297 default:
298 ret = -EINVAL;
299 }
300
301 /* The tracer didn't start */
302 if (ret)
303 local_set(&drvdata->mode, CS_MODE_DISABLED);
304
305 return ret;
306}
307
308static void etm4_disable_hw(void *info)
309{
310 u32 control;
311 struct etmv4_drvdata *drvdata = info;
312
313 CS_UNLOCK(drvdata->base);
314
315 /* power can be removed from the trace unit now */
316 control = readl_relaxed(drvdata->base + TRCPDCR);
317 control &= ~TRCPDCR_PU;
318 writel_relaxed(control, drvdata->base + TRCPDCR);
319
320 control = readl_relaxed(drvdata->base + TRCPRGCTLR);
321
322 /* EN, bit[0] Trace unit enable bit */
323 control &= ~0x1;
324
325 /* make sure everything completes before disabling */
326 mb();
327 isb();
328 writel_relaxed(control, drvdata->base + TRCPRGCTLR);
329
330 CS_LOCK(drvdata->base);
331
332 dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
333}
334
335static int etm4_disable_perf(struct coresight_device *csdev,
336 struct perf_event *event)
337{
338 u32 control;
339 struct etm_filters *filters = event->hw.addr_filters;
340 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
341
342 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
343 return -EINVAL;
344
345 etm4_disable_hw(drvdata);
346
347 /*
348 * Check if the start/stop logic was active when the unit was stopped.
349 * That way we can re-enable the start/stop logic when the process is
350 * scheduled again. Configuration of the start/stop logic happens in
351 * function etm4_set_event_filters().
352 */
353 control = readl_relaxed(drvdata->base + TRCVICTLR);
354 /* TRCVICTLR::SSSTATUS, bit[9] */
355 filters->ssstatus = (control & BIT(9));
356
357 return 0;
358}
359
360static void etm4_disable_sysfs(struct coresight_device *csdev)
361{
362 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
363
364 /*
365 * Taking hotplug lock here protects from clocks getting disabled
366 * with tracing being left on (crash scenario) if user disable occurs
367 * after cpu online mask indicates the cpu is offline but before the
368 * DYING hotplug callback is serviced by the ETM driver.
369 */
370 get_online_cpus();
371 spin_lock(&drvdata->spinlock);
372
373 /*
374 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
375 * ensures that register writes occur when cpu is powered.
376 */
377 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
378
379 spin_unlock(&drvdata->spinlock);
380 put_online_cpus();
381
382 dev_info(drvdata->dev, "ETM tracing disabled\n");
383}
384
385static void etm4_disable(struct coresight_device *csdev,
386 struct perf_event *event)
387{
388 u32 mode;
389 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
390
391 /*
392 * For as long as the tracer isn't disabled another entity can't
393 * change its status. As such we can read the status here without
394 * fearing it will change under us.
395 */
396 mode = local_read(&drvdata->mode);
397
398 switch (mode) {
399 case CS_MODE_DISABLED:
400 break;
401 case CS_MODE_SYSFS:
402 etm4_disable_sysfs(csdev);
403 break;
404 case CS_MODE_PERF:
405 etm4_disable_perf(csdev, event);
406 break;
407 }
408
409 if (mode)
410 local_set(&drvdata->mode, CS_MODE_DISABLED);
411}
412
413static const struct coresight_ops_source etm4_source_ops = {
414 .cpu_id = etm4_cpu_id,
415 .trace_id = etm4_trace_id,
416 .enable = etm4_enable,
417 .disable = etm4_disable,
418};
419
420static const struct coresight_ops etm4_cs_ops = {
421 .source_ops = &etm4_source_ops,
422};
423
424static void etm4_init_arch_data(void *info)
425{
426 u32 etmidr0;
427 u32 etmidr1;
428 u32 etmidr2;
429 u32 etmidr3;
430 u32 etmidr4;
431 u32 etmidr5;
432 struct etmv4_drvdata *drvdata = info;
433
434 /* Make sure all registers are accessible */
435 etm4_os_unlock(drvdata);
436
437 CS_UNLOCK(drvdata->base);
438
439 /* find all capabilities of the tracing unit */
440 etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
441
442 /* INSTP0, bits[2:1] P0 tracing support field */
443 if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
444 drvdata->instrp0 = true;
445 else
446 drvdata->instrp0 = false;
447
448 /* TRCBB, bit[5] Branch broadcast tracing support bit */
449 if (BMVAL(etmidr0, 5, 5))
450 drvdata->trcbb = true;
451 else
452 drvdata->trcbb = false;
453
454 /* TRCCOND, bit[6] Conditional instruction tracing support bit */
455 if (BMVAL(etmidr0, 6, 6))
456 drvdata->trccond = true;
457 else
458 drvdata->trccond = false;
459
460 /* TRCCCI, bit[7] Cycle counting instruction bit */
461 if (BMVAL(etmidr0, 7, 7))
462 drvdata->trccci = true;
463 else
464 drvdata->trccci = false;
465
466 /* RETSTACK, bit[9] Return stack bit */
467 if (BMVAL(etmidr0, 9, 9))
468 drvdata->retstack = true;
469 else
470 drvdata->retstack = false;
471
472 /* NUMEVENT, bits[11:10] Number of events field */
473 drvdata->nr_event = BMVAL(etmidr0, 10, 11);
474 /* QSUPP, bits[16:15] Q element support field */
475 drvdata->q_support = BMVAL(etmidr0, 15, 16);
476 /* TSSIZE, bits[28:24] Global timestamp size field */
477 drvdata->ts_size = BMVAL(etmidr0, 24, 28);
478
479 /* base architecture of trace unit */
480 etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
481 /*
482 * TRCARCHMIN, bits[7:4] architecture the minor version number
483 * TRCARCHMAJ, bits[11:8] architecture major versin number
484 */
485 drvdata->arch = BMVAL(etmidr1, 4, 11);
486
487 /* maximum size of resources */
488 etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
489 /* CIDSIZE, bits[9:5] Indicates the Context ID size */
490 drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
491 /* VMIDSIZE, bits[14:10] Indicates the VMID size */
492 drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
493 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
494 drvdata->ccsize = BMVAL(etmidr2, 25, 28);
495
496 etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
497 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
498 drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
499 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
500 drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
501 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
502 drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
503
504 /*
505 * TRCERR, bit[24] whether a trace unit can trace a
506 * system error exception.
507 */
508 if (BMVAL(etmidr3, 24, 24))
509 drvdata->trc_error = true;
510 else
511 drvdata->trc_error = false;
512
513 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
514 if (BMVAL(etmidr3, 25, 25))
515 drvdata->syncpr = true;
516 else
517 drvdata->syncpr = false;
518
519 /* STALLCTL, bit[26] is stall control implemented? */
520 if (BMVAL(etmidr3, 26, 26))
521 drvdata->stallctl = true;
522 else
523 drvdata->stallctl = false;
524
525 /* SYSSTALL, bit[27] implementation can support stall control? */
526 if (BMVAL(etmidr3, 27, 27))
527 drvdata->sysstall = true;
528 else
529 drvdata->sysstall = false;
530
531 /* NUMPROC, bits[30:28] the number of PEs available for tracing */
532 drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
533
534 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
535 if (BMVAL(etmidr3, 31, 31))
536 drvdata->nooverflow = true;
537 else
538 drvdata->nooverflow = false;
539
540 /* number of resources trace unit supports */
541 etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
542 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
543 drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
544 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
545 drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
546 /*
547 * NUMRSPAIR, bits[19:16]
548 * The number of resource pairs conveyed by the HW starts at 0, i.e a
549 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
550 * As such add 1 to the value of NUMRSPAIR for a better representation.
551 */
552 drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
553 /*
554 * NUMSSCC, bits[23:20] the number of single-shot
555 * comparator control for tracing
556 */
557 drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
558 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
559 drvdata->numcidc = BMVAL(etmidr4, 24, 27);
560 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
561 drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
562
563 etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
564 /* NUMEXTIN, bits[8:0] number of external inputs implemented */
565 drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
566 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
567 drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
568 /* ATBTRIG, bit[22] implementation can support ATB triggers? */
569 if (BMVAL(etmidr5, 22, 22))
570 drvdata->atbtrig = true;
571 else
572 drvdata->atbtrig = false;
573 /*
574 * LPOVERRIDE, bit[23] implementation supports
575 * low-power state override
576 */
577 if (BMVAL(etmidr5, 23, 23))
578 drvdata->lpoverride = true;
579 else
580 drvdata->lpoverride = false;
581 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
582 drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
583 /* NUMCNTR, bits[30:28] number of counters available for tracing */
584 drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
585 CS_LOCK(drvdata->base);
586}
587
588static void etm4_set_default_config(struct etmv4_config *config)
589{
590 /* disable all events tracing */
591 config->eventctrl0 = 0x0;
592 config->eventctrl1 = 0x0;
593
594 /* disable stalling */
595 config->stall_ctrl = 0x0;
596
597 /* enable trace synchronization every 4096 bytes, if available */
598 config->syncfreq = 0xC;
599
600 /* disable timestamp event */
601 config->ts_ctrl = 0x0;
602
603 /* TRCVICTLR::EVENT = 0x01, select the always on logic */
604 config->vinst_ctrl |= BIT(0);
605}
606
607static u64 etm4_get_access_type(struct etmv4_config *config)
608{
609 u64 access_type = 0;
610
611 /*
612 * EXLEVEL_NS, bits[15:12]
613 * The Exception levels are:
614 * Bit[12] Exception level 0 - Application
615 * Bit[13] Exception level 1 - OS
616 * Bit[14] Exception level 2 - Hypervisor
617 * Bit[15] Never implemented
618 *
619 * Always stay away from hypervisor mode.
620 */
621 access_type = ETM_EXLEVEL_NS_HYP;
622
623 if (config->mode & ETM_MODE_EXCL_KERN)
624 access_type |= ETM_EXLEVEL_NS_OS;
625
626 if (config->mode & ETM_MODE_EXCL_USER)
627 access_type |= ETM_EXLEVEL_NS_APP;
628
629 /*
630 * EXLEVEL_S, bits[11:8], don't trace anything happening
631 * in secure state.
632 */
633 access_type |= (ETM_EXLEVEL_S_APP |
634 ETM_EXLEVEL_S_OS |
635 ETM_EXLEVEL_S_HYP);
636
637 return access_type;
638}
639
640static void etm4_set_comparator_filter(struct etmv4_config *config,
641 u64 start, u64 stop, int comparator)
642{
643 u64 access_type = etm4_get_access_type(config);
644
645 /* First half of default address comparator */
646 config->addr_val[comparator] = start;
647 config->addr_acc[comparator] = access_type;
648 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
649
650 /* Second half of default address comparator */
651 config->addr_val[comparator + 1] = stop;
652 config->addr_acc[comparator + 1] = access_type;
653 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
654
655 /*
656 * Configure the ViewInst function to include this address range
657 * comparator.
658 *
659 * @comparator is divided by two since it is the index in the
660 * etmv4_config::addr_val array but register TRCVIIECTLR deals with
661 * address range comparator _pairs_.
662 *
663 * Therefore:
664 * index 0 -> compatator pair 0
665 * index 2 -> comparator pair 1
666 * index 4 -> comparator pair 2
667 * ...
668 * index 14 -> comparator pair 7
669 */
670 config->viiectlr |= BIT(comparator / 2);
671}
672
673static void etm4_set_start_stop_filter(struct etmv4_config *config,
674 u64 address, int comparator,
675 enum etm_addr_type type)
676{
677 int shift;
678 u64 access_type = etm4_get_access_type(config);
679
680 /* Configure the comparator */
681 config->addr_val[comparator] = address;
682 config->addr_acc[comparator] = access_type;
683 config->addr_type[comparator] = type;
684
685 /*
686 * Configure ViewInst Start-Stop control register.
687 * Addresses configured to start tracing go from bit 0 to n-1,
688 * while those configured to stop tracing from 16 to 16 + n-1.
689 */
690 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
691 config->vissctlr |= BIT(shift + comparator);
692}
693
694static void etm4_set_default_filter(struct etmv4_config *config)
695{
696 u64 start, stop;
697
698 /*
699 * Configure address range comparator '0' to encompass all
700 * possible addresses.
701 */
702 start = 0x0;
703 stop = ~0x0;
704
705 etm4_set_comparator_filter(config, start, stop,
706 ETM_DEFAULT_ADDR_COMP);
707
708 /*
709 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
710 * in the started state
711 */
712 config->vinst_ctrl |= BIT(9);
713
714 /* No start-stop filtering for ViewInst */
715 config->vissctlr = 0x0;
716}
717
718static void etm4_set_default(struct etmv4_config *config)
719{
720 if (WARN_ON_ONCE(!config))
721 return;
722
723 /*
724 * Make default initialisation trace everything
725 *
726 * Select the "always true" resource selector on the
727 * "Enablign Event" line and configure address range comparator
728 * '0' to trace all the possible address range. From there
729 * configure the "include/exclude" engine to include address
730 * range comparator '0'.
731 */
732 etm4_set_default_config(config);
733 etm4_set_default_filter(config);
734}
735
736static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
737{
738 int nr_comparator, index = 0;
739 struct etmv4_config *config = &drvdata->config;
740
741 /*
742 * nr_addr_cmp holds the number of comparator _pair_, so time 2
743 * for the total number of comparators.
744 */
745 nr_comparator = drvdata->nr_addr_cmp * 2;
746
747 /* Go through the tally of comparators looking for a free one. */
748 while (index < nr_comparator) {
749 switch (type) {
750 case ETM_ADDR_TYPE_RANGE:
751 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
752 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
753 return index;
754
755 /* Address range comparators go in pairs */
756 index += 2;
757 break;
758 case ETM_ADDR_TYPE_START:
759 case ETM_ADDR_TYPE_STOP:
760 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
761 return index;
762
763 /* Start/stop address can have odd indexes */
764 index += 1;
765 break;
766 default:
767 return -EINVAL;
768 }
769 }
770
771 /* If we are here all the comparators have been used. */
772 return -ENOSPC;
773}
774
775static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
776 struct perf_event *event)
777{
778 int i, comparator, ret = 0;
779 u64 address;
780 struct etmv4_config *config = &drvdata->config;
781 struct etm_filters *filters = event->hw.addr_filters;
782
783 if (!filters)
784 goto default_filter;
785
786 /* Sync events with what Perf got */
787 perf_event_addr_filters_sync(event);
788
789 /*
790 * If there are no filters to deal with simply go ahead with
791 * the default filter, i.e the entire address range.
792 */
793 if (!filters->nr_filters)
794 goto default_filter;
795
796 for (i = 0; i < filters->nr_filters; i++) {
797 struct etm_filter *filter = &filters->etm_filter[i];
798 enum etm_addr_type type = filter->type;
799
800 /* See if a comparator is free. */
801 comparator = etm4_get_next_comparator(drvdata, type);
802 if (comparator < 0) {
803 ret = comparator;
804 goto out;
805 }
806
807 switch (type) {
808 case ETM_ADDR_TYPE_RANGE:
809 etm4_set_comparator_filter(config,
810 filter->start_addr,
811 filter->stop_addr,
812 comparator);
813 /*
814 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
815 * in the started state
816 */
817 config->vinst_ctrl |= BIT(9);
818
819 /* No start-stop filtering for ViewInst */
820 config->vissctlr = 0x0;
821 break;
822 case ETM_ADDR_TYPE_START:
823 case ETM_ADDR_TYPE_STOP:
824 /* Get the right start or stop address */
825 address = (type == ETM_ADDR_TYPE_START ?
826 filter->start_addr :
827 filter->stop_addr);
828
829 /* Configure comparator */
830 etm4_set_start_stop_filter(config, address,
831 comparator, type);
832
833 /*
834 * If filters::ssstatus == 1, trace acquisition was
835 * started but the process was yanked away before the
836 * the stop address was hit. As such the start/stop
837 * logic needs to be re-started so that tracing can
838 * resume where it left.
839 *
840 * The start/stop logic status when a process is
841 * scheduled out is checked in function
842 * etm4_disable_perf().
843 */
844 if (filters->ssstatus)
845 config->vinst_ctrl |= BIT(9);
846
847 /* No include/exclude filtering for ViewInst */
848 config->viiectlr = 0x0;
849 break;
850 default:
851 ret = -EINVAL;
852 goto out;
853 }
854 }
855
856 goto out;
857
858
859default_filter:
860 etm4_set_default_filter(config);
861
862out:
863 return ret;
864}
865
866void etm4_config_trace_mode(struct etmv4_config *config)
867{
868 u32 addr_acc, mode;
869
870 mode = config->mode;
871 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
872
873 /* excluding kernel AND user space doesn't make sense */
874 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
875
876 /* nothing to do if neither flags are set */
877 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
878 return;
879
880 addr_acc = config->addr_acc[ETM_DEFAULT_ADDR_COMP];
881 /* clear default config */
882 addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS);
883
884 /*
885 * EXLEVEL_NS, bits[15:12]
886 * The Exception levels are:
887 * Bit[12] Exception level 0 - Application
888 * Bit[13] Exception level 1 - OS
889 * Bit[14] Exception level 2 - Hypervisor
890 * Bit[15] Never implemented
891 */
892 if (mode & ETM_MODE_EXCL_KERN)
893 addr_acc |= ETM_EXLEVEL_NS_OS;
894 else
895 addr_acc |= ETM_EXLEVEL_NS_APP;
896
897 config->addr_acc[ETM_DEFAULT_ADDR_COMP] = addr_acc;
898 config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] = addr_acc;
899}
900
901static int etm4_online_cpu(unsigned int cpu)
902{
903 if (!etmdrvdata[cpu])
904 return 0;
905
906 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
907 coresight_enable(etmdrvdata[cpu]->csdev);
908 return 0;
909}
910
911static int etm4_starting_cpu(unsigned int cpu)
912{
913 if (!etmdrvdata[cpu])
914 return 0;
915
916 spin_lock(&etmdrvdata[cpu]->spinlock);
917 if (!etmdrvdata[cpu]->os_unlock) {
918 etm4_os_unlock(etmdrvdata[cpu]);
919 etmdrvdata[cpu]->os_unlock = true;
920 }
921
922 if (local_read(&etmdrvdata[cpu]->mode))
923 etm4_enable_hw(etmdrvdata[cpu]);
924 spin_unlock(&etmdrvdata[cpu]->spinlock);
925 return 0;
926}
927
928static int etm4_dying_cpu(unsigned int cpu)
929{
930 if (!etmdrvdata[cpu])
931 return 0;
932
933 spin_lock(&etmdrvdata[cpu]->spinlock);
934 if (local_read(&etmdrvdata[cpu]->mode))
935 etm4_disable_hw(etmdrvdata[cpu]);
936 spin_unlock(&etmdrvdata[cpu]->spinlock);
937 return 0;
938}
939
940static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
941{
942 drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
943}
944
945static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
946{
947 int ret;
948 void __iomem *base;
949 struct device *dev = &adev->dev;
950 struct coresight_platform_data *pdata = NULL;
951 struct etmv4_drvdata *drvdata;
952 struct resource *res = &adev->res;
953 struct coresight_desc desc = { 0 };
954 struct device_node *np = adev->dev.of_node;
955
956 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
957 if (!drvdata)
958 return -ENOMEM;
959
960 if (np) {
961 pdata = of_get_coresight_platform_data(dev, np);
962 if (IS_ERR(pdata))
963 return PTR_ERR(pdata);
964 adev->dev.platform_data = pdata;
965 }
966
967 drvdata->dev = &adev->dev;
968 dev_set_drvdata(dev, drvdata);
969
970 /* Validity for the resource is already checked by the AMBA core */
971 base = devm_ioremap_resource(dev, res);
972 if (IS_ERR(base))
973 return PTR_ERR(base);
974
975 drvdata->base = base;
976
977 spin_lock_init(&drvdata->spinlock);
978
979 drvdata->cpu = pdata ? pdata->cpu : 0;
980
981 get_online_cpus();
982 etmdrvdata[drvdata->cpu] = drvdata;
983
984 if (smp_call_function_single(drvdata->cpu,
985 etm4_init_arch_data, drvdata, 1))
986 dev_err(dev, "ETM arch init failed\n");
987
988 if (!etm4_count++) {
989 cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
990 "arm/coresight4:starting",
991 etm4_starting_cpu, etm4_dying_cpu);
992 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
993 "arm/coresight4:online",
994 etm4_online_cpu, NULL);
995 if (ret < 0)
996 goto err_arch_supported;
997 hp_online = ret;
998 }
999
1000 put_online_cpus();
1001
1002 if (etm4_arch_supported(drvdata->arch) == false) {
1003 ret = -EINVAL;
1004 goto err_arch_supported;
1005 }
1006
1007 etm4_init_trace_id(drvdata);
1008 etm4_set_default(&drvdata->config);
1009
1010 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1011 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1012 desc.ops = &etm4_cs_ops;
1013 desc.pdata = pdata;
1014 desc.dev = dev;
1015 desc.groups = coresight_etmv4_groups;
1016 drvdata->csdev = coresight_register(&desc);
1017 if (IS_ERR(drvdata->csdev)) {
1018 ret = PTR_ERR(drvdata->csdev);
1019 goto err_arch_supported;
1020 }
1021
1022 ret = etm_perf_symlink(drvdata->csdev, true);
1023 if (ret) {
1024 coresight_unregister(drvdata->csdev);
1025 goto err_arch_supported;
1026 }
1027
1028 pm_runtime_put(&adev->dev);
1029 dev_info(dev, "%s initialized\n", (char *)id->data);
1030
1031 if (boot_enable) {
1032 coresight_enable(drvdata->csdev);
1033 drvdata->boot_enable = true;
1034 }
1035
1036 return 0;
1037
1038err_arch_supported:
1039 if (--etm4_count == 0) {
1040 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1041 if (hp_online)
1042 cpuhp_remove_state_nocalls(hp_online);
1043 }
1044 return ret;
1045}
1046
1047static struct amba_id etm4_ids[] = {
1048 { /* ETM 4.0 - Cortex-A53 */
1049 .id = 0x000bb95d,
1050 .mask = 0x000fffff,
1051 .data = "ETM 4.0",
1052 },
1053 { /* ETM 4.0 - Cortex-A57 */
1054 .id = 0x000bb95e,
1055 .mask = 0x000fffff,
1056 .data = "ETM 4.0",
1057 },
1058 { /* ETM 4.0 - A72, Maia, HiSilicon */
1059 .id = 0x000bb95a,
1060 .mask = 0x000fffff,
1061 .data = "ETM 4.0",
1062 },
1063 { 0, 0},
1064};
1065
1066static struct amba_driver etm4x_driver = {
1067 .drv = {
1068 .name = "coresight-etm4x",
1069 .suppress_bind_attrs = true,
1070 },
1071 .probe = etm4_probe,
1072 .id_table = etm4_ids,
1073};
1074builtin_amba_driver(etm4x_driver);