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1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43
44#include <linux/init.h>
45#include <linux/smp.h>
46#include <linux/module.h>
47#include <linux/sched.h>
48#include <linux/percpu.h>
49#include <linux/bootmem.h>
50#include <linux/err.h>
51#include <linux/nmi.h>
52#include <linux/tboot.h>
53#include <linux/stackprotector.h>
54#include <linux/gfp.h>
55#include <linux/cpuidle.h>
56
57#include <asm/acpi.h>
58#include <asm/desc.h>
59#include <asm/nmi.h>
60#include <asm/irq.h>
61#include <asm/idle.h>
62#include <asm/realmode.h>
63#include <asm/cpu.h>
64#include <asm/numa.h>
65#include <asm/pgtable.h>
66#include <asm/tlbflush.h>
67#include <asm/mtrr.h>
68#include <asm/mwait.h>
69#include <asm/apic.h>
70#include <asm/io_apic.h>
71#include <asm/i387.h>
72#include <asm/fpu-internal.h>
73#include <asm/setup.h>
74#include <asm/uv/uv.h>
75#include <linux/mc146818rtc.h>
76#include <asm/smpboot_hooks.h>
77#include <asm/i8259.h>
78#include <asm/realmode.h>
79#include <asm/misc.h>
80
81/* State of each CPU */
82DEFINE_PER_CPU(int, cpu_state) = { 0 };
83
84/* Number of siblings per CPU package */
85int smp_num_siblings = 1;
86EXPORT_SYMBOL(smp_num_siblings);
87
88/* Last level cache ID of each logical CPU */
89DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
90
91/* representing HT siblings of each logical CPU */
92DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
93EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
94
95/* representing HT and core siblings of each logical CPU */
96DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
97EXPORT_PER_CPU_SYMBOL(cpu_core_map);
98
99DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
100
101/* Per CPU bogomips and other parameters */
102DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
103EXPORT_PER_CPU_SYMBOL(cpu_info);
104
105atomic_t init_deasserted;
106
107/*
108 * Report back to the Boot Processor during boot time or to the caller processor
109 * during CPU online.
110 */
111static void smp_callin(void)
112{
113 int cpuid, phys_id;
114 unsigned long timeout;
115
116 /*
117 * If waken up by an INIT in an 82489DX configuration
118 * we may get here before an INIT-deassert IPI reaches
119 * our local APIC. We have to wait for the IPI or we'll
120 * lock up on an APIC access.
121 *
122 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
123 */
124 cpuid = smp_processor_id();
125 if (apic->wait_for_init_deassert && cpuid)
126 while (!atomic_read(&init_deasserted))
127 cpu_relax();
128
129 /*
130 * (This works even if the APIC is not enabled.)
131 */
132 phys_id = read_apic_id();
133 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
134 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
135 phys_id, cpuid);
136 }
137 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
138
139 /*
140 * STARTUP IPIs are fragile beasts as they might sometimes
141 * trigger some glue motherboard logic. Complete APIC bus
142 * silence for 1 second, this overestimates the time the
143 * boot CPU is spending to send the up to 2 STARTUP IPIs
144 * by a factor of two. This should be enough.
145 */
146
147 /*
148 * Waiting 2s total for startup (udelay is not yet working)
149 */
150 timeout = jiffies + 2*HZ;
151 while (time_before(jiffies, timeout)) {
152 /*
153 * Has the boot CPU finished it's STARTUP sequence?
154 */
155 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
156 break;
157 cpu_relax();
158 }
159
160 if (!time_before(jiffies, timeout)) {
161 panic("%s: CPU%d started up but did not get a callout!\n",
162 __func__, cpuid);
163 }
164
165 /*
166 * the boot CPU has finished the init stage and is spinning
167 * on callin_map until we finish. We are free to set up this
168 * CPU, first the APIC. (this is probably redundant on most
169 * boards)
170 */
171
172 pr_debug("CALLIN, before setup_local_APIC()\n");
173 if (apic->smp_callin_clear_local_apic)
174 apic->smp_callin_clear_local_apic();
175 setup_local_APIC();
176 end_local_APIC_setup();
177
178 /*
179 * Need to setup vector mappings before we enable interrupts.
180 */
181 setup_vector_irq(smp_processor_id());
182
183 /*
184 * Save our processor parameters. Note: this information
185 * is needed for clock calibration.
186 */
187 smp_store_cpu_info(cpuid);
188
189 /*
190 * Get our bogomips.
191 * Update loops_per_jiffy in cpu_data. Previous call to
192 * smp_store_cpu_info() stored a value that is close but not as
193 * accurate as the value just calculated.
194 */
195 calibrate_delay();
196 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
197 pr_debug("Stack at about %p\n", &cpuid);
198
199 /*
200 * This must be done before setting cpu_online_mask
201 * or calling notify_cpu_starting.
202 */
203 set_cpu_sibling_map(raw_smp_processor_id());
204 wmb();
205
206 notify_cpu_starting(cpuid);
207
208 /*
209 * Allow the master to continue.
210 */
211 cpumask_set_cpu(cpuid, cpu_callin_mask);
212}
213
214static int cpu0_logical_apicid;
215static int enable_start_cpu0;
216/*
217 * Activate a secondary processor.
218 */
219static void notrace start_secondary(void *unused)
220{
221 /*
222 * Don't put *anything* before cpu_init(), SMP booting is too
223 * fragile that we want to limit the things done here to the
224 * most necessary things.
225 */
226 cpu_init();
227 x86_cpuinit.early_percpu_clock_init();
228 preempt_disable();
229 smp_callin();
230
231 enable_start_cpu0 = 0;
232
233#ifdef CONFIG_X86_32
234 /* switch away from the initial page table */
235 load_cr3(swapper_pg_dir);
236 __flush_tlb_all();
237#endif
238
239 /* otherwise gcc will move up smp_processor_id before the cpu_init */
240 barrier();
241 /*
242 * Check TSC synchronization with the BP:
243 */
244 check_tsc_sync_target();
245
246 /*
247 * We need to hold vector_lock so there the set of online cpus
248 * does not change while we are assigning vectors to cpus. Holding
249 * this lock ensures we don't half assign or remove an irq from a cpu.
250 */
251 lock_vector_lock();
252 set_cpu_online(smp_processor_id(), true);
253 unlock_vector_lock();
254 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
255 x86_platform.nmi_init();
256
257 /* enable local interrupts */
258 local_irq_enable();
259
260 /* to prevent fake stack check failure in clock setup */
261 boot_init_stack_canary();
262
263 x86_cpuinit.setup_percpu_clockev();
264
265 wmb();
266 cpu_startup_entry(CPUHP_ONLINE);
267}
268
269void __init smp_store_boot_cpu_info(void)
270{
271 int id = 0; /* CPU 0 */
272 struct cpuinfo_x86 *c = &cpu_data(id);
273
274 *c = boot_cpu_data;
275 c->cpu_index = id;
276}
277
278/*
279 * The bootstrap kernel entry code has set these up. Save them for
280 * a given CPU
281 */
282void smp_store_cpu_info(int id)
283{
284 struct cpuinfo_x86 *c = &cpu_data(id);
285
286 *c = boot_cpu_data;
287 c->cpu_index = id;
288 /*
289 * During boot time, CPU0 has this setup already. Save the info when
290 * bringing up AP or offlined CPU0.
291 */
292 identify_secondary_cpu(c);
293}
294
295static bool
296topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
297{
298 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
299
300 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2),
301 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
302 "[node: %d != %d]. Ignoring dependency.\n",
303 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
304}
305
306#define link_mask(_m, c1, c2) \
307do { \
308 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
309 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
310} while (0)
311
312static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
313{
314 if (cpu_has_topoext) {
315 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
316
317 if (c->phys_proc_id == o->phys_proc_id &&
318 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
319 c->compute_unit_id == o->compute_unit_id)
320 return topology_sane(c, o, "smt");
321
322 } else if (c->phys_proc_id == o->phys_proc_id &&
323 c->cpu_core_id == o->cpu_core_id) {
324 return topology_sane(c, o, "smt");
325 }
326
327 return false;
328}
329
330static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
331{
332 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
333
334 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
335 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
336 return topology_sane(c, o, "llc");
337
338 return false;
339}
340
341static bool match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
342{
343 if (c->phys_proc_id == o->phys_proc_id) {
344 if (cpu_has(c, X86_FEATURE_AMD_DCM))
345 return true;
346
347 return topology_sane(c, o, "mc");
348 }
349 return false;
350}
351
352void set_cpu_sibling_map(int cpu)
353{
354 bool has_smt = smp_num_siblings > 1;
355 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
356 struct cpuinfo_x86 *c = &cpu_data(cpu);
357 struct cpuinfo_x86 *o;
358 int i;
359
360 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
361
362 if (!has_mp) {
363 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
364 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
365 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
366 c->booted_cores = 1;
367 return;
368 }
369
370 for_each_cpu(i, cpu_sibling_setup_mask) {
371 o = &cpu_data(i);
372
373 if ((i == cpu) || (has_smt && match_smt(c, o)))
374 link_mask(sibling, cpu, i);
375
376 if ((i == cpu) || (has_mp && match_llc(c, o)))
377 link_mask(llc_shared, cpu, i);
378
379 }
380
381 /*
382 * This needs a separate iteration over the cpus because we rely on all
383 * cpu_sibling_mask links to be set-up.
384 */
385 for_each_cpu(i, cpu_sibling_setup_mask) {
386 o = &cpu_data(i);
387
388 if ((i == cpu) || (has_mp && match_mc(c, o))) {
389 link_mask(core, cpu, i);
390
391 /*
392 * Does this new cpu bringup a new core?
393 */
394 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
395 /*
396 * for each core in package, increment
397 * the booted_cores for this new cpu
398 */
399 if (cpumask_first(cpu_sibling_mask(i)) == i)
400 c->booted_cores++;
401 /*
402 * increment the core count for all
403 * the other cpus in this package
404 */
405 if (i != cpu)
406 cpu_data(i).booted_cores++;
407 } else if (i != cpu && !c->booted_cores)
408 c->booted_cores = cpu_data(i).booted_cores;
409 }
410 }
411}
412
413/* maps the cpu to the sched domain representing multi-core */
414const struct cpumask *cpu_coregroup_mask(int cpu)
415{
416 return cpu_llc_shared_mask(cpu);
417}
418
419static void impress_friends(void)
420{
421 int cpu;
422 unsigned long bogosum = 0;
423 /*
424 * Allow the user to impress friends.
425 */
426 pr_debug("Before bogomips\n");
427 for_each_possible_cpu(cpu)
428 if (cpumask_test_cpu(cpu, cpu_callout_mask))
429 bogosum += cpu_data(cpu).loops_per_jiffy;
430 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
431 num_online_cpus(),
432 bogosum/(500000/HZ),
433 (bogosum/(5000/HZ))%100);
434
435 pr_debug("Before bogocount - setting activated=1\n");
436}
437
438void __inquire_remote_apic(int apicid)
439{
440 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
441 const char * const names[] = { "ID", "VERSION", "SPIV" };
442 int timeout;
443 u32 status;
444
445 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
446
447 for (i = 0; i < ARRAY_SIZE(regs); i++) {
448 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
449
450 /*
451 * Wait for idle.
452 */
453 status = safe_apic_wait_icr_idle();
454 if (status)
455 pr_cont("a previous APIC delivery may have failed\n");
456
457 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
458
459 timeout = 0;
460 do {
461 udelay(100);
462 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
463 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
464
465 switch (status) {
466 case APIC_ICR_RR_VALID:
467 status = apic_read(APIC_RRR);
468 pr_cont("%08x\n", status);
469 break;
470 default:
471 pr_cont("failed\n");
472 }
473 }
474}
475
476/*
477 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
478 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
479 * won't ... remember to clear down the APIC, etc later.
480 */
481int
482wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
483{
484 unsigned long send_status, accept_status = 0;
485 int maxlvt;
486
487 /* Target chip */
488 /* Boot on the stack */
489 /* Kick the second */
490 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
491
492 pr_debug("Waiting for send to finish...\n");
493 send_status = safe_apic_wait_icr_idle();
494
495 /*
496 * Give the other CPU some time to accept the IPI.
497 */
498 udelay(200);
499 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
500 maxlvt = lapic_get_maxlvt();
501 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
502 apic_write(APIC_ESR, 0);
503 accept_status = (apic_read(APIC_ESR) & 0xEF);
504 }
505 pr_debug("NMI sent\n");
506
507 if (send_status)
508 pr_err("APIC never delivered???\n");
509 if (accept_status)
510 pr_err("APIC delivery error (%lx)\n", accept_status);
511
512 return (send_status | accept_status);
513}
514
515static int
516wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
517{
518 unsigned long send_status, accept_status = 0;
519 int maxlvt, num_starts, j;
520
521 maxlvt = lapic_get_maxlvt();
522
523 /*
524 * Be paranoid about clearing APIC errors.
525 */
526 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
527 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
528 apic_write(APIC_ESR, 0);
529 apic_read(APIC_ESR);
530 }
531
532 pr_debug("Asserting INIT\n");
533
534 /*
535 * Turn INIT on target chip
536 */
537 /*
538 * Send IPI
539 */
540 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
541 phys_apicid);
542
543 pr_debug("Waiting for send to finish...\n");
544 send_status = safe_apic_wait_icr_idle();
545
546 mdelay(10);
547
548 pr_debug("Deasserting INIT\n");
549
550 /* Target chip */
551 /* Send IPI */
552 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
553
554 pr_debug("Waiting for send to finish...\n");
555 send_status = safe_apic_wait_icr_idle();
556
557 mb();
558 atomic_set(&init_deasserted, 1);
559
560 /*
561 * Should we send STARTUP IPIs ?
562 *
563 * Determine this based on the APIC version.
564 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
565 */
566 if (APIC_INTEGRATED(apic_version[phys_apicid]))
567 num_starts = 2;
568 else
569 num_starts = 0;
570
571 /*
572 * Paravirt / VMI wants a startup IPI hook here to set up the
573 * target processor state.
574 */
575 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
576 stack_start);
577
578 /*
579 * Run STARTUP IPI loop.
580 */
581 pr_debug("#startup loops: %d\n", num_starts);
582
583 for (j = 1; j <= num_starts; j++) {
584 pr_debug("Sending STARTUP #%d\n", j);
585 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
586 apic_write(APIC_ESR, 0);
587 apic_read(APIC_ESR);
588 pr_debug("After apic_write\n");
589
590 /*
591 * STARTUP IPI
592 */
593
594 /* Target chip */
595 /* Boot on the stack */
596 /* Kick the second */
597 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
598 phys_apicid);
599
600 /*
601 * Give the other CPU some time to accept the IPI.
602 */
603 udelay(300);
604
605 pr_debug("Startup point 1\n");
606
607 pr_debug("Waiting for send to finish...\n");
608 send_status = safe_apic_wait_icr_idle();
609
610 /*
611 * Give the other CPU some time to accept the IPI.
612 */
613 udelay(200);
614 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
615 apic_write(APIC_ESR, 0);
616 accept_status = (apic_read(APIC_ESR) & 0xEF);
617 if (send_status || accept_status)
618 break;
619 }
620 pr_debug("After Startup\n");
621
622 if (send_status)
623 pr_err("APIC never delivered???\n");
624 if (accept_status)
625 pr_err("APIC delivery error (%lx)\n", accept_status);
626
627 return (send_status | accept_status);
628}
629
630void smp_announce(void)
631{
632 int num_nodes = num_online_nodes();
633
634 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
635 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
636}
637
638/* reduce the number of lines printed when booting a large cpu count system */
639static void announce_cpu(int cpu, int apicid)
640{
641 static int current_node = -1;
642 int node = early_cpu_to_node(cpu);
643 static int width, node_width;
644
645 if (!width)
646 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
647
648 if (!node_width)
649 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
650
651 if (cpu == 1)
652 printk(KERN_INFO "x86: Booting SMP configuration:\n");
653
654 if (system_state == SYSTEM_BOOTING) {
655 if (node != current_node) {
656 if (current_node > (-1))
657 pr_cont("\n");
658 current_node = node;
659
660 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
661 node_width - num_digits(node), " ", node);
662 }
663
664 /* Add padding for the BSP */
665 if (cpu == 1)
666 pr_cont("%*s", width + 1, " ");
667
668 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
669
670 } else
671 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
672 node, cpu, apicid);
673}
674
675static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
676{
677 int cpu;
678
679 cpu = smp_processor_id();
680 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
681 return NMI_HANDLED;
682
683 return NMI_DONE;
684}
685
686/*
687 * Wake up AP by INIT, INIT, STARTUP sequence.
688 *
689 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
690 * boot-strap code which is not a desired behavior for waking up BSP. To
691 * void the boot-strap code, wake up CPU0 by NMI instead.
692 *
693 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
694 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
695 * We'll change this code in the future to wake up hard offlined CPU0 if
696 * real platform and request are available.
697 */
698static int
699wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
700 int *cpu0_nmi_registered)
701{
702 int id;
703 int boot_error;
704
705 preempt_disable();
706
707 /*
708 * Wake up AP by INIT, INIT, STARTUP sequence.
709 */
710 if (cpu) {
711 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
712 goto out;
713 }
714
715 /*
716 * Wake up BSP by nmi.
717 *
718 * Register a NMI handler to help wake up CPU0.
719 */
720 boot_error = register_nmi_handler(NMI_LOCAL,
721 wakeup_cpu0_nmi, 0, "wake_cpu0");
722
723 if (!boot_error) {
724 enable_start_cpu0 = 1;
725 *cpu0_nmi_registered = 1;
726 if (apic->dest_logical == APIC_DEST_LOGICAL)
727 id = cpu0_logical_apicid;
728 else
729 id = apicid;
730 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
731 }
732
733out:
734 preempt_enable();
735
736 return boot_error;
737}
738
739/*
740 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
741 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
742 * Returns zero if CPU booted OK, else error code from
743 * ->wakeup_secondary_cpu.
744 */
745static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
746{
747 volatile u32 *trampoline_status =
748 (volatile u32 *) __va(real_mode_header->trampoline_status);
749 /* start_ip had better be page-aligned! */
750 unsigned long start_ip = real_mode_header->trampoline_start;
751
752 unsigned long boot_error = 0;
753 int timeout;
754 int cpu0_nmi_registered = 0;
755
756 /* Just in case we booted with a single CPU. */
757 alternatives_enable_smp();
758
759 idle->thread.sp = (unsigned long) (((struct pt_regs *)
760 (THREAD_SIZE + task_stack_page(idle))) - 1);
761 per_cpu(current_task, cpu) = idle;
762
763#ifdef CONFIG_X86_32
764 /* Stack for startup_32 can be just as for start_secondary onwards */
765 irq_ctx_init(cpu);
766#else
767 clear_tsk_thread_flag(idle, TIF_FORK);
768 initial_gs = per_cpu_offset(cpu);
769#endif
770 per_cpu(kernel_stack, cpu) =
771 (unsigned long)task_stack_page(idle) -
772 KERNEL_STACK_OFFSET + THREAD_SIZE;
773 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
774 initial_code = (unsigned long)start_secondary;
775 stack_start = idle->thread.sp;
776
777 /* So we see what's up */
778 announce_cpu(cpu, apicid);
779
780 /*
781 * This grunge runs the startup process for
782 * the targeted processor.
783 */
784
785 atomic_set(&init_deasserted, 0);
786
787 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
788
789 pr_debug("Setting warm reset code and vector.\n");
790
791 smpboot_setup_warm_reset_vector(start_ip);
792 /*
793 * Be paranoid about clearing APIC errors.
794 */
795 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
796 apic_write(APIC_ESR, 0);
797 apic_read(APIC_ESR);
798 }
799 }
800
801 /*
802 * Wake up a CPU in difference cases:
803 * - Use the method in the APIC driver if it's defined
804 * Otherwise,
805 * - Use an INIT boot APIC message for APs or NMI for BSP.
806 */
807 if (apic->wakeup_secondary_cpu)
808 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
809 else
810 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
811 &cpu0_nmi_registered);
812
813 if (!boot_error) {
814 /*
815 * allow APs to start initializing.
816 */
817 pr_debug("Before Callout %d\n", cpu);
818 cpumask_set_cpu(cpu, cpu_callout_mask);
819 pr_debug("After Callout %d\n", cpu);
820
821 /*
822 * Wait 5s total for a response
823 */
824 for (timeout = 0; timeout < 50000; timeout++) {
825 if (cpumask_test_cpu(cpu, cpu_callin_mask))
826 break; /* It has booted */
827 udelay(100);
828 /*
829 * Allow other tasks to run while we wait for the
830 * AP to come online. This also gives a chance
831 * for the MTRR work(triggered by the AP coming online)
832 * to be completed in the stop machine context.
833 */
834 schedule();
835 }
836
837 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
838 print_cpu_msr(&cpu_data(cpu));
839 pr_debug("CPU%d: has booted.\n", cpu);
840 } else {
841 boot_error = 1;
842 if (*trampoline_status == 0xA5A5A5A5)
843 /* trampoline started but...? */
844 pr_err("CPU%d: Stuck ??\n", cpu);
845 else
846 /* trampoline code not run */
847 pr_err("CPU%d: Not responding\n", cpu);
848 if (apic->inquire_remote_apic)
849 apic->inquire_remote_apic(apicid);
850 }
851 }
852
853 if (boot_error) {
854 /* Try to put things back the way they were before ... */
855 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
856
857 /* was set by do_boot_cpu() */
858 cpumask_clear_cpu(cpu, cpu_callout_mask);
859
860 /* was set by cpu_init() */
861 cpumask_clear_cpu(cpu, cpu_initialized_mask);
862 }
863
864 /* mark "stuck" area as not stuck */
865 *trampoline_status = 0;
866
867 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
868 /*
869 * Cleanup possible dangling ends...
870 */
871 smpboot_restore_warm_reset_vector();
872 }
873 /*
874 * Clean up the nmi handler. Do this after the callin and callout sync
875 * to avoid impact of possible long unregister time.
876 */
877 if (cpu0_nmi_registered)
878 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
879
880 return boot_error;
881}
882
883int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
884{
885 int apicid = apic->cpu_present_to_apicid(cpu);
886 unsigned long flags;
887 int err;
888
889 WARN_ON(irqs_disabled());
890
891 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
892
893 if (apicid == BAD_APICID ||
894 !physid_isset(apicid, phys_cpu_present_map) ||
895 !apic->apic_id_valid(apicid)) {
896 pr_err("%s: bad cpu %d\n", __func__, cpu);
897 return -EINVAL;
898 }
899
900 /*
901 * Already booted CPU?
902 */
903 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
904 pr_debug("do_boot_cpu %d Already started\n", cpu);
905 return -ENOSYS;
906 }
907
908 /*
909 * Save current MTRR state in case it was changed since early boot
910 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
911 */
912 mtrr_save_state();
913
914 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
915
916 /* the FPU context is blank, nobody can own it */
917 __cpu_disable_lazy_restore(cpu);
918
919 err = do_boot_cpu(apicid, cpu, tidle);
920 if (err) {
921 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
922 return -EIO;
923 }
924
925 /*
926 * Check TSC synchronization with the AP (keep irqs disabled
927 * while doing so):
928 */
929 local_irq_save(flags);
930 check_tsc_sync_source(cpu);
931 local_irq_restore(flags);
932
933 while (!cpu_online(cpu)) {
934 cpu_relax();
935 touch_nmi_watchdog();
936 }
937
938 return 0;
939}
940
941/**
942 * arch_disable_smp_support() - disables SMP support for x86 at runtime
943 */
944void arch_disable_smp_support(void)
945{
946 disable_ioapic_support();
947}
948
949/*
950 * Fall back to non SMP mode after errors.
951 *
952 * RED-PEN audit/test this more. I bet there is more state messed up here.
953 */
954static __init void disable_smp(void)
955{
956 init_cpu_present(cpumask_of(0));
957 init_cpu_possible(cpumask_of(0));
958 smpboot_clear_io_apic_irqs();
959
960 if (smp_found_config)
961 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
962 else
963 physid_set_mask_of_physid(0, &phys_cpu_present_map);
964 cpumask_set_cpu(0, cpu_sibling_mask(0));
965 cpumask_set_cpu(0, cpu_core_mask(0));
966}
967
968/*
969 * Various sanity checks.
970 */
971static int __init smp_sanity_check(unsigned max_cpus)
972{
973 preempt_disable();
974
975#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
976 if (def_to_bigsmp && nr_cpu_ids > 8) {
977 unsigned int cpu;
978 unsigned nr;
979
980 pr_warn("More than 8 CPUs detected - skipping them\n"
981 "Use CONFIG_X86_BIGSMP\n");
982
983 nr = 0;
984 for_each_present_cpu(cpu) {
985 if (nr >= 8)
986 set_cpu_present(cpu, false);
987 nr++;
988 }
989
990 nr = 0;
991 for_each_possible_cpu(cpu) {
992 if (nr >= 8)
993 set_cpu_possible(cpu, false);
994 nr++;
995 }
996
997 nr_cpu_ids = 8;
998 }
999#endif
1000
1001 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1002 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1003 hard_smp_processor_id());
1004
1005 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1006 }
1007
1008 /*
1009 * If we couldn't find an SMP configuration at boot time,
1010 * get out of here now!
1011 */
1012 if (!smp_found_config && !acpi_lapic) {
1013 preempt_enable();
1014 pr_notice("SMP motherboard not detected\n");
1015 disable_smp();
1016 if (APIC_init_uniprocessor())
1017 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1018 return -1;
1019 }
1020
1021 /*
1022 * Should not be necessary because the MP table should list the boot
1023 * CPU too, but we do it for the sake of robustness anyway.
1024 */
1025 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1026 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1027 boot_cpu_physical_apicid);
1028 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1029 }
1030 preempt_enable();
1031
1032 /*
1033 * If we couldn't find a local APIC, then get out of here now!
1034 */
1035 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1036 !cpu_has_apic) {
1037 if (!disable_apic) {
1038 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1039 boot_cpu_physical_apicid);
1040 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1041 }
1042 smpboot_clear_io_apic();
1043 disable_ioapic_support();
1044 return -1;
1045 }
1046
1047 verify_local_APIC();
1048
1049 /*
1050 * If SMP should be disabled, then really disable it!
1051 */
1052 if (!max_cpus) {
1053 pr_info("SMP mode deactivated\n");
1054 smpboot_clear_io_apic();
1055
1056 connect_bsp_APIC();
1057 setup_local_APIC();
1058 bsp_end_local_APIC_setup();
1059 return -1;
1060 }
1061
1062 return 0;
1063}
1064
1065static void __init smp_cpu_index_default(void)
1066{
1067 int i;
1068 struct cpuinfo_x86 *c;
1069
1070 for_each_possible_cpu(i) {
1071 c = &cpu_data(i);
1072 /* mark all to hotplug */
1073 c->cpu_index = nr_cpu_ids;
1074 }
1075}
1076
1077/*
1078 * Prepare for SMP bootup. The MP table or ACPI has been read
1079 * earlier. Just do some sanity checking here and enable APIC mode.
1080 */
1081void __init native_smp_prepare_cpus(unsigned int max_cpus)
1082{
1083 unsigned int i;
1084
1085 preempt_disable();
1086 smp_cpu_index_default();
1087
1088 /*
1089 * Setup boot CPU information
1090 */
1091 smp_store_boot_cpu_info(); /* Final full version of the data */
1092 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1093 mb();
1094
1095 current_thread_info()->cpu = 0; /* needed? */
1096 for_each_possible_cpu(i) {
1097 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1098 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1099 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1100 }
1101 set_cpu_sibling_map(0);
1102
1103
1104 if (smp_sanity_check(max_cpus) < 0) {
1105 pr_info("SMP disabled\n");
1106 disable_smp();
1107 goto out;
1108 }
1109
1110 default_setup_apic_routing();
1111
1112 preempt_disable();
1113 if (read_apic_id() != boot_cpu_physical_apicid) {
1114 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1115 read_apic_id(), boot_cpu_physical_apicid);
1116 /* Or can we switch back to PIC here? */
1117 }
1118 preempt_enable();
1119
1120 connect_bsp_APIC();
1121
1122 /*
1123 * Switch from PIC to APIC mode.
1124 */
1125 setup_local_APIC();
1126
1127 if (x2apic_mode)
1128 cpu0_logical_apicid = apic_read(APIC_LDR);
1129 else
1130 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1131
1132 /*
1133 * Enable IO APIC before setting up error vector
1134 */
1135 if (!skip_ioapic_setup && nr_ioapics)
1136 enable_IO_APIC();
1137
1138 bsp_end_local_APIC_setup();
1139
1140 if (apic->setup_portio_remap)
1141 apic->setup_portio_remap();
1142
1143 smpboot_setup_io_apic();
1144 /*
1145 * Set up local APIC timer on boot CPU.
1146 */
1147
1148 pr_info("CPU%d: ", 0);
1149 print_cpu_info(&cpu_data(0));
1150 x86_init.timers.setup_percpu_clockev();
1151
1152 if (is_uv_system())
1153 uv_system_init();
1154
1155 set_mtrr_aps_delayed_init();
1156out:
1157 preempt_enable();
1158}
1159
1160void arch_enable_nonboot_cpus_begin(void)
1161{
1162 set_mtrr_aps_delayed_init();
1163}
1164
1165void arch_enable_nonboot_cpus_end(void)
1166{
1167 mtrr_aps_init();
1168}
1169
1170/*
1171 * Early setup to make printk work.
1172 */
1173void __init native_smp_prepare_boot_cpu(void)
1174{
1175 int me = smp_processor_id();
1176 switch_to_new_gdt(me);
1177 /* already set me in cpu_online_mask in boot_cpu_init() */
1178 cpumask_set_cpu(me, cpu_callout_mask);
1179 per_cpu(cpu_state, me) = CPU_ONLINE;
1180}
1181
1182void __init native_smp_cpus_done(unsigned int max_cpus)
1183{
1184 pr_debug("Boot done\n");
1185
1186 nmi_selftest();
1187 impress_friends();
1188#ifdef CONFIG_X86_IO_APIC
1189 setup_ioapic_dest();
1190#endif
1191 mtrr_aps_init();
1192}
1193
1194static int __initdata setup_possible_cpus = -1;
1195static int __init _setup_possible_cpus(char *str)
1196{
1197 get_option(&str, &setup_possible_cpus);
1198 return 0;
1199}
1200early_param("possible_cpus", _setup_possible_cpus);
1201
1202
1203/*
1204 * cpu_possible_mask should be static, it cannot change as cpu's
1205 * are onlined, or offlined. The reason is per-cpu data-structures
1206 * are allocated by some modules at init time, and dont expect to
1207 * do this dynamically on cpu arrival/departure.
1208 * cpu_present_mask on the other hand can change dynamically.
1209 * In case when cpu_hotplug is not compiled, then we resort to current
1210 * behaviour, which is cpu_possible == cpu_present.
1211 * - Ashok Raj
1212 *
1213 * Three ways to find out the number of additional hotplug CPUs:
1214 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1215 * - The user can overwrite it with possible_cpus=NUM
1216 * - Otherwise don't reserve additional CPUs.
1217 * We do this because additional CPUs waste a lot of memory.
1218 * -AK
1219 */
1220__init void prefill_possible_map(void)
1221{
1222 int i, possible;
1223
1224 /* no processor from mptable or madt */
1225 if (!num_processors)
1226 num_processors = 1;
1227
1228 i = setup_max_cpus ?: 1;
1229 if (setup_possible_cpus == -1) {
1230 possible = num_processors;
1231#ifdef CONFIG_HOTPLUG_CPU
1232 if (setup_max_cpus)
1233 possible += disabled_cpus;
1234#else
1235 if (possible > i)
1236 possible = i;
1237#endif
1238 } else
1239 possible = setup_possible_cpus;
1240
1241 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1242
1243 /* nr_cpu_ids could be reduced via nr_cpus= */
1244 if (possible > nr_cpu_ids) {
1245 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1246 possible, nr_cpu_ids);
1247 possible = nr_cpu_ids;
1248 }
1249
1250#ifdef CONFIG_HOTPLUG_CPU
1251 if (!setup_max_cpus)
1252#endif
1253 if (possible > i) {
1254 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1255 possible, setup_max_cpus);
1256 possible = i;
1257 }
1258
1259 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1260 possible, max_t(int, possible - num_processors, 0));
1261
1262 for (i = 0; i < possible; i++)
1263 set_cpu_possible(i, true);
1264 for (; i < NR_CPUS; i++)
1265 set_cpu_possible(i, false);
1266
1267 nr_cpu_ids = possible;
1268}
1269
1270#ifdef CONFIG_HOTPLUG_CPU
1271
1272static void remove_siblinginfo(int cpu)
1273{
1274 int sibling;
1275 struct cpuinfo_x86 *c = &cpu_data(cpu);
1276
1277 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1278 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1279 /*/
1280 * last thread sibling in this cpu core going down
1281 */
1282 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1283 cpu_data(sibling).booted_cores--;
1284 }
1285
1286 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1287 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1288 cpumask_clear(cpu_sibling_mask(cpu));
1289 cpumask_clear(cpu_core_mask(cpu));
1290 c->phys_proc_id = 0;
1291 c->cpu_core_id = 0;
1292 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1293}
1294
1295static void __ref remove_cpu_from_maps(int cpu)
1296{
1297 set_cpu_online(cpu, false);
1298 cpumask_clear_cpu(cpu, cpu_callout_mask);
1299 cpumask_clear_cpu(cpu, cpu_callin_mask);
1300 /* was set by cpu_init() */
1301 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1302 numa_remove_cpu(cpu);
1303}
1304
1305void cpu_disable_common(void)
1306{
1307 int cpu = smp_processor_id();
1308
1309 remove_siblinginfo(cpu);
1310
1311 /* It's now safe to remove this processor from the online map */
1312 lock_vector_lock();
1313 remove_cpu_from_maps(cpu);
1314 unlock_vector_lock();
1315 fixup_irqs();
1316}
1317
1318int native_cpu_disable(void)
1319{
1320 int ret;
1321
1322 ret = check_irq_vectors_for_cpu_disable();
1323 if (ret)
1324 return ret;
1325
1326 clear_local_APIC();
1327
1328 cpu_disable_common();
1329 return 0;
1330}
1331
1332void native_cpu_die(unsigned int cpu)
1333{
1334 /* We don't do anything here: idle task is faking death itself. */
1335 unsigned int i;
1336
1337 for (i = 0; i < 10; i++) {
1338 /* They ack this in play_dead by setting CPU_DEAD */
1339 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1340 if (system_state == SYSTEM_RUNNING)
1341 pr_info("CPU %u is now offline\n", cpu);
1342 return;
1343 }
1344 msleep(100);
1345 }
1346 pr_err("CPU %u didn't die...\n", cpu);
1347}
1348
1349void play_dead_common(void)
1350{
1351 idle_task_exit();
1352 reset_lazy_tlbstate();
1353 amd_e400_remove_cpu(raw_smp_processor_id());
1354
1355 mb();
1356 /* Ack it */
1357 __this_cpu_write(cpu_state, CPU_DEAD);
1358
1359 /*
1360 * With physical CPU hotplug, we should halt the cpu
1361 */
1362 local_irq_disable();
1363}
1364
1365static bool wakeup_cpu0(void)
1366{
1367 if (smp_processor_id() == 0 && enable_start_cpu0)
1368 return true;
1369
1370 return false;
1371}
1372
1373/*
1374 * We need to flush the caches before going to sleep, lest we have
1375 * dirty data in our caches when we come back up.
1376 */
1377static inline void mwait_play_dead(void)
1378{
1379 unsigned int eax, ebx, ecx, edx;
1380 unsigned int highest_cstate = 0;
1381 unsigned int highest_subcstate = 0;
1382 void *mwait_ptr;
1383 int i;
1384
1385 if (!this_cpu_has(X86_FEATURE_MWAIT))
1386 return;
1387 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1388 return;
1389 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1390 return;
1391
1392 eax = CPUID_MWAIT_LEAF;
1393 ecx = 0;
1394 native_cpuid(&eax, &ebx, &ecx, &edx);
1395
1396 /*
1397 * eax will be 0 if EDX enumeration is not valid.
1398 * Initialized below to cstate, sub_cstate value when EDX is valid.
1399 */
1400 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1401 eax = 0;
1402 } else {
1403 edx >>= MWAIT_SUBSTATE_SIZE;
1404 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1405 if (edx & MWAIT_SUBSTATE_MASK) {
1406 highest_cstate = i;
1407 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1408 }
1409 }
1410 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1411 (highest_subcstate - 1);
1412 }
1413
1414 /*
1415 * This should be a memory location in a cache line which is
1416 * unlikely to be touched by other processors. The actual
1417 * content is immaterial as it is not actually modified in any way.
1418 */
1419 mwait_ptr = ¤t_thread_info()->flags;
1420
1421 wbinvd();
1422
1423 while (1) {
1424 /*
1425 * The CLFLUSH is a workaround for erratum AAI65 for
1426 * the Xeon 7400 series. It's not clear it is actually
1427 * needed, but it should be harmless in either case.
1428 * The WBINVD is insufficient due to the spurious-wakeup
1429 * case where we return around the loop.
1430 */
1431 mb();
1432 clflush(mwait_ptr);
1433 mb();
1434 __monitor(mwait_ptr, 0, 0);
1435 mb();
1436 __mwait(eax, 0);
1437 /*
1438 * If NMI wants to wake up CPU0, start CPU0.
1439 */
1440 if (wakeup_cpu0())
1441 start_cpu0();
1442 }
1443}
1444
1445static inline void hlt_play_dead(void)
1446{
1447 if (__this_cpu_read(cpu_info.x86) >= 4)
1448 wbinvd();
1449
1450 while (1) {
1451 native_halt();
1452 /*
1453 * If NMI wants to wake up CPU0, start CPU0.
1454 */
1455 if (wakeup_cpu0())
1456 start_cpu0();
1457 }
1458}
1459
1460void native_play_dead(void)
1461{
1462 play_dead_common();
1463 tboot_shutdown(TB_SHUTDOWN_WFS);
1464
1465 mwait_play_dead(); /* Only returns on failure */
1466 if (cpuidle_play_dead())
1467 hlt_play_dead();
1468}
1469
1470#else /* ... !CONFIG_HOTPLUG_CPU */
1471int native_cpu_disable(void)
1472{
1473 return -ENOSYS;
1474}
1475
1476void native_cpu_die(unsigned int cpu)
1477{
1478 /* We said "no" in __cpu_disable */
1479 BUG();
1480}
1481
1482void native_play_dead(void)
1483{
1484 BUG();
1485}
1486
1487#endif
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43
44#include <linux/init.h>
45#include <linux/smp.h>
46#include <linux/export.h>
47#include <linux/sched.h>
48#include <linux/percpu.h>
49#include <linux/bootmem.h>
50#include <linux/err.h>
51#include <linux/nmi.h>
52#include <linux/tboot.h>
53#include <linux/stackprotector.h>
54#include <linux/gfp.h>
55#include <linux/cpuidle.h>
56
57#include <asm/acpi.h>
58#include <asm/desc.h>
59#include <asm/nmi.h>
60#include <asm/irq.h>
61#include <asm/realmode.h>
62#include <asm/cpu.h>
63#include <asm/numa.h>
64#include <asm/pgtable.h>
65#include <asm/tlbflush.h>
66#include <asm/mtrr.h>
67#include <asm/mwait.h>
68#include <asm/apic.h>
69#include <asm/io_apic.h>
70#include <asm/fpu/internal.h>
71#include <asm/setup.h>
72#include <asm/uv/uv.h>
73#include <linux/mc146818rtc.h>
74#include <asm/i8259.h>
75#include <asm/realmode.h>
76#include <asm/misc.h>
77
78/* Number of siblings per CPU package */
79int smp_num_siblings = 1;
80EXPORT_SYMBOL(smp_num_siblings);
81
82/* Last level cache ID of each logical CPU */
83DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
84
85/* representing HT siblings of each logical CPU */
86DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
87EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
88
89/* representing HT and core siblings of each logical CPU */
90DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
91EXPORT_PER_CPU_SYMBOL(cpu_core_map);
92
93DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
94
95/* Per CPU bogomips and other parameters */
96DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
97EXPORT_PER_CPU_SYMBOL(cpu_info);
98
99/* Logical package management. We might want to allocate that dynamically */
100static int *physical_to_logical_pkg __read_mostly;
101static unsigned long *physical_package_map __read_mostly;;
102static unsigned int max_physical_pkg_id __read_mostly;
103unsigned int __max_logical_packages __read_mostly;
104EXPORT_SYMBOL(__max_logical_packages);
105static unsigned int logical_packages __read_mostly;
106
107/* Maximum number of SMT threads on any online core */
108int __max_smt_threads __read_mostly;
109
110/* Flag to indicate if a complete sched domain rebuild is required */
111bool x86_topology_update;
112
113int arch_update_cpu_topology(void)
114{
115 int retval = x86_topology_update;
116
117 x86_topology_update = false;
118 return retval;
119}
120
121static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
122{
123 unsigned long flags;
124
125 spin_lock_irqsave(&rtc_lock, flags);
126 CMOS_WRITE(0xa, 0xf);
127 spin_unlock_irqrestore(&rtc_lock, flags);
128 local_flush_tlb();
129 pr_debug("1.\n");
130 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
131 start_eip >> 4;
132 pr_debug("2.\n");
133 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
134 start_eip & 0xf;
135 pr_debug("3.\n");
136}
137
138static inline void smpboot_restore_warm_reset_vector(void)
139{
140 unsigned long flags;
141
142 /*
143 * Install writable page 0 entry to set BIOS data area.
144 */
145 local_flush_tlb();
146
147 /*
148 * Paranoid: Set warm reset code and vector here back
149 * to default values.
150 */
151 spin_lock_irqsave(&rtc_lock, flags);
152 CMOS_WRITE(0, 0xf);
153 spin_unlock_irqrestore(&rtc_lock, flags);
154
155 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
156}
157
158/*
159 * Report back to the Boot Processor during boot time or to the caller processor
160 * during CPU online.
161 */
162static void smp_callin(void)
163{
164 int cpuid, phys_id;
165
166 /*
167 * If waken up by an INIT in an 82489DX configuration
168 * cpu_callout_mask guarantees we don't get here before
169 * an INIT_deassert IPI reaches our local APIC, so it is
170 * now safe to touch our local APIC.
171 */
172 cpuid = smp_processor_id();
173
174 /*
175 * (This works even if the APIC is not enabled.)
176 */
177 phys_id = read_apic_id();
178
179 /*
180 * the boot CPU has finished the init stage and is spinning
181 * on callin_map until we finish. We are free to set up this
182 * CPU, first the APIC. (this is probably redundant on most
183 * boards)
184 */
185 apic_ap_setup();
186
187 /*
188 * Save our processor parameters. Note: this information
189 * is needed for clock calibration.
190 */
191 smp_store_cpu_info(cpuid);
192
193 /*
194 * Get our bogomips.
195 * Update loops_per_jiffy in cpu_data. Previous call to
196 * smp_store_cpu_info() stored a value that is close but not as
197 * accurate as the value just calculated.
198 */
199 calibrate_delay();
200 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
201 pr_debug("Stack at about %p\n", &cpuid);
202
203 /*
204 * This must be done before setting cpu_online_mask
205 * or calling notify_cpu_starting.
206 */
207 set_cpu_sibling_map(raw_smp_processor_id());
208 wmb();
209
210 notify_cpu_starting(cpuid);
211
212 /*
213 * Allow the master to continue.
214 */
215 cpumask_set_cpu(cpuid, cpu_callin_mask);
216}
217
218static int cpu0_logical_apicid;
219static int enable_start_cpu0;
220/*
221 * Activate a secondary processor.
222 */
223static void notrace start_secondary(void *unused)
224{
225 /*
226 * Don't put *anything* before cpu_init(), SMP booting is too
227 * fragile that we want to limit the things done here to the
228 * most necessary things.
229 */
230 cpu_init();
231 x86_cpuinit.early_percpu_clock_init();
232 preempt_disable();
233 smp_callin();
234
235 enable_start_cpu0 = 0;
236
237#ifdef CONFIG_X86_32
238 /* switch away from the initial page table */
239 load_cr3(swapper_pg_dir);
240 __flush_tlb_all();
241#endif
242
243 /* otherwise gcc will move up smp_processor_id before the cpu_init */
244 barrier();
245 /*
246 * Check TSC synchronization with the BP:
247 */
248 check_tsc_sync_target();
249
250 /*
251 * Lock vector_lock and initialize the vectors on this cpu
252 * before setting the cpu online. We must set it online with
253 * vector_lock held to prevent a concurrent setup/teardown
254 * from seeing a half valid vector space.
255 */
256 lock_vector_lock();
257 setup_vector_irq(smp_processor_id());
258 set_cpu_online(smp_processor_id(), true);
259 unlock_vector_lock();
260 cpu_set_state_online(smp_processor_id());
261 x86_platform.nmi_init();
262
263 /* enable local interrupts */
264 local_irq_enable();
265
266 /* to prevent fake stack check failure in clock setup */
267 boot_init_stack_canary();
268
269 x86_cpuinit.setup_percpu_clockev();
270
271 wmb();
272 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
273}
274
275/**
276 * topology_update_package_map - Update the physical to logical package map
277 * @pkg: The physical package id as retrieved via CPUID
278 * @cpu: The cpu for which this is updated
279 */
280int topology_update_package_map(unsigned int pkg, unsigned int cpu)
281{
282 unsigned int new;
283
284 /* Called from early boot ? */
285 if (!physical_package_map)
286 return 0;
287
288 if (pkg >= max_physical_pkg_id)
289 return -EINVAL;
290
291 /* Set the logical package id */
292 if (test_and_set_bit(pkg, physical_package_map))
293 goto found;
294
295 if (logical_packages >= __max_logical_packages) {
296 pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n",
297 logical_packages, cpu, __max_logical_packages);
298 return -ENOSPC;
299 }
300
301 new = logical_packages++;
302 if (new != pkg) {
303 pr_info("CPU %u Converting physical %u to logical package %u\n",
304 cpu, pkg, new);
305 }
306 physical_to_logical_pkg[pkg] = new;
307
308found:
309 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg];
310 return 0;
311}
312
313/**
314 * topology_phys_to_logical_pkg - Map a physical package id to a logical
315 *
316 * Returns logical package id or -1 if not found
317 */
318int topology_phys_to_logical_pkg(unsigned int phys_pkg)
319{
320 if (phys_pkg >= max_physical_pkg_id)
321 return -1;
322 return physical_to_logical_pkg[phys_pkg];
323}
324EXPORT_SYMBOL(topology_phys_to_logical_pkg);
325
326static void __init smp_init_package_map(struct cpuinfo_x86 *c, unsigned int cpu)
327{
328 unsigned int ncpus;
329 size_t size;
330
331 /*
332 * Today neither Intel nor AMD support heterogenous systems. That
333 * might change in the future....
334 *
335 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
336 * computation, this won't actually work since some Intel BIOSes
337 * report inconsistent HT data when they disable HT.
338 *
339 * In particular, they reduce the APIC-IDs to only include the cores,
340 * but leave the CPUID topology to say there are (2) siblings.
341 * This means we don't know how many threads there will be until
342 * after the APIC enumeration.
343 *
344 * By not including this we'll sometimes over-estimate the number of
345 * logical packages by the amount of !present siblings, but this is
346 * still better than MAX_LOCAL_APIC.
347 *
348 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
349 * on the command line leading to a similar issue as the HT disable
350 * problem because the hyperthreads are usually enumerated after the
351 * primary cores.
352 */
353 ncpus = boot_cpu_data.x86_max_cores;
354 if (!ncpus) {
355 pr_warn("x86_max_cores == zero !?!?");
356 ncpus = 1;
357 }
358
359 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
360 logical_packages = 0;
361
362 /*
363 * Possibly larger than what we need as the number of apic ids per
364 * package can be smaller than the actual used apic ids.
365 */
366 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus);
367 size = max_physical_pkg_id * sizeof(unsigned int);
368 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL);
369 memset(physical_to_logical_pkg, 0xff, size);
370 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long);
371 physical_package_map = kzalloc(size, GFP_KERNEL);
372
373 pr_info("Max logical packages: %u\n", __max_logical_packages);
374
375 topology_update_package_map(c->phys_proc_id, cpu);
376}
377
378void __init smp_store_boot_cpu_info(void)
379{
380 int id = 0; /* CPU 0 */
381 struct cpuinfo_x86 *c = &cpu_data(id);
382
383 *c = boot_cpu_data;
384 c->cpu_index = id;
385 smp_init_package_map(c, id);
386}
387
388/*
389 * The bootstrap kernel entry code has set these up. Save them for
390 * a given CPU
391 */
392void smp_store_cpu_info(int id)
393{
394 struct cpuinfo_x86 *c = &cpu_data(id);
395
396 *c = boot_cpu_data;
397 c->cpu_index = id;
398 /*
399 * During boot time, CPU0 has this setup already. Save the info when
400 * bringing up AP or offlined CPU0.
401 */
402 identify_secondary_cpu(c);
403}
404
405static bool
406topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
407{
408 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
409
410 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
411}
412
413static bool
414topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
415{
416 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
417
418 return !WARN_ONCE(!topology_same_node(c, o),
419 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
420 "[node: %d != %d]. Ignoring dependency.\n",
421 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
422}
423
424#define link_mask(mfunc, c1, c2) \
425do { \
426 cpumask_set_cpu((c1), mfunc(c2)); \
427 cpumask_set_cpu((c2), mfunc(c1)); \
428} while (0)
429
430static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
431{
432 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
433 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
434
435 if (c->phys_proc_id == o->phys_proc_id &&
436 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
437 if (c->cpu_core_id == o->cpu_core_id)
438 return topology_sane(c, o, "smt");
439
440 if ((c->cu_id != 0xff) &&
441 (o->cu_id != 0xff) &&
442 (c->cu_id == o->cu_id))
443 return topology_sane(c, o, "smt");
444 }
445
446 } else if (c->phys_proc_id == o->phys_proc_id &&
447 c->cpu_core_id == o->cpu_core_id) {
448 return topology_sane(c, o, "smt");
449 }
450
451 return false;
452}
453
454static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
455{
456 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
457
458 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
459 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
460 return topology_sane(c, o, "llc");
461
462 return false;
463}
464
465/*
466 * Unlike the other levels, we do not enforce keeping a
467 * multicore group inside a NUMA node. If this happens, we will
468 * discard the MC level of the topology later.
469 */
470static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
471{
472 if (c->phys_proc_id == o->phys_proc_id)
473 return true;
474 return false;
475}
476
477#if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
478static inline int x86_sched_itmt_flags(void)
479{
480 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
481}
482
483#ifdef CONFIG_SCHED_MC
484static int x86_core_flags(void)
485{
486 return cpu_core_flags() | x86_sched_itmt_flags();
487}
488#endif
489#ifdef CONFIG_SCHED_SMT
490static int x86_smt_flags(void)
491{
492 return cpu_smt_flags() | x86_sched_itmt_flags();
493}
494#endif
495#endif
496
497static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
498#ifdef CONFIG_SCHED_SMT
499 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
500#endif
501#ifdef CONFIG_SCHED_MC
502 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
503#endif
504 { NULL, },
505};
506
507static struct sched_domain_topology_level x86_topology[] = {
508#ifdef CONFIG_SCHED_SMT
509 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
510#endif
511#ifdef CONFIG_SCHED_MC
512 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
513#endif
514 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
515 { NULL, },
516};
517
518/*
519 * Set if a package/die has multiple NUMA nodes inside.
520 * AMD Magny-Cours and Intel Cluster-on-Die have this.
521 */
522static bool x86_has_numa_in_package;
523
524void set_cpu_sibling_map(int cpu)
525{
526 bool has_smt = smp_num_siblings > 1;
527 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
528 struct cpuinfo_x86 *c = &cpu_data(cpu);
529 struct cpuinfo_x86 *o;
530 int i, threads;
531
532 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
533
534 if (!has_mp) {
535 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
536 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
537 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
538 c->booted_cores = 1;
539 return;
540 }
541
542 for_each_cpu(i, cpu_sibling_setup_mask) {
543 o = &cpu_data(i);
544
545 if ((i == cpu) || (has_smt && match_smt(c, o)))
546 link_mask(topology_sibling_cpumask, cpu, i);
547
548 if ((i == cpu) || (has_mp && match_llc(c, o)))
549 link_mask(cpu_llc_shared_mask, cpu, i);
550
551 }
552
553 /*
554 * This needs a separate iteration over the cpus because we rely on all
555 * topology_sibling_cpumask links to be set-up.
556 */
557 for_each_cpu(i, cpu_sibling_setup_mask) {
558 o = &cpu_data(i);
559
560 if ((i == cpu) || (has_mp && match_die(c, o))) {
561 link_mask(topology_core_cpumask, cpu, i);
562
563 /*
564 * Does this new cpu bringup a new core?
565 */
566 if (cpumask_weight(
567 topology_sibling_cpumask(cpu)) == 1) {
568 /*
569 * for each core in package, increment
570 * the booted_cores for this new cpu
571 */
572 if (cpumask_first(
573 topology_sibling_cpumask(i)) == i)
574 c->booted_cores++;
575 /*
576 * increment the core count for all
577 * the other cpus in this package
578 */
579 if (i != cpu)
580 cpu_data(i).booted_cores++;
581 } else if (i != cpu && !c->booted_cores)
582 c->booted_cores = cpu_data(i).booted_cores;
583 }
584 if (match_die(c, o) && !topology_same_node(c, o))
585 x86_has_numa_in_package = true;
586 }
587
588 threads = cpumask_weight(topology_sibling_cpumask(cpu));
589 if (threads > __max_smt_threads)
590 __max_smt_threads = threads;
591}
592
593/* maps the cpu to the sched domain representing multi-core */
594const struct cpumask *cpu_coregroup_mask(int cpu)
595{
596 return cpu_llc_shared_mask(cpu);
597}
598
599static void impress_friends(void)
600{
601 int cpu;
602 unsigned long bogosum = 0;
603 /*
604 * Allow the user to impress friends.
605 */
606 pr_debug("Before bogomips\n");
607 for_each_possible_cpu(cpu)
608 if (cpumask_test_cpu(cpu, cpu_callout_mask))
609 bogosum += cpu_data(cpu).loops_per_jiffy;
610 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
611 num_online_cpus(),
612 bogosum/(500000/HZ),
613 (bogosum/(5000/HZ))%100);
614
615 pr_debug("Before bogocount - setting activated=1\n");
616}
617
618void __inquire_remote_apic(int apicid)
619{
620 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
621 const char * const names[] = { "ID", "VERSION", "SPIV" };
622 int timeout;
623 u32 status;
624
625 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
626
627 for (i = 0; i < ARRAY_SIZE(regs); i++) {
628 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
629
630 /*
631 * Wait for idle.
632 */
633 status = safe_apic_wait_icr_idle();
634 if (status)
635 pr_cont("a previous APIC delivery may have failed\n");
636
637 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
638
639 timeout = 0;
640 do {
641 udelay(100);
642 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
643 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
644
645 switch (status) {
646 case APIC_ICR_RR_VALID:
647 status = apic_read(APIC_RRR);
648 pr_cont("%08x\n", status);
649 break;
650 default:
651 pr_cont("failed\n");
652 }
653 }
654}
655
656/*
657 * The Multiprocessor Specification 1.4 (1997) example code suggests
658 * that there should be a 10ms delay between the BSP asserting INIT
659 * and de-asserting INIT, when starting a remote processor.
660 * But that slows boot and resume on modern processors, which include
661 * many cores and don't require that delay.
662 *
663 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
664 * Modern processor families are quirked to remove the delay entirely.
665 */
666#define UDELAY_10MS_DEFAULT 10000
667
668static unsigned int init_udelay = UINT_MAX;
669
670static int __init cpu_init_udelay(char *str)
671{
672 get_option(&str, &init_udelay);
673
674 return 0;
675}
676early_param("cpu_init_udelay", cpu_init_udelay);
677
678static void __init smp_quirk_init_udelay(void)
679{
680 /* if cmdline changed it from default, leave it alone */
681 if (init_udelay != UINT_MAX)
682 return;
683
684 /* if modern processor, use no delay */
685 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
686 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
687 init_udelay = 0;
688 return;
689 }
690 /* else, use legacy delay */
691 init_udelay = UDELAY_10MS_DEFAULT;
692}
693
694/*
695 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
696 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
697 * won't ... remember to clear down the APIC, etc later.
698 */
699int
700wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
701{
702 unsigned long send_status, accept_status = 0;
703 int maxlvt;
704
705 /* Target chip */
706 /* Boot on the stack */
707 /* Kick the second */
708 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
709
710 pr_debug("Waiting for send to finish...\n");
711 send_status = safe_apic_wait_icr_idle();
712
713 /*
714 * Give the other CPU some time to accept the IPI.
715 */
716 udelay(200);
717 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
718 maxlvt = lapic_get_maxlvt();
719 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
720 apic_write(APIC_ESR, 0);
721 accept_status = (apic_read(APIC_ESR) & 0xEF);
722 }
723 pr_debug("NMI sent\n");
724
725 if (send_status)
726 pr_err("APIC never delivered???\n");
727 if (accept_status)
728 pr_err("APIC delivery error (%lx)\n", accept_status);
729
730 return (send_status | accept_status);
731}
732
733static int
734wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
735{
736 unsigned long send_status = 0, accept_status = 0;
737 int maxlvt, num_starts, j;
738
739 maxlvt = lapic_get_maxlvt();
740
741 /*
742 * Be paranoid about clearing APIC errors.
743 */
744 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
745 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
746 apic_write(APIC_ESR, 0);
747 apic_read(APIC_ESR);
748 }
749
750 pr_debug("Asserting INIT\n");
751
752 /*
753 * Turn INIT on target chip
754 */
755 /*
756 * Send IPI
757 */
758 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
759 phys_apicid);
760
761 pr_debug("Waiting for send to finish...\n");
762 send_status = safe_apic_wait_icr_idle();
763
764 udelay(init_udelay);
765
766 pr_debug("Deasserting INIT\n");
767
768 /* Target chip */
769 /* Send IPI */
770 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
771
772 pr_debug("Waiting for send to finish...\n");
773 send_status = safe_apic_wait_icr_idle();
774
775 mb();
776
777 /*
778 * Should we send STARTUP IPIs ?
779 *
780 * Determine this based on the APIC version.
781 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
782 */
783 if (APIC_INTEGRATED(boot_cpu_apic_version))
784 num_starts = 2;
785 else
786 num_starts = 0;
787
788 /*
789 * Run STARTUP IPI loop.
790 */
791 pr_debug("#startup loops: %d\n", num_starts);
792
793 for (j = 1; j <= num_starts; j++) {
794 pr_debug("Sending STARTUP #%d\n", j);
795 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
796 apic_write(APIC_ESR, 0);
797 apic_read(APIC_ESR);
798 pr_debug("After apic_write\n");
799
800 /*
801 * STARTUP IPI
802 */
803
804 /* Target chip */
805 /* Boot on the stack */
806 /* Kick the second */
807 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
808 phys_apicid);
809
810 /*
811 * Give the other CPU some time to accept the IPI.
812 */
813 if (init_udelay == 0)
814 udelay(10);
815 else
816 udelay(300);
817
818 pr_debug("Startup point 1\n");
819
820 pr_debug("Waiting for send to finish...\n");
821 send_status = safe_apic_wait_icr_idle();
822
823 /*
824 * Give the other CPU some time to accept the IPI.
825 */
826 if (init_udelay == 0)
827 udelay(10);
828 else
829 udelay(200);
830
831 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
832 apic_write(APIC_ESR, 0);
833 accept_status = (apic_read(APIC_ESR) & 0xEF);
834 if (send_status || accept_status)
835 break;
836 }
837 pr_debug("After Startup\n");
838
839 if (send_status)
840 pr_err("APIC never delivered???\n");
841 if (accept_status)
842 pr_err("APIC delivery error (%lx)\n", accept_status);
843
844 return (send_status | accept_status);
845}
846
847/* reduce the number of lines printed when booting a large cpu count system */
848static void announce_cpu(int cpu, int apicid)
849{
850 static int current_node = -1;
851 int node = early_cpu_to_node(cpu);
852 static int width, node_width;
853
854 if (!width)
855 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
856
857 if (!node_width)
858 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
859
860 if (cpu == 1)
861 printk(KERN_INFO "x86: Booting SMP configuration:\n");
862
863 if (system_state == SYSTEM_BOOTING) {
864 if (node != current_node) {
865 if (current_node > (-1))
866 pr_cont("\n");
867 current_node = node;
868
869 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
870 node_width - num_digits(node), " ", node);
871 }
872
873 /* Add padding for the BSP */
874 if (cpu == 1)
875 pr_cont("%*s", width + 1, " ");
876
877 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
878
879 } else
880 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
881 node, cpu, apicid);
882}
883
884static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
885{
886 int cpu;
887
888 cpu = smp_processor_id();
889 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
890 return NMI_HANDLED;
891
892 return NMI_DONE;
893}
894
895/*
896 * Wake up AP by INIT, INIT, STARTUP sequence.
897 *
898 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
899 * boot-strap code which is not a desired behavior for waking up BSP. To
900 * void the boot-strap code, wake up CPU0 by NMI instead.
901 *
902 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
903 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
904 * We'll change this code in the future to wake up hard offlined CPU0 if
905 * real platform and request are available.
906 */
907static int
908wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
909 int *cpu0_nmi_registered)
910{
911 int id;
912 int boot_error;
913
914 preempt_disable();
915
916 /*
917 * Wake up AP by INIT, INIT, STARTUP sequence.
918 */
919 if (cpu) {
920 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
921 goto out;
922 }
923
924 /*
925 * Wake up BSP by nmi.
926 *
927 * Register a NMI handler to help wake up CPU0.
928 */
929 boot_error = register_nmi_handler(NMI_LOCAL,
930 wakeup_cpu0_nmi, 0, "wake_cpu0");
931
932 if (!boot_error) {
933 enable_start_cpu0 = 1;
934 *cpu0_nmi_registered = 1;
935 if (apic->dest_logical == APIC_DEST_LOGICAL)
936 id = cpu0_logical_apicid;
937 else
938 id = apicid;
939 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
940 }
941
942out:
943 preempt_enable();
944
945 return boot_error;
946}
947
948void common_cpu_up(unsigned int cpu, struct task_struct *idle)
949{
950 /* Just in case we booted with a single CPU. */
951 alternatives_enable_smp();
952
953 per_cpu(current_task, cpu) = idle;
954
955#ifdef CONFIG_X86_32
956 /* Stack for startup_32 can be just as for start_secondary onwards */
957 irq_ctx_init(cpu);
958 per_cpu(cpu_current_top_of_stack, cpu) =
959 (unsigned long)task_stack_page(idle) + THREAD_SIZE;
960#else
961 initial_gs = per_cpu_offset(cpu);
962#endif
963}
964
965/*
966 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
967 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
968 * Returns zero if CPU booted OK, else error code from
969 * ->wakeup_secondary_cpu.
970 */
971static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
972{
973 volatile u32 *trampoline_status =
974 (volatile u32 *) __va(real_mode_header->trampoline_status);
975 /* start_ip had better be page-aligned! */
976 unsigned long start_ip = real_mode_header->trampoline_start;
977
978 unsigned long boot_error = 0;
979 int cpu0_nmi_registered = 0;
980 unsigned long timeout;
981
982 idle->thread.sp = (unsigned long)task_pt_regs(idle);
983 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
984 initial_code = (unsigned long)start_secondary;
985 initial_stack = idle->thread.sp;
986
987 /*
988 * Enable the espfix hack for this CPU
989 */
990#ifdef CONFIG_X86_ESPFIX64
991 init_espfix_ap(cpu);
992#endif
993
994 /* So we see what's up */
995 announce_cpu(cpu, apicid);
996
997 /*
998 * This grunge runs the startup process for
999 * the targeted processor.
1000 */
1001
1002 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1003
1004 pr_debug("Setting warm reset code and vector.\n");
1005
1006 smpboot_setup_warm_reset_vector(start_ip);
1007 /*
1008 * Be paranoid about clearing APIC errors.
1009 */
1010 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1011 apic_write(APIC_ESR, 0);
1012 apic_read(APIC_ESR);
1013 }
1014 }
1015
1016 /*
1017 * AP might wait on cpu_callout_mask in cpu_init() with
1018 * cpu_initialized_mask set if previous attempt to online
1019 * it timed-out. Clear cpu_initialized_mask so that after
1020 * INIT/SIPI it could start with a clean state.
1021 */
1022 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1023 smp_mb();
1024
1025 /*
1026 * Wake up a CPU in difference cases:
1027 * - Use the method in the APIC driver if it's defined
1028 * Otherwise,
1029 * - Use an INIT boot APIC message for APs or NMI for BSP.
1030 */
1031 if (apic->wakeup_secondary_cpu)
1032 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1033 else
1034 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1035 &cpu0_nmi_registered);
1036
1037 if (!boot_error) {
1038 /*
1039 * Wait 10s total for first sign of life from AP
1040 */
1041 boot_error = -1;
1042 timeout = jiffies + 10*HZ;
1043 while (time_before(jiffies, timeout)) {
1044 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1045 /*
1046 * Tell AP to proceed with initialization
1047 */
1048 cpumask_set_cpu(cpu, cpu_callout_mask);
1049 boot_error = 0;
1050 break;
1051 }
1052 schedule();
1053 }
1054 }
1055
1056 if (!boot_error) {
1057 /*
1058 * Wait till AP completes initial initialization
1059 */
1060 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1061 /*
1062 * Allow other tasks to run while we wait for the
1063 * AP to come online. This also gives a chance
1064 * for the MTRR work(triggered by the AP coming online)
1065 * to be completed in the stop machine context.
1066 */
1067 schedule();
1068 }
1069 }
1070
1071 /* mark "stuck" area as not stuck */
1072 *trampoline_status = 0;
1073
1074 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1075 /*
1076 * Cleanup possible dangling ends...
1077 */
1078 smpboot_restore_warm_reset_vector();
1079 }
1080 /*
1081 * Clean up the nmi handler. Do this after the callin and callout sync
1082 * to avoid impact of possible long unregister time.
1083 */
1084 if (cpu0_nmi_registered)
1085 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1086
1087 return boot_error;
1088}
1089
1090int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1091{
1092 int apicid = apic->cpu_present_to_apicid(cpu);
1093 unsigned long flags;
1094 int err;
1095
1096 WARN_ON(irqs_disabled());
1097
1098 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1099
1100 if (apicid == BAD_APICID ||
1101 !physid_isset(apicid, phys_cpu_present_map) ||
1102 !apic->apic_id_valid(apicid)) {
1103 pr_err("%s: bad cpu %d\n", __func__, cpu);
1104 return -EINVAL;
1105 }
1106
1107 /*
1108 * Already booted CPU?
1109 */
1110 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1111 pr_debug("do_boot_cpu %d Already started\n", cpu);
1112 return -ENOSYS;
1113 }
1114
1115 /*
1116 * Save current MTRR state in case it was changed since early boot
1117 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1118 */
1119 mtrr_save_state();
1120
1121 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1122 err = cpu_check_up_prepare(cpu);
1123 if (err && err != -EBUSY)
1124 return err;
1125
1126 /* the FPU context is blank, nobody can own it */
1127 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1128
1129 common_cpu_up(cpu, tidle);
1130
1131 err = do_boot_cpu(apicid, cpu, tidle);
1132 if (err) {
1133 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1134 return -EIO;
1135 }
1136
1137 /*
1138 * Check TSC synchronization with the AP (keep irqs disabled
1139 * while doing so):
1140 */
1141 local_irq_save(flags);
1142 check_tsc_sync_source(cpu);
1143 local_irq_restore(flags);
1144
1145 while (!cpu_online(cpu)) {
1146 cpu_relax();
1147 touch_nmi_watchdog();
1148 }
1149
1150 return 0;
1151}
1152
1153/**
1154 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1155 */
1156void arch_disable_smp_support(void)
1157{
1158 disable_ioapic_support();
1159}
1160
1161/*
1162 * Fall back to non SMP mode after errors.
1163 *
1164 * RED-PEN audit/test this more. I bet there is more state messed up here.
1165 */
1166static __init void disable_smp(void)
1167{
1168 pr_info("SMP disabled\n");
1169
1170 disable_ioapic_support();
1171
1172 init_cpu_present(cpumask_of(0));
1173 init_cpu_possible(cpumask_of(0));
1174
1175 if (smp_found_config)
1176 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1177 else
1178 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1179 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1180 cpumask_set_cpu(0, topology_core_cpumask(0));
1181}
1182
1183enum {
1184 SMP_OK,
1185 SMP_NO_CONFIG,
1186 SMP_NO_APIC,
1187 SMP_FORCE_UP,
1188};
1189
1190/*
1191 * Various sanity checks.
1192 */
1193static int __init smp_sanity_check(unsigned max_cpus)
1194{
1195 preempt_disable();
1196
1197#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1198 if (def_to_bigsmp && nr_cpu_ids > 8) {
1199 unsigned int cpu;
1200 unsigned nr;
1201
1202 pr_warn("More than 8 CPUs detected - skipping them\n"
1203 "Use CONFIG_X86_BIGSMP\n");
1204
1205 nr = 0;
1206 for_each_present_cpu(cpu) {
1207 if (nr >= 8)
1208 set_cpu_present(cpu, false);
1209 nr++;
1210 }
1211
1212 nr = 0;
1213 for_each_possible_cpu(cpu) {
1214 if (nr >= 8)
1215 set_cpu_possible(cpu, false);
1216 nr++;
1217 }
1218
1219 nr_cpu_ids = 8;
1220 }
1221#endif
1222
1223 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1224 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1225 hard_smp_processor_id());
1226
1227 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1228 }
1229
1230 /*
1231 * If we couldn't find an SMP configuration at boot time,
1232 * get out of here now!
1233 */
1234 if (!smp_found_config && !acpi_lapic) {
1235 preempt_enable();
1236 pr_notice("SMP motherboard not detected\n");
1237 return SMP_NO_CONFIG;
1238 }
1239
1240 /*
1241 * Should not be necessary because the MP table should list the boot
1242 * CPU too, but we do it for the sake of robustness anyway.
1243 */
1244 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1245 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1246 boot_cpu_physical_apicid);
1247 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1248 }
1249 preempt_enable();
1250
1251 /*
1252 * If we couldn't find a local APIC, then get out of here now!
1253 */
1254 if (APIC_INTEGRATED(boot_cpu_apic_version) &&
1255 !boot_cpu_has(X86_FEATURE_APIC)) {
1256 if (!disable_apic) {
1257 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1258 boot_cpu_physical_apicid);
1259 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1260 }
1261 return SMP_NO_APIC;
1262 }
1263
1264 /*
1265 * If SMP should be disabled, then really disable it!
1266 */
1267 if (!max_cpus) {
1268 pr_info("SMP mode deactivated\n");
1269 return SMP_FORCE_UP;
1270 }
1271
1272 return SMP_OK;
1273}
1274
1275static void __init smp_cpu_index_default(void)
1276{
1277 int i;
1278 struct cpuinfo_x86 *c;
1279
1280 for_each_possible_cpu(i) {
1281 c = &cpu_data(i);
1282 /* mark all to hotplug */
1283 c->cpu_index = nr_cpu_ids;
1284 }
1285}
1286
1287/*
1288 * Prepare for SMP bootup. The MP table or ACPI has been read
1289 * earlier. Just do some sanity checking here and enable APIC mode.
1290 */
1291void __init native_smp_prepare_cpus(unsigned int max_cpus)
1292{
1293 unsigned int i;
1294
1295 smp_cpu_index_default();
1296
1297 /*
1298 * Setup boot CPU information
1299 */
1300 smp_store_boot_cpu_info(); /* Final full version of the data */
1301 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1302 mb();
1303
1304 for_each_possible_cpu(i) {
1305 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1306 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1307 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1308 }
1309
1310 /*
1311 * Set 'default' x86 topology, this matches default_topology() in that
1312 * it has NUMA nodes as a topology level. See also
1313 * native_smp_cpus_done().
1314 *
1315 * Must be done before set_cpus_sibling_map() is ran.
1316 */
1317 set_sched_topology(x86_topology);
1318
1319 set_cpu_sibling_map(0);
1320
1321 switch (smp_sanity_check(max_cpus)) {
1322 case SMP_NO_CONFIG:
1323 disable_smp();
1324 if (APIC_init_uniprocessor())
1325 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1326 return;
1327 case SMP_NO_APIC:
1328 disable_smp();
1329 return;
1330 case SMP_FORCE_UP:
1331 disable_smp();
1332 apic_bsp_setup(false);
1333 return;
1334 case SMP_OK:
1335 break;
1336 }
1337
1338 if (read_apic_id() != boot_cpu_physical_apicid) {
1339 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1340 read_apic_id(), boot_cpu_physical_apicid);
1341 /* Or can we switch back to PIC here? */
1342 }
1343
1344 default_setup_apic_routing();
1345 cpu0_logical_apicid = apic_bsp_setup(false);
1346
1347 pr_info("CPU0: ");
1348 print_cpu_info(&cpu_data(0));
1349
1350 if (is_uv_system())
1351 uv_system_init();
1352
1353 set_mtrr_aps_delayed_init();
1354
1355 smp_quirk_init_udelay();
1356}
1357
1358void arch_enable_nonboot_cpus_begin(void)
1359{
1360 set_mtrr_aps_delayed_init();
1361}
1362
1363void arch_enable_nonboot_cpus_end(void)
1364{
1365 mtrr_aps_init();
1366}
1367
1368/*
1369 * Early setup to make printk work.
1370 */
1371void __init native_smp_prepare_boot_cpu(void)
1372{
1373 int me = smp_processor_id();
1374 switch_to_new_gdt(me);
1375 /* already set me in cpu_online_mask in boot_cpu_init() */
1376 cpumask_set_cpu(me, cpu_callout_mask);
1377 cpu_set_state_online(me);
1378}
1379
1380void __init native_smp_cpus_done(unsigned int max_cpus)
1381{
1382 pr_debug("Boot done\n");
1383
1384 if (x86_has_numa_in_package)
1385 set_sched_topology(x86_numa_in_package_topology);
1386
1387 nmi_selftest();
1388 impress_friends();
1389 setup_ioapic_dest();
1390 mtrr_aps_init();
1391}
1392
1393static int __initdata setup_possible_cpus = -1;
1394static int __init _setup_possible_cpus(char *str)
1395{
1396 get_option(&str, &setup_possible_cpus);
1397 return 0;
1398}
1399early_param("possible_cpus", _setup_possible_cpus);
1400
1401
1402/*
1403 * cpu_possible_mask should be static, it cannot change as cpu's
1404 * are onlined, or offlined. The reason is per-cpu data-structures
1405 * are allocated by some modules at init time, and dont expect to
1406 * do this dynamically on cpu arrival/departure.
1407 * cpu_present_mask on the other hand can change dynamically.
1408 * In case when cpu_hotplug is not compiled, then we resort to current
1409 * behaviour, which is cpu_possible == cpu_present.
1410 * - Ashok Raj
1411 *
1412 * Three ways to find out the number of additional hotplug CPUs:
1413 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1414 * - The user can overwrite it with possible_cpus=NUM
1415 * - Otherwise don't reserve additional CPUs.
1416 * We do this because additional CPUs waste a lot of memory.
1417 * -AK
1418 */
1419__init void prefill_possible_map(void)
1420{
1421 int i, possible;
1422
1423 /* No boot processor was found in mptable or ACPI MADT */
1424 if (!num_processors) {
1425 if (boot_cpu_has(X86_FEATURE_APIC)) {
1426 int apicid = boot_cpu_physical_apicid;
1427 int cpu = hard_smp_processor_id();
1428
1429 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1430
1431 /* Make sure boot cpu is enumerated */
1432 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1433 apic->apic_id_valid(apicid))
1434 generic_processor_info(apicid, boot_cpu_apic_version);
1435 }
1436
1437 if (!num_processors)
1438 num_processors = 1;
1439 }
1440
1441 i = setup_max_cpus ?: 1;
1442 if (setup_possible_cpus == -1) {
1443 possible = num_processors;
1444#ifdef CONFIG_HOTPLUG_CPU
1445 if (setup_max_cpus)
1446 possible += disabled_cpus;
1447#else
1448 if (possible > i)
1449 possible = i;
1450#endif
1451 } else
1452 possible = setup_possible_cpus;
1453
1454 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1455
1456 /* nr_cpu_ids could be reduced via nr_cpus= */
1457 if (possible > nr_cpu_ids) {
1458 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1459 possible, nr_cpu_ids);
1460 possible = nr_cpu_ids;
1461 }
1462
1463#ifdef CONFIG_HOTPLUG_CPU
1464 if (!setup_max_cpus)
1465#endif
1466 if (possible > i) {
1467 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1468 possible, setup_max_cpus);
1469 possible = i;
1470 }
1471
1472 nr_cpu_ids = possible;
1473
1474 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1475 possible, max_t(int, possible - num_processors, 0));
1476
1477 reset_cpu_possible_mask();
1478
1479 for (i = 0; i < possible; i++)
1480 set_cpu_possible(i, true);
1481}
1482
1483#ifdef CONFIG_HOTPLUG_CPU
1484
1485/* Recompute SMT state for all CPUs on offline */
1486static void recompute_smt_state(void)
1487{
1488 int max_threads, cpu;
1489
1490 max_threads = 0;
1491 for_each_online_cpu (cpu) {
1492 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1493
1494 if (threads > max_threads)
1495 max_threads = threads;
1496 }
1497 __max_smt_threads = max_threads;
1498}
1499
1500static void remove_siblinginfo(int cpu)
1501{
1502 int sibling;
1503 struct cpuinfo_x86 *c = &cpu_data(cpu);
1504
1505 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1506 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1507 /*/
1508 * last thread sibling in this cpu core going down
1509 */
1510 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1511 cpu_data(sibling).booted_cores--;
1512 }
1513
1514 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1515 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1516 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1517 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1518 cpumask_clear(cpu_llc_shared_mask(cpu));
1519 cpumask_clear(topology_sibling_cpumask(cpu));
1520 cpumask_clear(topology_core_cpumask(cpu));
1521 c->phys_proc_id = 0;
1522 c->cpu_core_id = 0;
1523 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1524 recompute_smt_state();
1525}
1526
1527static void remove_cpu_from_maps(int cpu)
1528{
1529 set_cpu_online(cpu, false);
1530 cpumask_clear_cpu(cpu, cpu_callout_mask);
1531 cpumask_clear_cpu(cpu, cpu_callin_mask);
1532 /* was set by cpu_init() */
1533 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1534 numa_remove_cpu(cpu);
1535}
1536
1537void cpu_disable_common(void)
1538{
1539 int cpu = smp_processor_id();
1540
1541 remove_siblinginfo(cpu);
1542
1543 /* It's now safe to remove this processor from the online map */
1544 lock_vector_lock();
1545 remove_cpu_from_maps(cpu);
1546 unlock_vector_lock();
1547 fixup_irqs();
1548}
1549
1550int native_cpu_disable(void)
1551{
1552 int ret;
1553
1554 ret = check_irq_vectors_for_cpu_disable();
1555 if (ret)
1556 return ret;
1557
1558 clear_local_APIC();
1559 cpu_disable_common();
1560
1561 return 0;
1562}
1563
1564int common_cpu_die(unsigned int cpu)
1565{
1566 int ret = 0;
1567
1568 /* We don't do anything here: idle task is faking death itself. */
1569
1570 /* They ack this in play_dead() by setting CPU_DEAD */
1571 if (cpu_wait_death(cpu, 5)) {
1572 if (system_state == SYSTEM_RUNNING)
1573 pr_info("CPU %u is now offline\n", cpu);
1574 } else {
1575 pr_err("CPU %u didn't die...\n", cpu);
1576 ret = -1;
1577 }
1578
1579 return ret;
1580}
1581
1582void native_cpu_die(unsigned int cpu)
1583{
1584 common_cpu_die(cpu);
1585}
1586
1587void play_dead_common(void)
1588{
1589 idle_task_exit();
1590 reset_lazy_tlbstate();
1591
1592 /* Ack it */
1593 (void)cpu_report_death();
1594
1595 /*
1596 * With physical CPU hotplug, we should halt the cpu
1597 */
1598 local_irq_disable();
1599}
1600
1601static bool wakeup_cpu0(void)
1602{
1603 if (smp_processor_id() == 0 && enable_start_cpu0)
1604 return true;
1605
1606 return false;
1607}
1608
1609/*
1610 * We need to flush the caches before going to sleep, lest we have
1611 * dirty data in our caches when we come back up.
1612 */
1613static inline void mwait_play_dead(void)
1614{
1615 unsigned int eax, ebx, ecx, edx;
1616 unsigned int highest_cstate = 0;
1617 unsigned int highest_subcstate = 0;
1618 void *mwait_ptr;
1619 int i;
1620
1621 if (!this_cpu_has(X86_FEATURE_MWAIT))
1622 return;
1623 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1624 return;
1625 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1626 return;
1627
1628 eax = CPUID_MWAIT_LEAF;
1629 ecx = 0;
1630 native_cpuid(&eax, &ebx, &ecx, &edx);
1631
1632 /*
1633 * eax will be 0 if EDX enumeration is not valid.
1634 * Initialized below to cstate, sub_cstate value when EDX is valid.
1635 */
1636 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1637 eax = 0;
1638 } else {
1639 edx >>= MWAIT_SUBSTATE_SIZE;
1640 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1641 if (edx & MWAIT_SUBSTATE_MASK) {
1642 highest_cstate = i;
1643 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1644 }
1645 }
1646 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1647 (highest_subcstate - 1);
1648 }
1649
1650 /*
1651 * This should be a memory location in a cache line which is
1652 * unlikely to be touched by other processors. The actual
1653 * content is immaterial as it is not actually modified in any way.
1654 */
1655 mwait_ptr = ¤t_thread_info()->flags;
1656
1657 wbinvd();
1658
1659 while (1) {
1660 /*
1661 * The CLFLUSH is a workaround for erratum AAI65 for
1662 * the Xeon 7400 series. It's not clear it is actually
1663 * needed, but it should be harmless in either case.
1664 * The WBINVD is insufficient due to the spurious-wakeup
1665 * case where we return around the loop.
1666 */
1667 mb();
1668 clflush(mwait_ptr);
1669 mb();
1670 __monitor(mwait_ptr, 0, 0);
1671 mb();
1672 __mwait(eax, 0);
1673 /*
1674 * If NMI wants to wake up CPU0, start CPU0.
1675 */
1676 if (wakeup_cpu0())
1677 start_cpu0();
1678 }
1679}
1680
1681void hlt_play_dead(void)
1682{
1683 if (__this_cpu_read(cpu_info.x86) >= 4)
1684 wbinvd();
1685
1686 while (1) {
1687 native_halt();
1688 /*
1689 * If NMI wants to wake up CPU0, start CPU0.
1690 */
1691 if (wakeup_cpu0())
1692 start_cpu0();
1693 }
1694}
1695
1696void native_play_dead(void)
1697{
1698 play_dead_common();
1699 tboot_shutdown(TB_SHUTDOWN_WFS);
1700
1701 mwait_play_dead(); /* Only returns on failure */
1702 if (cpuidle_play_dead())
1703 hlt_play_dead();
1704}
1705
1706#else /* ... !CONFIG_HOTPLUG_CPU */
1707int native_cpu_disable(void)
1708{
1709 return -ENOSYS;
1710}
1711
1712void native_cpu_die(unsigned int cpu)
1713{
1714 /* We said "no" in __cpu_disable */
1715 BUG();
1716}
1717
1718void native_play_dead(void)
1719{
1720 BUG();
1721}
1722
1723#endif