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1/* Various workarounds for chipset bugs.
2 This code runs very early and can't use the regular PCI subsystem
3 The entries are keyed to PCI bridges which usually identify chipsets
4 uniquely.
5 This is only for whole classes of chipsets with specific problems which
6 need early invasive action (e.g. before the timers are initialized).
7 Most PCI device specific workarounds can be done later and should be
8 in standard PCI quirks
9 Mainboard specific bugs should be handled by DMI entries.
10 CPU specific bugs in setup.c */
11
12#include <linux/pci.h>
13#include <linux/acpi.h>
14#include <linux/pci_ids.h>
15#include <drm/i915_drm.h>
16#include <asm/pci-direct.h>
17#include <asm/dma.h>
18#include <asm/io_apic.h>
19#include <asm/apic.h>
20#include <asm/hpet.h>
21#include <asm/iommu.h>
22#include <asm/gart.h>
23#include <asm/irq_remapping.h>
24
25static void __init fix_hypertransport_config(int num, int slot, int func)
26{
27 u32 htcfg;
28 /*
29 * we found a hypertransport bus
30 * make sure that we are broadcasting
31 * interrupts to all cpus on the ht bus
32 * if we're using extended apic ids
33 */
34 htcfg = read_pci_config(num, slot, func, 0x68);
35 if (htcfg & (1 << 18)) {
36 printk(KERN_INFO "Detected use of extended apic ids "
37 "on hypertransport bus\n");
38 if ((htcfg & (1 << 17)) == 0) {
39 printk(KERN_INFO "Enabling hypertransport extended "
40 "apic interrupt broadcast\n");
41 printk(KERN_INFO "Note this is a bios bug, "
42 "please contact your hw vendor\n");
43 htcfg |= (1 << 17);
44 write_pci_config(num, slot, func, 0x68, htcfg);
45 }
46 }
47
48
49}
50
51static void __init via_bugs(int num, int slot, int func)
52{
53#ifdef CONFIG_GART_IOMMU
54 if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
55 !gart_iommu_aperture_allowed) {
56 printk(KERN_INFO
57 "Looks like a VIA chipset. Disabling IOMMU."
58 " Override with iommu=allowed\n");
59 gart_iommu_aperture_disabled = 1;
60 }
61#endif
62}
63
64#ifdef CONFIG_ACPI
65#ifdef CONFIG_X86_IO_APIC
66
67static int __init nvidia_hpet_check(struct acpi_table_header *header)
68{
69 return 0;
70}
71#endif /* CONFIG_X86_IO_APIC */
72#endif /* CONFIG_ACPI */
73
74static void __init nvidia_bugs(int num, int slot, int func)
75{
76#ifdef CONFIG_ACPI
77#ifdef CONFIG_X86_IO_APIC
78 /*
79 * All timer overrides on Nvidia are
80 * wrong unless HPET is enabled.
81 * Unfortunately that's not true on many Asus boards.
82 * We don't know yet how to detect this automatically, but
83 * at least allow a command line override.
84 */
85 if (acpi_use_timer_override)
86 return;
87
88 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
89 acpi_skip_timer_override = 1;
90 printk(KERN_INFO "Nvidia board "
91 "detected. Ignoring ACPI "
92 "timer override.\n");
93 printk(KERN_INFO "If you got timer trouble "
94 "try acpi_use_timer_override\n");
95 }
96#endif
97#endif
98 /* RED-PEN skip them on mptables too? */
99
100}
101
102#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
103static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
104{
105 u32 d;
106 u8 b;
107
108 b = read_pci_config_byte(num, slot, func, 0xac);
109 b &= ~(1<<5);
110 write_pci_config_byte(num, slot, func, 0xac, b);
111
112 d = read_pci_config(num, slot, func, 0x70);
113 d |= 1<<8;
114 write_pci_config(num, slot, func, 0x70, d);
115
116 d = read_pci_config(num, slot, func, 0x8);
117 d &= 0xff;
118 return d;
119}
120
121static void __init ati_bugs(int num, int slot, int func)
122{
123 u32 d;
124 u8 b;
125
126 if (acpi_use_timer_override)
127 return;
128
129 d = ati_ixp4x0_rev(num, slot, func);
130 if (d < 0x82)
131 acpi_skip_timer_override = 1;
132 else {
133 /* check for IRQ0 interrupt swap */
134 outb(0x72, 0xcd6); b = inb(0xcd7);
135 if (!(b & 0x2))
136 acpi_skip_timer_override = 1;
137 }
138
139 if (acpi_skip_timer_override) {
140 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
141 printk(KERN_INFO "Ignoring ACPI timer override.\n");
142 printk(KERN_INFO "If you got timer trouble "
143 "try acpi_use_timer_override\n");
144 }
145}
146
147static u32 __init ati_sbx00_rev(int num, int slot, int func)
148{
149 u32 d;
150
151 d = read_pci_config(num, slot, func, 0x8);
152 d &= 0xff;
153
154 return d;
155}
156
157static void __init ati_bugs_contd(int num, int slot, int func)
158{
159 u32 d, rev;
160
161 rev = ati_sbx00_rev(num, slot, func);
162 if (rev >= 0x40)
163 acpi_fix_pin2_polarity = 1;
164
165 /*
166 * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
167 * SB700: revisions 0x39, 0x3a, ...
168 * SB800: revisions 0x40, 0x41, ...
169 */
170 if (rev >= 0x39)
171 return;
172
173 if (acpi_use_timer_override)
174 return;
175
176 /* check for IRQ0 interrupt swap */
177 d = read_pci_config(num, slot, func, 0x64);
178 if (!(d & (1<<14)))
179 acpi_skip_timer_override = 1;
180
181 if (acpi_skip_timer_override) {
182 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
183 printk(KERN_INFO "Ignoring ACPI timer override.\n");
184 printk(KERN_INFO "If you got timer trouble "
185 "try acpi_use_timer_override\n");
186 }
187}
188#else
189static void __init ati_bugs(int num, int slot, int func)
190{
191}
192
193static void __init ati_bugs_contd(int num, int slot, int func)
194{
195}
196#endif
197
198static void __init intel_remapping_check(int num, int slot, int func)
199{
200 u8 revision;
201 u16 device;
202
203 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
204 revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
205
206 /*
207 * Revision <= 13 of all triggering devices id in this quirk
208 * have a problem draining interrupts when irq remapping is
209 * enabled, and should be flagged as broken. Additionally
210 * revision 0x22 of device id 0x3405 has this problem.
211 */
212 if (revision <= 0x13)
213 set_irq_remapping_broken();
214 else if (device == 0x3405 && revision == 0x22)
215 set_irq_remapping_broken();
216}
217
218/*
219 * Systems with Intel graphics controllers set aside memory exclusively
220 * for gfx driver use. This memory is not marked in the E820 as reserved
221 * or as RAM, and so is subject to overlap from E820 manipulation later
222 * in the boot process. On some systems, MMIO space is allocated on top,
223 * despite the efforts of the "RAM buffer" approach, which simply rounds
224 * memory boundaries up to 64M to try to catch space that may decode
225 * as RAM and so is not suitable for MMIO.
226 *
227 * And yes, so far on current devices the base addr is always under 4G.
228 */
229static u32 __init intel_stolen_base(int num, int slot, int func, size_t stolen_size)
230{
231 u32 base;
232
233 /*
234 * For the PCI IDs in this quirk, the stolen base is always
235 * in 0x5c, aka the BDSM register (yes that's really what
236 * it's called).
237 */
238 base = read_pci_config(num, slot, func, 0x5c);
239 base &= ~((1<<20) - 1);
240
241 return base;
242}
243
244#define KB(x) ((x) * 1024UL)
245#define MB(x) (KB (KB (x)))
246#define GB(x) (MB (KB (x)))
247
248static size_t __init i830_tseg_size(void)
249{
250 u8 tmp = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
251
252 if (!(tmp & TSEG_ENABLE))
253 return 0;
254
255 if (tmp & I830_TSEG_SIZE_1M)
256 return MB(1);
257 else
258 return KB(512);
259}
260
261static size_t __init i845_tseg_size(void)
262{
263 u8 tmp = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
264
265 if (!(tmp & TSEG_ENABLE))
266 return 0;
267
268 switch (tmp & I845_TSEG_SIZE_MASK) {
269 case I845_TSEG_SIZE_512K:
270 return KB(512);
271 case I845_TSEG_SIZE_1M:
272 return MB(1);
273 default:
274 WARN_ON(1);
275 return 0;
276 }
277}
278
279static size_t __init i85x_tseg_size(void)
280{
281 u8 tmp = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
282
283 if (!(tmp & TSEG_ENABLE))
284 return 0;
285
286 return MB(1);
287}
288
289static size_t __init i830_mem_size(void)
290{
291 return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
292}
293
294static size_t __init i85x_mem_size(void)
295{
296 return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
297}
298
299/*
300 * On 830/845/85x the stolen memory base isn't available in any
301 * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
302 */
303static u32 __init i830_stolen_base(int num, int slot, int func, size_t stolen_size)
304{
305 return i830_mem_size() - i830_tseg_size() - stolen_size;
306}
307
308static u32 __init i845_stolen_base(int num, int slot, int func, size_t stolen_size)
309{
310 return i830_mem_size() - i845_tseg_size() - stolen_size;
311}
312
313static u32 __init i85x_stolen_base(int num, int slot, int func, size_t stolen_size)
314{
315 return i85x_mem_size() - i85x_tseg_size() - stolen_size;
316}
317
318static u32 __init i865_stolen_base(int num, int slot, int func, size_t stolen_size)
319{
320 /*
321 * FIXME is the graphics stolen memory region
322 * always at TOUD? Ie. is it always the last
323 * one to be allocated by the BIOS?
324 */
325 return read_pci_config_16(0, 0, 0, I865_TOUD) << 16;
326}
327
328static size_t __init i830_stolen_size(int num, int slot, int func)
329{
330 size_t stolen_size;
331 u16 gmch_ctrl;
332
333 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
334
335 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
336 case I830_GMCH_GMS_STOLEN_512:
337 stolen_size = KB(512);
338 break;
339 case I830_GMCH_GMS_STOLEN_1024:
340 stolen_size = MB(1);
341 break;
342 case I830_GMCH_GMS_STOLEN_8192:
343 stolen_size = MB(8);
344 break;
345 case I830_GMCH_GMS_LOCAL:
346 /* local memory isn't part of the normal address space */
347 stolen_size = 0;
348 break;
349 default:
350 return 0;
351 }
352
353 return stolen_size;
354}
355
356static size_t __init gen3_stolen_size(int num, int slot, int func)
357{
358 size_t stolen_size;
359 u16 gmch_ctrl;
360
361 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
362
363 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
364 case I855_GMCH_GMS_STOLEN_1M:
365 stolen_size = MB(1);
366 break;
367 case I855_GMCH_GMS_STOLEN_4M:
368 stolen_size = MB(4);
369 break;
370 case I855_GMCH_GMS_STOLEN_8M:
371 stolen_size = MB(8);
372 break;
373 case I855_GMCH_GMS_STOLEN_16M:
374 stolen_size = MB(16);
375 break;
376 case I855_GMCH_GMS_STOLEN_32M:
377 stolen_size = MB(32);
378 break;
379 case I915_GMCH_GMS_STOLEN_48M:
380 stolen_size = MB(48);
381 break;
382 case I915_GMCH_GMS_STOLEN_64M:
383 stolen_size = MB(64);
384 break;
385 case G33_GMCH_GMS_STOLEN_128M:
386 stolen_size = MB(128);
387 break;
388 case G33_GMCH_GMS_STOLEN_256M:
389 stolen_size = MB(256);
390 break;
391 case INTEL_GMCH_GMS_STOLEN_96M:
392 stolen_size = MB(96);
393 break;
394 case INTEL_GMCH_GMS_STOLEN_160M:
395 stolen_size = MB(160);
396 break;
397 case INTEL_GMCH_GMS_STOLEN_224M:
398 stolen_size = MB(224);
399 break;
400 case INTEL_GMCH_GMS_STOLEN_352M:
401 stolen_size = MB(352);
402 break;
403 default:
404 stolen_size = 0;
405 break;
406 }
407
408 return stolen_size;
409}
410
411static size_t __init gen6_stolen_size(int num, int slot, int func)
412{
413 u16 gmch_ctrl;
414
415 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
416 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
417 gmch_ctrl &= SNB_GMCH_GMS_MASK;
418
419 return gmch_ctrl << 25; /* 32 MB units */
420}
421
422static size_t gen8_stolen_size(int num, int slot, int func)
423{
424 u16 gmch_ctrl;
425
426 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
427 gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
428 gmch_ctrl &= BDW_GMCH_GMS_MASK;
429 return gmch_ctrl << 25; /* 32 MB units */
430}
431
432
433struct intel_stolen_funcs {
434 size_t (*size)(int num, int slot, int func);
435 u32 (*base)(int num, int slot, int func, size_t size);
436};
437
438static const struct intel_stolen_funcs i830_stolen_funcs = {
439 .base = i830_stolen_base,
440 .size = i830_stolen_size,
441};
442
443static const struct intel_stolen_funcs i845_stolen_funcs = {
444 .base = i845_stolen_base,
445 .size = i830_stolen_size,
446};
447
448static const struct intel_stolen_funcs i85x_stolen_funcs = {
449 .base = i85x_stolen_base,
450 .size = gen3_stolen_size,
451};
452
453static const struct intel_stolen_funcs i865_stolen_funcs = {
454 .base = i865_stolen_base,
455 .size = gen3_stolen_size,
456};
457
458static const struct intel_stolen_funcs gen3_stolen_funcs = {
459 .base = intel_stolen_base,
460 .size = gen3_stolen_size,
461};
462
463static const struct intel_stolen_funcs gen6_stolen_funcs = {
464 .base = intel_stolen_base,
465 .size = gen6_stolen_size,
466};
467
468static const struct intel_stolen_funcs gen8_stolen_funcs = {
469 .base = intel_stolen_base,
470 .size = gen8_stolen_size,
471};
472
473static struct pci_device_id intel_stolen_ids[] __initdata = {
474 INTEL_I830_IDS(&i830_stolen_funcs),
475 INTEL_I845G_IDS(&i845_stolen_funcs),
476 INTEL_I85X_IDS(&i85x_stolen_funcs),
477 INTEL_I865G_IDS(&i865_stolen_funcs),
478 INTEL_I915G_IDS(&gen3_stolen_funcs),
479 INTEL_I915GM_IDS(&gen3_stolen_funcs),
480 INTEL_I945G_IDS(&gen3_stolen_funcs),
481 INTEL_I945GM_IDS(&gen3_stolen_funcs),
482 INTEL_VLV_M_IDS(&gen6_stolen_funcs),
483 INTEL_VLV_D_IDS(&gen6_stolen_funcs),
484 INTEL_PINEVIEW_IDS(&gen3_stolen_funcs),
485 INTEL_I965G_IDS(&gen3_stolen_funcs),
486 INTEL_G33_IDS(&gen3_stolen_funcs),
487 INTEL_I965GM_IDS(&gen3_stolen_funcs),
488 INTEL_GM45_IDS(&gen3_stolen_funcs),
489 INTEL_G45_IDS(&gen3_stolen_funcs),
490 INTEL_IRONLAKE_D_IDS(&gen3_stolen_funcs),
491 INTEL_IRONLAKE_M_IDS(&gen3_stolen_funcs),
492 INTEL_SNB_D_IDS(&gen6_stolen_funcs),
493 INTEL_SNB_M_IDS(&gen6_stolen_funcs),
494 INTEL_IVB_M_IDS(&gen6_stolen_funcs),
495 INTEL_IVB_D_IDS(&gen6_stolen_funcs),
496 INTEL_HSW_D_IDS(&gen6_stolen_funcs),
497 INTEL_HSW_M_IDS(&gen6_stolen_funcs),
498 INTEL_BDW_M_IDS(&gen8_stolen_funcs),
499 INTEL_BDW_D_IDS(&gen8_stolen_funcs)
500};
501
502static void __init intel_graphics_stolen(int num, int slot, int func)
503{
504 size_t size;
505 int i;
506 u32 start;
507 u16 device, subvendor, subdevice;
508
509 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
510 subvendor = read_pci_config_16(num, slot, func,
511 PCI_SUBSYSTEM_VENDOR_ID);
512 subdevice = read_pci_config_16(num, slot, func, PCI_SUBSYSTEM_ID);
513
514 for (i = 0; i < ARRAY_SIZE(intel_stolen_ids); i++) {
515 if (intel_stolen_ids[i].device == device) {
516 const struct intel_stolen_funcs *stolen_funcs =
517 (const struct intel_stolen_funcs *)intel_stolen_ids[i].driver_data;
518 size = stolen_funcs->size(num, slot, func);
519 start = stolen_funcs->base(num, slot, func, size);
520 if (size && start) {
521 printk(KERN_INFO "Reserving Intel graphics stolen memory at 0x%x-0x%x\n",
522 start, start + (u32)size - 1);
523 /* Mark this space as reserved */
524 e820_add_region(start, size, E820_RESERVED);
525 sanitize_e820_map(e820.map,
526 ARRAY_SIZE(e820.map),
527 &e820.nr_map);
528 }
529 return;
530 }
531 }
532}
533
534static void __init force_disable_hpet(int num, int slot, int func)
535{
536#ifdef CONFIG_HPET_TIMER
537 boot_hpet_disable = 1;
538 pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n");
539#endif
540}
541
542
543#define QFLAG_APPLY_ONCE 0x1
544#define QFLAG_APPLIED 0x2
545#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
546struct chipset {
547 u32 vendor;
548 u32 device;
549 u32 class;
550 u32 class_mask;
551 u32 flags;
552 void (*f)(int num, int slot, int func);
553};
554
555/*
556 * Only works for devices on the root bus. If you add any devices
557 * not on bus 0 readd another loop level in early_quirks(). But
558 * be careful because at least the Nvidia quirk here relies on
559 * only matching on bus 0.
560 */
561static struct chipset early_qrk[] __initdata = {
562 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
563 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
564 { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
565 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
566 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
567 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
568 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
569 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
570 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
571 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
572 { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
573 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
574 { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
575 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
576 { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
577 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
578 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
579 QFLAG_APPLY_ONCE, intel_graphics_stolen },
580 /*
581 * HPET on current version of Baytrail platform has accuracy
582 * problems, disable it for now:
583 */
584 { PCI_VENDOR_ID_INTEL, 0x0f00,
585 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
586 {}
587};
588
589/**
590 * check_dev_quirk - apply early quirks to a given PCI device
591 * @num: bus number
592 * @slot: slot number
593 * @func: PCI function
594 *
595 * Check the vendor & device ID against the early quirks table.
596 *
597 * If the device is single function, let early_quirks() know so we don't
598 * poke at this device again.
599 */
600static int __init check_dev_quirk(int num, int slot, int func)
601{
602 u16 class;
603 u16 vendor;
604 u16 device;
605 u8 type;
606 int i;
607
608 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
609
610 if (class == 0xffff)
611 return -1; /* no class, treat as single function */
612
613 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
614
615 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
616
617 for (i = 0; early_qrk[i].f != NULL; i++) {
618 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
619 (early_qrk[i].vendor == vendor)) &&
620 ((early_qrk[i].device == PCI_ANY_ID) ||
621 (early_qrk[i].device == device)) &&
622 (!((early_qrk[i].class ^ class) &
623 early_qrk[i].class_mask))) {
624 if ((early_qrk[i].flags &
625 QFLAG_DONE) != QFLAG_DONE)
626 early_qrk[i].f(num, slot, func);
627 early_qrk[i].flags |= QFLAG_APPLIED;
628 }
629 }
630
631 type = read_pci_config_byte(num, slot, func,
632 PCI_HEADER_TYPE);
633 if (!(type & 0x80))
634 return -1;
635
636 return 0;
637}
638
639void __init early_quirks(void)
640{
641 int slot, func;
642
643 if (!early_pci_allowed())
644 return;
645
646 /* Poor man's PCI discovery */
647 /* Only scan the root bus */
648 for (slot = 0; slot < 32; slot++)
649 for (func = 0; func < 8; func++) {
650 /* Only probe function 0 on single fn devices */
651 if (check_dev_quirk(0, slot, func))
652 break;
653 }
654}
1/* Various workarounds for chipset bugs.
2 This code runs very early and can't use the regular PCI subsystem
3 The entries are keyed to PCI bridges which usually identify chipsets
4 uniquely.
5 This is only for whole classes of chipsets with specific problems which
6 need early invasive action (e.g. before the timers are initialized).
7 Most PCI device specific workarounds can be done later and should be
8 in standard PCI quirks
9 Mainboard specific bugs should be handled by DMI entries.
10 CPU specific bugs in setup.c */
11
12#include <linux/pci.h>
13#include <linux/acpi.h>
14#include <linux/delay.h>
15#include <linux/dmi.h>
16#include <linux/pci_ids.h>
17#include <linux/bcma/bcma.h>
18#include <linux/bcma/bcma_regs.h>
19#include <drm/i915_drm.h>
20#include <asm/pci-direct.h>
21#include <asm/dma.h>
22#include <asm/io_apic.h>
23#include <asm/apic.h>
24#include <asm/hpet.h>
25#include <asm/iommu.h>
26#include <asm/gart.h>
27#include <asm/irq_remapping.h>
28#include <asm/early_ioremap.h>
29
30#define dev_err(msg) pr_err("pci 0000:%02x:%02x.%d: %s", bus, slot, func, msg)
31
32static void __init fix_hypertransport_config(int num, int slot, int func)
33{
34 u32 htcfg;
35 /*
36 * we found a hypertransport bus
37 * make sure that we are broadcasting
38 * interrupts to all cpus on the ht bus
39 * if we're using extended apic ids
40 */
41 htcfg = read_pci_config(num, slot, func, 0x68);
42 if (htcfg & (1 << 18)) {
43 printk(KERN_INFO "Detected use of extended apic ids "
44 "on hypertransport bus\n");
45 if ((htcfg & (1 << 17)) == 0) {
46 printk(KERN_INFO "Enabling hypertransport extended "
47 "apic interrupt broadcast\n");
48 printk(KERN_INFO "Note this is a bios bug, "
49 "please contact your hw vendor\n");
50 htcfg |= (1 << 17);
51 write_pci_config(num, slot, func, 0x68, htcfg);
52 }
53 }
54
55
56}
57
58static void __init via_bugs(int num, int slot, int func)
59{
60#ifdef CONFIG_GART_IOMMU
61 if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
62 !gart_iommu_aperture_allowed) {
63 printk(KERN_INFO
64 "Looks like a VIA chipset. Disabling IOMMU."
65 " Override with iommu=allowed\n");
66 gart_iommu_aperture_disabled = 1;
67 }
68#endif
69}
70
71#ifdef CONFIG_ACPI
72#ifdef CONFIG_X86_IO_APIC
73
74static int __init nvidia_hpet_check(struct acpi_table_header *header)
75{
76 return 0;
77}
78#endif /* CONFIG_X86_IO_APIC */
79#endif /* CONFIG_ACPI */
80
81static void __init nvidia_bugs(int num, int slot, int func)
82{
83#ifdef CONFIG_ACPI
84#ifdef CONFIG_X86_IO_APIC
85 /*
86 * Only applies to Nvidia root ports (bus 0) and not to
87 * Nvidia graphics cards with PCI ports on secondary buses.
88 */
89 if (num)
90 return;
91
92 /*
93 * All timer overrides on Nvidia are
94 * wrong unless HPET is enabled.
95 * Unfortunately that's not true on many Asus boards.
96 * We don't know yet how to detect this automatically, but
97 * at least allow a command line override.
98 */
99 if (acpi_use_timer_override)
100 return;
101
102 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
103 acpi_skip_timer_override = 1;
104 printk(KERN_INFO "Nvidia board "
105 "detected. Ignoring ACPI "
106 "timer override.\n");
107 printk(KERN_INFO "If you got timer trouble "
108 "try acpi_use_timer_override\n");
109 }
110#endif
111#endif
112 /* RED-PEN skip them on mptables too? */
113
114}
115
116#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
117static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
118{
119 u32 d;
120 u8 b;
121
122 b = read_pci_config_byte(num, slot, func, 0xac);
123 b &= ~(1<<5);
124 write_pci_config_byte(num, slot, func, 0xac, b);
125
126 d = read_pci_config(num, slot, func, 0x70);
127 d |= 1<<8;
128 write_pci_config(num, slot, func, 0x70, d);
129
130 d = read_pci_config(num, slot, func, 0x8);
131 d &= 0xff;
132 return d;
133}
134
135static void __init ati_bugs(int num, int slot, int func)
136{
137 u32 d;
138 u8 b;
139
140 if (acpi_use_timer_override)
141 return;
142
143 d = ati_ixp4x0_rev(num, slot, func);
144 if (d < 0x82)
145 acpi_skip_timer_override = 1;
146 else {
147 /* check for IRQ0 interrupt swap */
148 outb(0x72, 0xcd6); b = inb(0xcd7);
149 if (!(b & 0x2))
150 acpi_skip_timer_override = 1;
151 }
152
153 if (acpi_skip_timer_override) {
154 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
155 printk(KERN_INFO "Ignoring ACPI timer override.\n");
156 printk(KERN_INFO "If you got timer trouble "
157 "try acpi_use_timer_override\n");
158 }
159}
160
161static u32 __init ati_sbx00_rev(int num, int slot, int func)
162{
163 u32 d;
164
165 d = read_pci_config(num, slot, func, 0x8);
166 d &= 0xff;
167
168 return d;
169}
170
171static void __init ati_bugs_contd(int num, int slot, int func)
172{
173 u32 d, rev;
174
175 rev = ati_sbx00_rev(num, slot, func);
176 if (rev >= 0x40)
177 acpi_fix_pin2_polarity = 1;
178
179 /*
180 * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
181 * SB700: revisions 0x39, 0x3a, ...
182 * SB800: revisions 0x40, 0x41, ...
183 */
184 if (rev >= 0x39)
185 return;
186
187 if (acpi_use_timer_override)
188 return;
189
190 /* check for IRQ0 interrupt swap */
191 d = read_pci_config(num, slot, func, 0x64);
192 if (!(d & (1<<14)))
193 acpi_skip_timer_override = 1;
194
195 if (acpi_skip_timer_override) {
196 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
197 printk(KERN_INFO "Ignoring ACPI timer override.\n");
198 printk(KERN_INFO "If you got timer trouble "
199 "try acpi_use_timer_override\n");
200 }
201}
202#else
203static void __init ati_bugs(int num, int slot, int func)
204{
205}
206
207static void __init ati_bugs_contd(int num, int slot, int func)
208{
209}
210#endif
211
212static void __init intel_remapping_check(int num, int slot, int func)
213{
214 u8 revision;
215 u16 device;
216
217 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
218 revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
219
220 /*
221 * Revision <= 13 of all triggering devices id in this quirk
222 * have a problem draining interrupts when irq remapping is
223 * enabled, and should be flagged as broken. Additionally
224 * revision 0x22 of device id 0x3405 has this problem.
225 */
226 if (revision <= 0x13)
227 set_irq_remapping_broken();
228 else if (device == 0x3405 && revision == 0x22)
229 set_irq_remapping_broken();
230}
231
232/*
233 * Systems with Intel graphics controllers set aside memory exclusively
234 * for gfx driver use. This memory is not marked in the E820 as reserved
235 * or as RAM, and so is subject to overlap from E820 manipulation later
236 * in the boot process. On some systems, MMIO space is allocated on top,
237 * despite the efforts of the "RAM buffer" approach, which simply rounds
238 * memory boundaries up to 64M to try to catch space that may decode
239 * as RAM and so is not suitable for MMIO.
240 */
241
242#define KB(x) ((x) * 1024UL)
243#define MB(x) (KB (KB (x)))
244
245static size_t __init i830_tseg_size(void)
246{
247 u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
248
249 if (!(esmramc & TSEG_ENABLE))
250 return 0;
251
252 if (esmramc & I830_TSEG_SIZE_1M)
253 return MB(1);
254 else
255 return KB(512);
256}
257
258static size_t __init i845_tseg_size(void)
259{
260 u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
261 u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK;
262
263 if (!(esmramc & TSEG_ENABLE))
264 return 0;
265
266 switch (tseg_size) {
267 case I845_TSEG_SIZE_512K: return KB(512);
268 case I845_TSEG_SIZE_1M: return MB(1);
269 default:
270 WARN(1, "Unknown ESMRAMC value: %x!\n", esmramc);
271 }
272 return 0;
273}
274
275static size_t __init i85x_tseg_size(void)
276{
277 u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
278
279 if (!(esmramc & TSEG_ENABLE))
280 return 0;
281
282 return MB(1);
283}
284
285static size_t __init i830_mem_size(void)
286{
287 return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
288}
289
290static size_t __init i85x_mem_size(void)
291{
292 return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
293}
294
295/*
296 * On 830/845/85x the stolen memory base isn't available in any
297 * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
298 */
299static phys_addr_t __init i830_stolen_base(int num, int slot, int func,
300 size_t stolen_size)
301{
302 return (phys_addr_t)i830_mem_size() - i830_tseg_size() - stolen_size;
303}
304
305static phys_addr_t __init i845_stolen_base(int num, int slot, int func,
306 size_t stolen_size)
307{
308 return (phys_addr_t)i830_mem_size() - i845_tseg_size() - stolen_size;
309}
310
311static phys_addr_t __init i85x_stolen_base(int num, int slot, int func,
312 size_t stolen_size)
313{
314 return (phys_addr_t)i85x_mem_size() - i85x_tseg_size() - stolen_size;
315}
316
317static phys_addr_t __init i865_stolen_base(int num, int slot, int func,
318 size_t stolen_size)
319{
320 u16 toud = 0;
321
322 toud = read_pci_config_16(0, 0, 0, I865_TOUD);
323
324 return (phys_addr_t)(toud << 16) + i845_tseg_size();
325}
326
327static phys_addr_t __init gen3_stolen_base(int num, int slot, int func,
328 size_t stolen_size)
329{
330 u32 bsm;
331
332 /* Almost universally we can find the Graphics Base of Stolen Memory
333 * at register BSM (0x5c) in the igfx configuration space. On a few
334 * (desktop) machines this is also mirrored in the bridge device at
335 * different locations, or in the MCHBAR.
336 */
337 bsm = read_pci_config(num, slot, func, INTEL_BSM);
338
339 return (phys_addr_t)bsm & INTEL_BSM_MASK;
340}
341
342static size_t __init i830_stolen_size(int num, int slot, int func)
343{
344 u16 gmch_ctrl;
345 u16 gms;
346
347 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
348 gms = gmch_ctrl & I830_GMCH_GMS_MASK;
349
350 switch (gms) {
351 case I830_GMCH_GMS_STOLEN_512: return KB(512);
352 case I830_GMCH_GMS_STOLEN_1024: return MB(1);
353 case I830_GMCH_GMS_STOLEN_8192: return MB(8);
354 /* local memory isn't part of the normal address space */
355 case I830_GMCH_GMS_LOCAL: return 0;
356 default:
357 WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
358 }
359
360 return 0;
361}
362
363static size_t __init gen3_stolen_size(int num, int slot, int func)
364{
365 u16 gmch_ctrl;
366 u16 gms;
367
368 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
369 gms = gmch_ctrl & I855_GMCH_GMS_MASK;
370
371 switch (gms) {
372 case I855_GMCH_GMS_STOLEN_1M: return MB(1);
373 case I855_GMCH_GMS_STOLEN_4M: return MB(4);
374 case I855_GMCH_GMS_STOLEN_8M: return MB(8);
375 case I855_GMCH_GMS_STOLEN_16M: return MB(16);
376 case I855_GMCH_GMS_STOLEN_32M: return MB(32);
377 case I915_GMCH_GMS_STOLEN_48M: return MB(48);
378 case I915_GMCH_GMS_STOLEN_64M: return MB(64);
379 case G33_GMCH_GMS_STOLEN_128M: return MB(128);
380 case G33_GMCH_GMS_STOLEN_256M: return MB(256);
381 case INTEL_GMCH_GMS_STOLEN_96M: return MB(96);
382 case INTEL_GMCH_GMS_STOLEN_160M:return MB(160);
383 case INTEL_GMCH_GMS_STOLEN_224M:return MB(224);
384 case INTEL_GMCH_GMS_STOLEN_352M:return MB(352);
385 default:
386 WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
387 }
388
389 return 0;
390}
391
392static size_t __init gen6_stolen_size(int num, int slot, int func)
393{
394 u16 gmch_ctrl;
395 u16 gms;
396
397 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
398 gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
399
400 return (size_t)gms * MB(32);
401}
402
403static size_t __init gen8_stolen_size(int num, int slot, int func)
404{
405 u16 gmch_ctrl;
406 u16 gms;
407
408 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
409 gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
410
411 return (size_t)gms * MB(32);
412}
413
414static size_t __init chv_stolen_size(int num, int slot, int func)
415{
416 u16 gmch_ctrl;
417 u16 gms;
418
419 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
420 gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
421
422 /*
423 * 0x0 to 0x10: 32MB increments starting at 0MB
424 * 0x11 to 0x16: 4MB increments starting at 8MB
425 * 0x17 to 0x1d: 4MB increments start at 36MB
426 */
427 if (gms < 0x11)
428 return (size_t)gms * MB(32);
429 else if (gms < 0x17)
430 return (size_t)(gms - 0x11 + 2) * MB(4);
431 else
432 return (size_t)(gms - 0x17 + 9) * MB(4);
433}
434
435static size_t __init gen9_stolen_size(int num, int slot, int func)
436{
437 u16 gmch_ctrl;
438 u16 gms;
439
440 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
441 gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
442
443 /* 0x0 to 0xef: 32MB increments starting at 0MB */
444 /* 0xf0 to 0xfe: 4MB increments starting at 4MB */
445 if (gms < 0xf0)
446 return (size_t)gms * MB(32);
447 else
448 return (size_t)(gms - 0xf0 + 1) * MB(4);
449}
450
451struct intel_early_ops {
452 size_t (*stolen_size)(int num, int slot, int func);
453 phys_addr_t (*stolen_base)(int num, int slot, int func, size_t size);
454};
455
456static const struct intel_early_ops i830_early_ops __initconst = {
457 .stolen_base = i830_stolen_base,
458 .stolen_size = i830_stolen_size,
459};
460
461static const struct intel_early_ops i845_early_ops __initconst = {
462 .stolen_base = i845_stolen_base,
463 .stolen_size = i830_stolen_size,
464};
465
466static const struct intel_early_ops i85x_early_ops __initconst = {
467 .stolen_base = i85x_stolen_base,
468 .stolen_size = gen3_stolen_size,
469};
470
471static const struct intel_early_ops i865_early_ops __initconst = {
472 .stolen_base = i865_stolen_base,
473 .stolen_size = gen3_stolen_size,
474};
475
476static const struct intel_early_ops gen3_early_ops __initconst = {
477 .stolen_base = gen3_stolen_base,
478 .stolen_size = gen3_stolen_size,
479};
480
481static const struct intel_early_ops gen6_early_ops __initconst = {
482 .stolen_base = gen3_stolen_base,
483 .stolen_size = gen6_stolen_size,
484};
485
486static const struct intel_early_ops gen8_early_ops __initconst = {
487 .stolen_base = gen3_stolen_base,
488 .stolen_size = gen8_stolen_size,
489};
490
491static const struct intel_early_ops gen9_early_ops __initconst = {
492 .stolen_base = gen3_stolen_base,
493 .stolen_size = gen9_stolen_size,
494};
495
496static const struct intel_early_ops chv_early_ops __initconst = {
497 .stolen_base = gen3_stolen_base,
498 .stolen_size = chv_stolen_size,
499};
500
501static const struct pci_device_id intel_early_ids[] __initconst = {
502 INTEL_I830_IDS(&i830_early_ops),
503 INTEL_I845G_IDS(&i845_early_ops),
504 INTEL_I85X_IDS(&i85x_early_ops),
505 INTEL_I865G_IDS(&i865_early_ops),
506 INTEL_I915G_IDS(&gen3_early_ops),
507 INTEL_I915GM_IDS(&gen3_early_ops),
508 INTEL_I945G_IDS(&gen3_early_ops),
509 INTEL_I945GM_IDS(&gen3_early_ops),
510 INTEL_VLV_IDS(&gen6_early_ops),
511 INTEL_PINEVIEW_IDS(&gen3_early_ops),
512 INTEL_I965G_IDS(&gen3_early_ops),
513 INTEL_G33_IDS(&gen3_early_ops),
514 INTEL_I965GM_IDS(&gen3_early_ops),
515 INTEL_GM45_IDS(&gen3_early_ops),
516 INTEL_G45_IDS(&gen3_early_ops),
517 INTEL_IRONLAKE_D_IDS(&gen3_early_ops),
518 INTEL_IRONLAKE_M_IDS(&gen3_early_ops),
519 INTEL_SNB_D_IDS(&gen6_early_ops),
520 INTEL_SNB_M_IDS(&gen6_early_ops),
521 INTEL_IVB_M_IDS(&gen6_early_ops),
522 INTEL_IVB_D_IDS(&gen6_early_ops),
523 INTEL_HSW_IDS(&gen6_early_ops),
524 INTEL_BDW_IDS(&gen8_early_ops),
525 INTEL_CHV_IDS(&chv_early_ops),
526 INTEL_SKL_IDS(&gen9_early_ops),
527 INTEL_BXT_IDS(&gen9_early_ops),
528 INTEL_KBL_IDS(&gen9_early_ops),
529};
530
531static void __init
532intel_graphics_stolen(int num, int slot, int func,
533 const struct intel_early_ops *early_ops)
534{
535 phys_addr_t base, end;
536 size_t size;
537
538 size = early_ops->stolen_size(num, slot, func);
539 base = early_ops->stolen_base(num, slot, func, size);
540
541 if (!size || !base)
542 return;
543
544 end = base + size - 1;
545 printk(KERN_INFO "Reserving Intel graphics memory at %pa-%pa\n",
546 &base, &end);
547
548 /* Mark this space as reserved */
549 e820_add_region(base, size, E820_RESERVED);
550 sanitize_e820_map(e820->map, ARRAY_SIZE(e820->map), &e820->nr_map);
551}
552
553static void __init intel_graphics_quirks(int num, int slot, int func)
554{
555 const struct intel_early_ops *early_ops;
556 u16 device;
557 int i;
558
559 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
560
561 for (i = 0; i < ARRAY_SIZE(intel_early_ids); i++) {
562 kernel_ulong_t driver_data = intel_early_ids[i].driver_data;
563
564 if (intel_early_ids[i].device != device)
565 continue;
566
567 early_ops = (typeof(early_ops))driver_data;
568
569 intel_graphics_stolen(num, slot, func, early_ops);
570
571 return;
572 }
573}
574
575static void __init force_disable_hpet(int num, int slot, int func)
576{
577#ifdef CONFIG_HPET_TIMER
578 boot_hpet_disable = true;
579 pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n");
580#endif
581}
582
583#define BCM4331_MMIO_SIZE 16384
584#define BCM4331_PM_CAP 0x40
585#define bcma_aread32(reg) ioread32(mmio + 1 * BCMA_CORE_SIZE + reg)
586#define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg)
587
588static void __init apple_airport_reset(int bus, int slot, int func)
589{
590 void __iomem *mmio;
591 u16 pmcsr;
592 u64 addr;
593 int i;
594
595 if (!dmi_match(DMI_SYS_VENDOR, "Apple Inc."))
596 return;
597
598 /* Card may have been put into PCI_D3hot by grub quirk */
599 pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
600
601 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
602 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
603 write_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL, pmcsr);
604 mdelay(10);
605
606 pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
607 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
608 dev_err("Cannot power up Apple AirPort card\n");
609 return;
610 }
611 }
612
613 addr = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
614 addr |= (u64)read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_1) << 32;
615 addr &= PCI_BASE_ADDRESS_MEM_MASK;
616
617 mmio = early_ioremap(addr, BCM4331_MMIO_SIZE);
618 if (!mmio) {
619 dev_err("Cannot iomap Apple AirPort card\n");
620 return;
621 }
622
623 pr_info("Resetting Apple AirPort card (left enabled by EFI)\n");
624
625 for (i = 0; bcma_aread32(BCMA_RESET_ST) && i < 30; i++)
626 udelay(10);
627
628 bcma_awrite32(BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
629 bcma_aread32(BCMA_RESET_CTL);
630 udelay(1);
631
632 bcma_awrite32(BCMA_RESET_CTL, 0);
633 bcma_aread32(BCMA_RESET_CTL);
634 udelay(10);
635
636 early_iounmap(mmio, BCM4331_MMIO_SIZE);
637}
638
639#define QFLAG_APPLY_ONCE 0x1
640#define QFLAG_APPLIED 0x2
641#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
642struct chipset {
643 u32 vendor;
644 u32 device;
645 u32 class;
646 u32 class_mask;
647 u32 flags;
648 void (*f)(int num, int slot, int func);
649};
650
651static struct chipset early_qrk[] __initdata = {
652 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
653 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
654 { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
655 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
656 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
657 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
658 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
659 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
660 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
661 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
662 { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
663 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
664 { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
665 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
666 { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
667 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
668 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
669 QFLAG_APPLY_ONCE, intel_graphics_quirks },
670 /*
671 * HPET on the current version of the Baytrail platform has accuracy
672 * problems: it will halt in deep idle state - so we disable it.
673 *
674 * More details can be found in section 18.10.1.3 of the datasheet:
675 *
676 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf
677 */
678 { PCI_VENDOR_ID_INTEL, 0x0f00,
679 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
680 { PCI_VENDOR_ID_BROADCOM, 0x4331,
681 PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset},
682 {}
683};
684
685static void __init early_pci_scan_bus(int bus);
686
687/**
688 * check_dev_quirk - apply early quirks to a given PCI device
689 * @num: bus number
690 * @slot: slot number
691 * @func: PCI function
692 *
693 * Check the vendor & device ID against the early quirks table.
694 *
695 * If the device is single function, let early_pci_scan_bus() know so we don't
696 * poke at this device again.
697 */
698static int __init check_dev_quirk(int num, int slot, int func)
699{
700 u16 class;
701 u16 vendor;
702 u16 device;
703 u8 type;
704 u8 sec;
705 int i;
706
707 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
708
709 if (class == 0xffff)
710 return -1; /* no class, treat as single function */
711
712 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
713
714 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
715
716 for (i = 0; early_qrk[i].f != NULL; i++) {
717 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
718 (early_qrk[i].vendor == vendor)) &&
719 ((early_qrk[i].device == PCI_ANY_ID) ||
720 (early_qrk[i].device == device)) &&
721 (!((early_qrk[i].class ^ class) &
722 early_qrk[i].class_mask))) {
723 if ((early_qrk[i].flags &
724 QFLAG_DONE) != QFLAG_DONE)
725 early_qrk[i].f(num, slot, func);
726 early_qrk[i].flags |= QFLAG_APPLIED;
727 }
728 }
729
730 type = read_pci_config_byte(num, slot, func,
731 PCI_HEADER_TYPE);
732
733 if ((type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
734 sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS);
735 if (sec > num)
736 early_pci_scan_bus(sec);
737 }
738
739 if (!(type & 0x80))
740 return -1;
741
742 return 0;
743}
744
745static void __init early_pci_scan_bus(int bus)
746{
747 int slot, func;
748
749 /* Poor man's PCI discovery */
750 for (slot = 0; slot < 32; slot++)
751 for (func = 0; func < 8; func++) {
752 /* Only probe function 0 on single fn devices */
753 if (check_dev_quirk(bus, slot, func))
754 break;
755 }
756}
757
758void __init early_quirks(void)
759{
760 if (!early_pci_allowed())
761 return;
762
763 early_pci_scan_bus(0);
764}