1/*
 2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
 3 *
 4 * Loongson 1 Clock Register Definitions.
 5 *
 6 * This program is free software; you can redistribute	it and/or modify it
 7 * under  the terms of	the GNU General	 Public License as published by the
 8 * Free Software Foundation;  either version 2 of the  License, or (at your
 9 * option) any later version.
10 */
11
12#ifndef __ASM_MACH_LOONGSON32_REGS_CLK_H
13#define __ASM_MACH_LOONGSON32_REGS_CLK_H
14
15#define LS1X_CLK_REG(x) \
16		((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
17
18#define LS1X_CLK_PLL_FREQ		LS1X_CLK_REG(0x0)
19#define LS1X_CLK_PLL_DIV		LS1X_CLK_REG(0x4)
20
21#if defined(CONFIG_LOONGSON1_LS1B)
22/* Clock PLL Divisor Register Bits */
23#define DIV_DC_EN			BIT(31)
24#define DIV_DC_RST			BIT(30)
25#define DIV_CPU_EN			BIT(25)
26#define DIV_CPU_RST			BIT(24)
27#define DIV_DDR_EN			BIT(19)
28#define DIV_DDR_RST			BIT(18)
29#define RST_DC_EN			BIT(5)
30#define RST_DC				BIT(4)
31#define RST_DDR_EN			BIT(3)
32#define RST_DDR				BIT(2)
33#define RST_CPU_EN			BIT(1)
34#define RST_CPU				BIT(0)
35
36#define DIV_DC_SHIFT			26
37#define DIV_CPU_SHIFT			20
38#define DIV_DDR_SHIFT			14
39
40#define DIV_DC_WIDTH			4
41#define DIV_CPU_WIDTH			4
42#define DIV_DDR_WIDTH			4
43
44#define BYPASS_DC_SHIFT			12
45#define BYPASS_DDR_SHIFT		10
46#define BYPASS_CPU_SHIFT		8
47
48#define BYPASS_DC_WIDTH			1
49#define BYPASS_DDR_WIDTH		1
50#define BYPASS_CPU_WIDTH		1
51
52#elif defined(CONFIG_LOONGSON1_LS1C)
53/* PLL/SDRAM Frequency configuration register Bits */
54#define PLL_VALID			BIT(31)
55#define FRAC_N				GENMASK(23, 16)
56#define RST_TIME			GENMASK(3, 2)
57#define SDRAM_DIV			GENMASK(1, 0)
58
59/* CPU/CAMERA/DC Frequency configuration register Bits */
60#define DIV_DC_EN			BIT(31)
61#define DIV_DC				GENMASK(30, 24)
62#define DIV_CAM_EN			BIT(23)
63#define DIV_CAM				GENMASK(22, 16)
64#define DIV_CPU_EN			BIT(15)
65#define DIV_CPU				GENMASK(14, 8)
66#define DIV_DC_SEL_EN			BIT(5)
67#define DIV_DC_SEL			BIT(4)
68#define DIV_CAM_SEL_EN			BIT(3)
69#define DIV_CAM_SEL			BIT(2)
70#define DIV_CPU_SEL_EN			BIT(1)
71#define DIV_CPU_SEL			BIT(0)
72
73#define DIV_DC_SHIFT			24
74#define DIV_CAM_SHIFT			16
75#define DIV_CPU_SHIFT			8
76#define DIV_DDR_SHIFT			0
77
78#define DIV_DC_WIDTH			7
79#define DIV_CAM_WIDTH			7
80#define DIV_CPU_WIDTH			7
81#define DIV_DDR_WIDTH			2
82
83#endif
84
85#endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */