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1/*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include "asix.h"
23
24#define PHY_MODE_MARVELL 0x0000
25#define MII_MARVELL_LED_CTRL 0x0018
26#define MII_MARVELL_STATUS 0x001b
27#define MII_MARVELL_CTRL 0x0014
28
29#define MARVELL_LED_MANUAL 0x0019
30
31#define MARVELL_STATUS_HWCFG 0x0004
32
33#define MARVELL_CTRL_TXDELAY 0x0002
34#define MARVELL_CTRL_RXDELAY 0x0080
35
36#define PHY_MODE_RTL8211CL 0x000C
37
38struct ax88172_int_data {
39 __le16 res1;
40 u8 link;
41 __le16 res2;
42 u8 status;
43 __le16 res3;
44} __packed;
45
46static void asix_status(struct usbnet *dev, struct urb *urb)
47{
48 struct ax88172_int_data *event;
49 int link;
50
51 if (urb->actual_length < 8)
52 return;
53
54 event = urb->transfer_buffer;
55 link = event->link & 0x01;
56 if (netif_carrier_ok(dev->net) != link) {
57 usbnet_link_change(dev, link, 1);
58 netdev_dbg(dev->net, "Link Status is: %d\n", link);
59 }
60}
61
62static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
63{
64 if (is_valid_ether_addr(addr)) {
65 memcpy(dev->net->dev_addr, addr, ETH_ALEN);
66 } else {
67 netdev_info(dev->net, "invalid hw address, using random\n");
68 eth_hw_addr_random(dev->net);
69 }
70}
71
72/* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
73static u32 asix_get_phyid(struct usbnet *dev)
74{
75 int phy_reg;
76 u32 phy_id;
77 int i;
78
79 /* Poll for the rare case the FW or phy isn't ready yet. */
80 for (i = 0; i < 100; i++) {
81 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
82 if (phy_reg != 0 && phy_reg != 0xFFFF)
83 break;
84 mdelay(1);
85 }
86
87 if (phy_reg <= 0 || phy_reg == 0xFFFF)
88 return 0;
89
90 phy_id = (phy_reg & 0xffff) << 16;
91
92 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
93 if (phy_reg < 0)
94 return 0;
95
96 phy_id |= (phy_reg & 0xffff);
97
98 return phy_id;
99}
100
101static u32 asix_get_link(struct net_device *net)
102{
103 struct usbnet *dev = netdev_priv(net);
104
105 return mii_link_ok(&dev->mii);
106}
107
108static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
109{
110 struct usbnet *dev = netdev_priv(net);
111
112 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
113}
114
115/* We need to override some ethtool_ops so we require our
116 own structure so we don't interfere with other usbnet
117 devices that may be connected at the same time. */
118static const struct ethtool_ops ax88172_ethtool_ops = {
119 .get_drvinfo = asix_get_drvinfo,
120 .get_link = asix_get_link,
121 .get_msglevel = usbnet_get_msglevel,
122 .set_msglevel = usbnet_set_msglevel,
123 .get_wol = asix_get_wol,
124 .set_wol = asix_set_wol,
125 .get_eeprom_len = asix_get_eeprom_len,
126 .get_eeprom = asix_get_eeprom,
127 .set_eeprom = asix_set_eeprom,
128 .get_settings = usbnet_get_settings,
129 .set_settings = usbnet_set_settings,
130 .nway_reset = usbnet_nway_reset,
131};
132
133static void ax88172_set_multicast(struct net_device *net)
134{
135 struct usbnet *dev = netdev_priv(net);
136 struct asix_data *data = (struct asix_data *)&dev->data;
137 u8 rx_ctl = 0x8c;
138
139 if (net->flags & IFF_PROMISC) {
140 rx_ctl |= 0x01;
141 } else if (net->flags & IFF_ALLMULTI ||
142 netdev_mc_count(net) > AX_MAX_MCAST) {
143 rx_ctl |= 0x02;
144 } else if (netdev_mc_empty(net)) {
145 /* just broadcast and directed */
146 } else {
147 /* We use the 20 byte dev->data
148 * for our 8 byte filter buffer
149 * to avoid allocating memory that
150 * is tricky to free later */
151 struct netdev_hw_addr *ha;
152 u32 crc_bits;
153
154 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
155
156 /* Build the multicast hash filter. */
157 netdev_for_each_mc_addr(ha, net) {
158 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
159 data->multi_filter[crc_bits >> 3] |=
160 1 << (crc_bits & 7);
161 }
162
163 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
164 AX_MCAST_FILTER_SIZE, data->multi_filter);
165
166 rx_ctl |= 0x10;
167 }
168
169 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
170}
171
172static int ax88172_link_reset(struct usbnet *dev)
173{
174 u8 mode;
175 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
176
177 mii_check_media(&dev->mii, 1, 1);
178 mii_ethtool_gset(&dev->mii, &ecmd);
179 mode = AX88172_MEDIUM_DEFAULT;
180
181 if (ecmd.duplex != DUPLEX_FULL)
182 mode |= ~AX88172_MEDIUM_FD;
183
184 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
185 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
186
187 asix_write_medium_mode(dev, mode);
188
189 return 0;
190}
191
192static const struct net_device_ops ax88172_netdev_ops = {
193 .ndo_open = usbnet_open,
194 .ndo_stop = usbnet_stop,
195 .ndo_start_xmit = usbnet_start_xmit,
196 .ndo_tx_timeout = usbnet_tx_timeout,
197 .ndo_change_mtu = usbnet_change_mtu,
198 .ndo_set_mac_address = eth_mac_addr,
199 .ndo_validate_addr = eth_validate_addr,
200 .ndo_do_ioctl = asix_ioctl,
201 .ndo_set_rx_mode = ax88172_set_multicast,
202};
203
204static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
205{
206 int ret = 0;
207 u8 buf[ETH_ALEN];
208 int i;
209 unsigned long gpio_bits = dev->driver_info->data;
210
211 usbnet_get_endpoints(dev,intf);
212
213 /* Toggle the GPIOs in a manufacturer/model specific way */
214 for (i = 2; i >= 0; i--) {
215 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
216 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL);
217 if (ret < 0)
218 goto out;
219 msleep(5);
220 }
221
222 ret = asix_write_rx_ctl(dev, 0x80);
223 if (ret < 0)
224 goto out;
225
226 /* Get the MAC address */
227 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
228 if (ret < 0) {
229 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
230 ret);
231 goto out;
232 }
233
234 asix_set_netdev_dev_addr(dev, buf);
235
236 /* Initialize MII structure */
237 dev->mii.dev = dev->net;
238 dev->mii.mdio_read = asix_mdio_read;
239 dev->mii.mdio_write = asix_mdio_write;
240 dev->mii.phy_id_mask = 0x3f;
241 dev->mii.reg_num_mask = 0x1f;
242 dev->mii.phy_id = asix_get_phy_addr(dev);
243
244 dev->net->netdev_ops = &ax88172_netdev_ops;
245 dev->net->ethtool_ops = &ax88172_ethtool_ops;
246 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
247 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
248
249 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
250 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
251 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
252 mii_nway_restart(&dev->mii);
253
254 return 0;
255
256out:
257 return ret;
258}
259
260static const struct ethtool_ops ax88772_ethtool_ops = {
261 .get_drvinfo = asix_get_drvinfo,
262 .get_link = asix_get_link,
263 .get_msglevel = usbnet_get_msglevel,
264 .set_msglevel = usbnet_set_msglevel,
265 .get_wol = asix_get_wol,
266 .set_wol = asix_set_wol,
267 .get_eeprom_len = asix_get_eeprom_len,
268 .get_eeprom = asix_get_eeprom,
269 .set_eeprom = asix_set_eeprom,
270 .get_settings = usbnet_get_settings,
271 .set_settings = usbnet_set_settings,
272 .nway_reset = usbnet_nway_reset,
273};
274
275static int ax88772_link_reset(struct usbnet *dev)
276{
277 u16 mode;
278 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
279
280 mii_check_media(&dev->mii, 1, 1);
281 mii_ethtool_gset(&dev->mii, &ecmd);
282 mode = AX88772_MEDIUM_DEFAULT;
283
284 if (ethtool_cmd_speed(&ecmd) != SPEED_100)
285 mode &= ~AX_MEDIUM_PS;
286
287 if (ecmd.duplex != DUPLEX_FULL)
288 mode &= ~AX_MEDIUM_FD;
289
290 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
291 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
292
293 asix_write_medium_mode(dev, mode);
294
295 return 0;
296}
297
298static int ax88772_reset(struct usbnet *dev)
299{
300 struct asix_data *data = (struct asix_data *)&dev->data;
301 int ret, embd_phy;
302 u16 rx_ctl;
303
304 ret = asix_write_gpio(dev,
305 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5);
306 if (ret < 0)
307 goto out;
308
309 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
310
311 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
312 if (ret < 0) {
313 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
314 goto out;
315 }
316
317 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
318 if (ret < 0)
319 goto out;
320
321 msleep(150);
322
323 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
324 if (ret < 0)
325 goto out;
326
327 msleep(150);
328
329 if (embd_phy) {
330 ret = asix_sw_reset(dev, AX_SWRESET_IPRL);
331 if (ret < 0)
332 goto out;
333 } else {
334 ret = asix_sw_reset(dev, AX_SWRESET_PRTE);
335 if (ret < 0)
336 goto out;
337 }
338
339 msleep(150);
340 rx_ctl = asix_read_rx_ctl(dev);
341 netdev_dbg(dev->net, "RX_CTL is 0x%04x after software reset\n", rx_ctl);
342 ret = asix_write_rx_ctl(dev, 0x0000);
343 if (ret < 0)
344 goto out;
345
346 rx_ctl = asix_read_rx_ctl(dev);
347 netdev_dbg(dev->net, "RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
348
349 ret = asix_sw_reset(dev, AX_SWRESET_PRL);
350 if (ret < 0)
351 goto out;
352
353 msleep(150);
354
355 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL);
356 if (ret < 0)
357 goto out;
358
359 msleep(150);
360
361 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
362 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
363 ADVERTISE_ALL | ADVERTISE_CSMA);
364 mii_nway_restart(&dev->mii);
365
366 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT);
367 if (ret < 0)
368 goto out;
369
370 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
371 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
372 AX88772_IPG2_DEFAULT, 0, NULL);
373 if (ret < 0) {
374 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
375 goto out;
376 }
377
378 /* Rewrite MAC address */
379 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
380 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
381 data->mac_addr);
382 if (ret < 0)
383 goto out;
384
385 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
386 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
387 if (ret < 0)
388 goto out;
389
390 rx_ctl = asix_read_rx_ctl(dev);
391 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
392 rx_ctl);
393
394 rx_ctl = asix_read_medium_status(dev);
395 netdev_dbg(dev->net,
396 "Medium Status is 0x%04x after all initializations\n",
397 rx_ctl);
398
399 return 0;
400
401out:
402 return ret;
403
404}
405
406static const struct net_device_ops ax88772_netdev_ops = {
407 .ndo_open = usbnet_open,
408 .ndo_stop = usbnet_stop,
409 .ndo_start_xmit = usbnet_start_xmit,
410 .ndo_tx_timeout = usbnet_tx_timeout,
411 .ndo_change_mtu = usbnet_change_mtu,
412 .ndo_set_mac_address = asix_set_mac_address,
413 .ndo_validate_addr = eth_validate_addr,
414 .ndo_do_ioctl = asix_ioctl,
415 .ndo_set_rx_mode = asix_set_multicast,
416};
417
418static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
419{
420 int ret, embd_phy, i;
421 u8 buf[ETH_ALEN];
422 u32 phyid;
423
424 usbnet_get_endpoints(dev,intf);
425
426 /* Get the MAC address */
427 if (dev->driver_info->data & FLAG_EEPROM_MAC) {
428 for (i = 0; i < (ETH_ALEN >> 1); i++) {
429 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x04 + i,
430 0, 2, buf + i * 2);
431 if (ret < 0)
432 break;
433 }
434 } else {
435 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
436 0, 0, ETH_ALEN, buf);
437 }
438
439 if (ret < 0) {
440 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
441 return ret;
442 }
443
444 asix_set_netdev_dev_addr(dev, buf);
445
446 /* Initialize MII structure */
447 dev->mii.dev = dev->net;
448 dev->mii.mdio_read = asix_mdio_read;
449 dev->mii.mdio_write = asix_mdio_write;
450 dev->mii.phy_id_mask = 0x1f;
451 dev->mii.reg_num_mask = 0x1f;
452 dev->mii.phy_id = asix_get_phy_addr(dev);
453
454 dev->net->netdev_ops = &ax88772_netdev_ops;
455 dev->net->ethtool_ops = &ax88772_ethtool_ops;
456 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
457 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
458
459 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
460
461 /* Reset the PHY to normal operation mode */
462 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
463 if (ret < 0) {
464 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
465 return ret;
466 }
467
468 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
469 if (ret < 0)
470 return ret;
471
472 msleep(150);
473
474 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
475 if (ret < 0)
476 return ret;
477
478 msleep(150);
479
480 ret = asix_sw_reset(dev, embd_phy ? AX_SWRESET_IPRL : AX_SWRESET_PRTE);
481
482 /* Read PHYID register *AFTER* the PHY was reset properly */
483 phyid = asix_get_phyid(dev);
484 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
485
486 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
487 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
488 /* hard_mtu is still the default - the device does not support
489 jumbo eth frames */
490 dev->rx_urb_size = 2048;
491 }
492
493 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
494 if (!dev->driver_priv)
495 return -ENOMEM;
496
497 return 0;
498}
499
500static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf)
501{
502 if (dev->driver_priv)
503 kfree(dev->driver_priv);
504}
505
506static const struct ethtool_ops ax88178_ethtool_ops = {
507 .get_drvinfo = asix_get_drvinfo,
508 .get_link = asix_get_link,
509 .get_msglevel = usbnet_get_msglevel,
510 .set_msglevel = usbnet_set_msglevel,
511 .get_wol = asix_get_wol,
512 .set_wol = asix_set_wol,
513 .get_eeprom_len = asix_get_eeprom_len,
514 .get_eeprom = asix_get_eeprom,
515 .set_eeprom = asix_set_eeprom,
516 .get_settings = usbnet_get_settings,
517 .set_settings = usbnet_set_settings,
518 .nway_reset = usbnet_nway_reset,
519};
520
521static int marvell_phy_init(struct usbnet *dev)
522{
523 struct asix_data *data = (struct asix_data *)&dev->data;
524 u16 reg;
525
526 netdev_dbg(dev->net, "marvell_phy_init()\n");
527
528 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
529 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
530
531 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
532 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
533
534 if (data->ledmode) {
535 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
536 MII_MARVELL_LED_CTRL);
537 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
538
539 reg &= 0xf8ff;
540 reg |= (1 + 0x0100);
541 asix_mdio_write(dev->net, dev->mii.phy_id,
542 MII_MARVELL_LED_CTRL, reg);
543
544 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
545 MII_MARVELL_LED_CTRL);
546 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
547 reg &= 0xfc0f;
548 }
549
550 return 0;
551}
552
553static int rtl8211cl_phy_init(struct usbnet *dev)
554{
555 struct asix_data *data = (struct asix_data *)&dev->data;
556
557 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
558
559 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
560 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
561 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
562 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
563 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
564
565 if (data->ledmode == 12) {
566 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
567 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
568 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
569 }
570
571 return 0;
572}
573
574static int marvell_led_status(struct usbnet *dev, u16 speed)
575{
576 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
577
578 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
579
580 /* Clear out the center LED bits - 0x03F0 */
581 reg &= 0xfc0f;
582
583 switch (speed) {
584 case SPEED_1000:
585 reg |= 0x03e0;
586 break;
587 case SPEED_100:
588 reg |= 0x03b0;
589 break;
590 default:
591 reg |= 0x02f0;
592 }
593
594 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
595 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
596
597 return 0;
598}
599
600static int ax88178_reset(struct usbnet *dev)
601{
602 struct asix_data *data = (struct asix_data *)&dev->data;
603 int ret;
604 __le16 eeprom;
605 u8 status;
606 int gpio0 = 0;
607 u32 phyid;
608
609 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status);
610 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
611
612 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL);
613 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom);
614 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL);
615
616 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
617
618 if (eeprom == cpu_to_le16(0xffff)) {
619 data->phymode = PHY_MODE_MARVELL;
620 data->ledmode = 0;
621 gpio0 = 1;
622 } else {
623 data->phymode = le16_to_cpu(eeprom) & 0x7F;
624 data->ledmode = le16_to_cpu(eeprom) >> 8;
625 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
626 }
627 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
628
629 /* Power up external GigaPHY through AX88178 GPIO pin */
630 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40);
631 if ((le16_to_cpu(eeprom) >> 8) != 1) {
632 asix_write_gpio(dev, 0x003c, 30);
633 asix_write_gpio(dev, 0x001c, 300);
634 asix_write_gpio(dev, 0x003c, 30);
635 } else {
636 netdev_dbg(dev->net, "gpio phymode == 1 path\n");
637 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30);
638 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30);
639 }
640
641 /* Read PHYID register *AFTER* powering up PHY */
642 phyid = asix_get_phyid(dev);
643 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
644
645 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
646 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL);
647
648 asix_sw_reset(dev, 0);
649 msleep(150);
650
651 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
652 msleep(150);
653
654 asix_write_rx_ctl(dev, 0);
655
656 if (data->phymode == PHY_MODE_MARVELL) {
657 marvell_phy_init(dev);
658 msleep(60);
659 } else if (data->phymode == PHY_MODE_RTL8211CL)
660 rtl8211cl_phy_init(dev);
661
662 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,
663 BMCR_RESET | BMCR_ANENABLE);
664 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
665 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
666 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
667 ADVERTISE_1000FULL);
668
669 mii_nway_restart(&dev->mii);
670
671 ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT);
672 if (ret < 0)
673 return ret;
674
675 /* Rewrite MAC address */
676 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
677 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
678 data->mac_addr);
679 if (ret < 0)
680 return ret;
681
682 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
683 if (ret < 0)
684 return ret;
685
686 return 0;
687}
688
689static int ax88178_link_reset(struct usbnet *dev)
690{
691 u16 mode;
692 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
693 struct asix_data *data = (struct asix_data *)&dev->data;
694 u32 speed;
695
696 netdev_dbg(dev->net, "ax88178_link_reset()\n");
697
698 mii_check_media(&dev->mii, 1, 1);
699 mii_ethtool_gset(&dev->mii, &ecmd);
700 mode = AX88178_MEDIUM_DEFAULT;
701 speed = ethtool_cmd_speed(&ecmd);
702
703 if (speed == SPEED_1000)
704 mode |= AX_MEDIUM_GM;
705 else if (speed == SPEED_100)
706 mode |= AX_MEDIUM_PS;
707 else
708 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
709
710 mode |= AX_MEDIUM_ENCK;
711
712 if (ecmd.duplex == DUPLEX_FULL)
713 mode |= AX_MEDIUM_FD;
714 else
715 mode &= ~AX_MEDIUM_FD;
716
717 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
718 speed, ecmd.duplex, mode);
719
720 asix_write_medium_mode(dev, mode);
721
722 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
723 marvell_led_status(dev, speed);
724
725 return 0;
726}
727
728static void ax88178_set_mfb(struct usbnet *dev)
729{
730 u16 mfb = AX_RX_CTL_MFB_16384;
731 u16 rxctl;
732 u16 medium;
733 int old_rx_urb_size = dev->rx_urb_size;
734
735 if (dev->hard_mtu < 2048) {
736 dev->rx_urb_size = 2048;
737 mfb = AX_RX_CTL_MFB_2048;
738 } else if (dev->hard_mtu < 4096) {
739 dev->rx_urb_size = 4096;
740 mfb = AX_RX_CTL_MFB_4096;
741 } else if (dev->hard_mtu < 8192) {
742 dev->rx_urb_size = 8192;
743 mfb = AX_RX_CTL_MFB_8192;
744 } else if (dev->hard_mtu < 16384) {
745 dev->rx_urb_size = 16384;
746 mfb = AX_RX_CTL_MFB_16384;
747 }
748
749 rxctl = asix_read_rx_ctl(dev);
750 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb);
751
752 medium = asix_read_medium_status(dev);
753 if (dev->net->mtu > 1500)
754 medium |= AX_MEDIUM_JFE;
755 else
756 medium &= ~AX_MEDIUM_JFE;
757 asix_write_medium_mode(dev, medium);
758
759 if (dev->rx_urb_size > old_rx_urb_size)
760 usbnet_unlink_rx_urbs(dev);
761}
762
763static int ax88178_change_mtu(struct net_device *net, int new_mtu)
764{
765 struct usbnet *dev = netdev_priv(net);
766 int ll_mtu = new_mtu + net->hard_header_len + 4;
767
768 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
769
770 if (new_mtu <= 0 || ll_mtu > 16384)
771 return -EINVAL;
772
773 if ((ll_mtu % dev->maxpacket) == 0)
774 return -EDOM;
775
776 net->mtu = new_mtu;
777 dev->hard_mtu = net->mtu + net->hard_header_len;
778 ax88178_set_mfb(dev);
779
780 /* max qlen depend on hard_mtu and rx_urb_size */
781 usbnet_update_max_qlen(dev);
782
783 return 0;
784}
785
786static const struct net_device_ops ax88178_netdev_ops = {
787 .ndo_open = usbnet_open,
788 .ndo_stop = usbnet_stop,
789 .ndo_start_xmit = usbnet_start_xmit,
790 .ndo_tx_timeout = usbnet_tx_timeout,
791 .ndo_set_mac_address = asix_set_mac_address,
792 .ndo_validate_addr = eth_validate_addr,
793 .ndo_set_rx_mode = asix_set_multicast,
794 .ndo_do_ioctl = asix_ioctl,
795 .ndo_change_mtu = ax88178_change_mtu,
796};
797
798static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
799{
800 int ret;
801 u8 buf[ETH_ALEN];
802
803 usbnet_get_endpoints(dev,intf);
804
805 /* Get the MAC address */
806 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
807 if (ret < 0) {
808 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
809 return ret;
810 }
811
812 asix_set_netdev_dev_addr(dev, buf);
813
814 /* Initialize MII structure */
815 dev->mii.dev = dev->net;
816 dev->mii.mdio_read = asix_mdio_read;
817 dev->mii.mdio_write = asix_mdio_write;
818 dev->mii.phy_id_mask = 0x1f;
819 dev->mii.reg_num_mask = 0xff;
820 dev->mii.supports_gmii = 1;
821 dev->mii.phy_id = asix_get_phy_addr(dev);
822
823 dev->net->netdev_ops = &ax88178_netdev_ops;
824 dev->net->ethtool_ops = &ax88178_ethtool_ops;
825
826 /* Blink LEDS so users know driver saw dongle */
827 asix_sw_reset(dev, 0);
828 msleep(150);
829
830 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
831 msleep(150);
832
833 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
834 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
835 /* hard_mtu is still the default - the device does not support
836 jumbo eth frames */
837 dev->rx_urb_size = 2048;
838 }
839
840 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
841 if (!dev->driver_priv)
842 return -ENOMEM;
843
844 return 0;
845}
846
847static const struct driver_info ax8817x_info = {
848 .description = "ASIX AX8817x USB 2.0 Ethernet",
849 .bind = ax88172_bind,
850 .status = asix_status,
851 .link_reset = ax88172_link_reset,
852 .reset = ax88172_link_reset,
853 .flags = FLAG_ETHER | FLAG_LINK_INTR,
854 .data = 0x00130103,
855};
856
857static const struct driver_info dlink_dub_e100_info = {
858 .description = "DLink DUB-E100 USB Ethernet",
859 .bind = ax88172_bind,
860 .status = asix_status,
861 .link_reset = ax88172_link_reset,
862 .reset = ax88172_link_reset,
863 .flags = FLAG_ETHER | FLAG_LINK_INTR,
864 .data = 0x009f9d9f,
865};
866
867static const struct driver_info netgear_fa120_info = {
868 .description = "Netgear FA-120 USB Ethernet",
869 .bind = ax88172_bind,
870 .status = asix_status,
871 .link_reset = ax88172_link_reset,
872 .reset = ax88172_link_reset,
873 .flags = FLAG_ETHER | FLAG_LINK_INTR,
874 .data = 0x00130103,
875};
876
877static const struct driver_info hawking_uf200_info = {
878 .description = "Hawking UF200 USB Ethernet",
879 .bind = ax88172_bind,
880 .status = asix_status,
881 .link_reset = ax88172_link_reset,
882 .reset = ax88172_link_reset,
883 .flags = FLAG_ETHER | FLAG_LINK_INTR,
884 .data = 0x001f1d1f,
885};
886
887static const struct driver_info ax88772_info = {
888 .description = "ASIX AX88772 USB 2.0 Ethernet",
889 .bind = ax88772_bind,
890 .unbind = ax88772_unbind,
891 .status = asix_status,
892 .link_reset = ax88772_link_reset,
893 .reset = ax88772_reset,
894 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
895 .rx_fixup = asix_rx_fixup_common,
896 .tx_fixup = asix_tx_fixup,
897};
898
899static const struct driver_info ax88772b_info = {
900 .description = "ASIX AX88772B USB 2.0 Ethernet",
901 .bind = ax88772_bind,
902 .unbind = ax88772_unbind,
903 .status = asix_status,
904 .link_reset = ax88772_link_reset,
905 .reset = ax88772_reset,
906 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
907 FLAG_MULTI_PACKET,
908 .rx_fixup = asix_rx_fixup_common,
909 .tx_fixup = asix_tx_fixup,
910 .data = FLAG_EEPROM_MAC,
911};
912
913static const struct driver_info ax88178_info = {
914 .description = "ASIX AX88178 USB 2.0 Ethernet",
915 .bind = ax88178_bind,
916 .unbind = ax88772_unbind,
917 .status = asix_status,
918 .link_reset = ax88178_link_reset,
919 .reset = ax88178_reset,
920 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
921 FLAG_MULTI_PACKET,
922 .rx_fixup = asix_rx_fixup_common,
923 .tx_fixup = asix_tx_fixup,
924};
925
926/*
927 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in
928 * no-name packaging.
929 * USB device strings are:
930 * 1: Manufacturer: USBLINK
931 * 2: Product: HG20F9 USB2.0
932 * 3: Serial: 000003
933 * Appears to be compatible with Asix 88772B.
934 */
935static const struct driver_info hg20f9_info = {
936 .description = "HG20F9 USB 2.0 Ethernet",
937 .bind = ax88772_bind,
938 .unbind = ax88772_unbind,
939 .status = asix_status,
940 .link_reset = ax88772_link_reset,
941 .reset = ax88772_reset,
942 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
943 FLAG_MULTI_PACKET,
944 .rx_fixup = asix_rx_fixup_common,
945 .tx_fixup = asix_tx_fixup,
946 .data = FLAG_EEPROM_MAC,
947};
948
949static const struct usb_device_id products [] = {
950{
951 // Linksys USB200M
952 USB_DEVICE (0x077b, 0x2226),
953 .driver_info = (unsigned long) &ax8817x_info,
954}, {
955 // Netgear FA120
956 USB_DEVICE (0x0846, 0x1040),
957 .driver_info = (unsigned long) &netgear_fa120_info,
958}, {
959 // DLink DUB-E100
960 USB_DEVICE (0x2001, 0x1a00),
961 .driver_info = (unsigned long) &dlink_dub_e100_info,
962}, {
963 // Intellinet, ST Lab USB Ethernet
964 USB_DEVICE (0x0b95, 0x1720),
965 .driver_info = (unsigned long) &ax8817x_info,
966}, {
967 // Hawking UF200, TrendNet TU2-ET100
968 USB_DEVICE (0x07b8, 0x420a),
969 .driver_info = (unsigned long) &hawking_uf200_info,
970}, {
971 // Billionton Systems, USB2AR
972 USB_DEVICE (0x08dd, 0x90ff),
973 .driver_info = (unsigned long) &ax8817x_info,
974}, {
975 // ATEN UC210T
976 USB_DEVICE (0x0557, 0x2009),
977 .driver_info = (unsigned long) &ax8817x_info,
978}, {
979 // Buffalo LUA-U2-KTX
980 USB_DEVICE (0x0411, 0x003d),
981 .driver_info = (unsigned long) &ax8817x_info,
982}, {
983 // Buffalo LUA-U2-GT 10/100/1000
984 USB_DEVICE (0x0411, 0x006e),
985 .driver_info = (unsigned long) &ax88178_info,
986}, {
987 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
988 USB_DEVICE (0x6189, 0x182d),
989 .driver_info = (unsigned long) &ax8817x_info,
990}, {
991 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
992 USB_DEVICE (0x0df6, 0x0056),
993 .driver_info = (unsigned long) &ax88178_info,
994}, {
995 // corega FEther USB2-TX
996 USB_DEVICE (0x07aa, 0x0017),
997 .driver_info = (unsigned long) &ax8817x_info,
998}, {
999 // Surecom EP-1427X-2
1000 USB_DEVICE (0x1189, 0x0893),
1001 .driver_info = (unsigned long) &ax8817x_info,
1002}, {
1003 // goodway corp usb gwusb2e
1004 USB_DEVICE (0x1631, 0x6200),
1005 .driver_info = (unsigned long) &ax8817x_info,
1006}, {
1007 // JVC MP-PRX1 Port Replicator
1008 USB_DEVICE (0x04f1, 0x3008),
1009 .driver_info = (unsigned long) &ax8817x_info,
1010}, {
1011 // Lenovo U2L100P 10/100
1012 USB_DEVICE (0x17ef, 0x7203),
1013 .driver_info = (unsigned long) &ax88772_info,
1014}, {
1015 // ASIX AX88772B 10/100
1016 USB_DEVICE (0x0b95, 0x772b),
1017 .driver_info = (unsigned long) &ax88772b_info,
1018}, {
1019 // ASIX AX88772 10/100
1020 USB_DEVICE (0x0b95, 0x7720),
1021 .driver_info = (unsigned long) &ax88772_info,
1022}, {
1023 // ASIX AX88178 10/100/1000
1024 USB_DEVICE (0x0b95, 0x1780),
1025 .driver_info = (unsigned long) &ax88178_info,
1026}, {
1027 // Logitec LAN-GTJ/U2A
1028 USB_DEVICE (0x0789, 0x0160),
1029 .driver_info = (unsigned long) &ax88178_info,
1030}, {
1031 // Linksys USB200M Rev 2
1032 USB_DEVICE (0x13b1, 0x0018),
1033 .driver_info = (unsigned long) &ax88772_info,
1034}, {
1035 // 0Q0 cable ethernet
1036 USB_DEVICE (0x1557, 0x7720),
1037 .driver_info = (unsigned long) &ax88772_info,
1038}, {
1039 // DLink DUB-E100 H/W Ver B1
1040 USB_DEVICE (0x07d1, 0x3c05),
1041 .driver_info = (unsigned long) &ax88772_info,
1042}, {
1043 // DLink DUB-E100 H/W Ver B1 Alternate
1044 USB_DEVICE (0x2001, 0x3c05),
1045 .driver_info = (unsigned long) &ax88772_info,
1046}, {
1047 // DLink DUB-E100 H/W Ver C1
1048 USB_DEVICE (0x2001, 0x1a02),
1049 .driver_info = (unsigned long) &ax88772_info,
1050}, {
1051 // Linksys USB1000
1052 USB_DEVICE (0x1737, 0x0039),
1053 .driver_info = (unsigned long) &ax88178_info,
1054}, {
1055 // IO-DATA ETG-US2
1056 USB_DEVICE (0x04bb, 0x0930),
1057 .driver_info = (unsigned long) &ax88178_info,
1058}, {
1059 // Belkin F5D5055
1060 USB_DEVICE(0x050d, 0x5055),
1061 .driver_info = (unsigned long) &ax88178_info,
1062}, {
1063 // Apple USB Ethernet Adapter
1064 USB_DEVICE(0x05ac, 0x1402),
1065 .driver_info = (unsigned long) &ax88772_info,
1066}, {
1067 // Cables-to-Go USB Ethernet Adapter
1068 USB_DEVICE(0x0b95, 0x772a),
1069 .driver_info = (unsigned long) &ax88772_info,
1070}, {
1071 // ABOCOM for pci
1072 USB_DEVICE(0x14ea, 0xab11),
1073 .driver_info = (unsigned long) &ax88178_info,
1074}, {
1075 // ASIX 88772a
1076 USB_DEVICE(0x0db0, 0xa877),
1077 .driver_info = (unsigned long) &ax88772_info,
1078}, {
1079 // Asus USB Ethernet Adapter
1080 USB_DEVICE (0x0b95, 0x7e2b),
1081 .driver_info = (unsigned long) &ax88772_info,
1082}, {
1083 /* ASIX 88172a demo board */
1084 USB_DEVICE(0x0b95, 0x172a),
1085 .driver_info = (unsigned long) &ax88172a_info,
1086}, {
1087 /*
1088 * USBLINK HG20F9 "USB 2.0 LAN"
1089 * Appears to have gazumped Linksys's manufacturer ID but
1090 * doesn't (yet) conflict with any known Linksys product.
1091 */
1092 USB_DEVICE(0x066b, 0x20f9),
1093 .driver_info = (unsigned long) &hg20f9_info,
1094},
1095 { }, // END
1096};
1097MODULE_DEVICE_TABLE(usb, products);
1098
1099static struct usb_driver asix_driver = {
1100 .name = DRIVER_NAME,
1101 .id_table = products,
1102 .probe = usbnet_probe,
1103 .suspend = usbnet_suspend,
1104 .resume = usbnet_resume,
1105 .disconnect = usbnet_disconnect,
1106 .supports_autosuspend = 1,
1107 .disable_hub_initiated_lpm = 1,
1108};
1109
1110module_usb_driver(asix_driver);
1111
1112MODULE_AUTHOR("David Hollis");
1113MODULE_VERSION(DRIVER_VERSION);
1114MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1115MODULE_LICENSE("GPL");
1116
1/*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include "asix.h"
23
24#define PHY_MODE_MARVELL 0x0000
25#define MII_MARVELL_LED_CTRL 0x0018
26#define MII_MARVELL_STATUS 0x001b
27#define MII_MARVELL_CTRL 0x0014
28
29#define MARVELL_LED_MANUAL 0x0019
30
31#define MARVELL_STATUS_HWCFG 0x0004
32
33#define MARVELL_CTRL_TXDELAY 0x0002
34#define MARVELL_CTRL_RXDELAY 0x0080
35
36#define PHY_MODE_RTL8211CL 0x000C
37
38#define AX88772A_PHY14H 0x14
39#define AX88772A_PHY14H_DEFAULT 0x442C
40
41#define AX88772A_PHY15H 0x15
42#define AX88772A_PHY15H_DEFAULT 0x03C8
43
44#define AX88772A_PHY16H 0x16
45#define AX88772A_PHY16H_DEFAULT 0x4044
46
47struct ax88172_int_data {
48 __le16 res1;
49 u8 link;
50 __le16 res2;
51 u8 status;
52 __le16 res3;
53} __packed;
54
55static void asix_status(struct usbnet *dev, struct urb *urb)
56{
57 struct ax88172_int_data *event;
58 int link;
59
60 if (urb->actual_length < 8)
61 return;
62
63 event = urb->transfer_buffer;
64 link = event->link & 0x01;
65 if (netif_carrier_ok(dev->net) != link) {
66 usbnet_link_change(dev, link, 1);
67 netdev_dbg(dev->net, "Link Status is: %d\n", link);
68 }
69}
70
71static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
72{
73 if (is_valid_ether_addr(addr)) {
74 memcpy(dev->net->dev_addr, addr, ETH_ALEN);
75 } else {
76 netdev_info(dev->net, "invalid hw address, using random\n");
77 eth_hw_addr_random(dev->net);
78 }
79}
80
81/* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
82static u32 asix_get_phyid(struct usbnet *dev)
83{
84 int phy_reg;
85 u32 phy_id;
86 int i;
87
88 /* Poll for the rare case the FW or phy isn't ready yet. */
89 for (i = 0; i < 100; i++) {
90 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
91 if (phy_reg < 0)
92 return 0;
93 if (phy_reg != 0 && phy_reg != 0xFFFF)
94 break;
95 mdelay(1);
96 }
97
98 if (phy_reg <= 0 || phy_reg == 0xFFFF)
99 return 0;
100
101 phy_id = (phy_reg & 0xffff) << 16;
102
103 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
104 if (phy_reg < 0)
105 return 0;
106
107 phy_id |= (phy_reg & 0xffff);
108
109 return phy_id;
110}
111
112static u32 asix_get_link(struct net_device *net)
113{
114 struct usbnet *dev = netdev_priv(net);
115
116 return mii_link_ok(&dev->mii);
117}
118
119static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
120{
121 struct usbnet *dev = netdev_priv(net);
122
123 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
124}
125
126/* We need to override some ethtool_ops so we require our
127 own structure so we don't interfere with other usbnet
128 devices that may be connected at the same time. */
129static const struct ethtool_ops ax88172_ethtool_ops = {
130 .get_drvinfo = asix_get_drvinfo,
131 .get_link = asix_get_link,
132 .get_msglevel = usbnet_get_msglevel,
133 .set_msglevel = usbnet_set_msglevel,
134 .get_wol = asix_get_wol,
135 .set_wol = asix_set_wol,
136 .get_eeprom_len = asix_get_eeprom_len,
137 .get_eeprom = asix_get_eeprom,
138 .set_eeprom = asix_set_eeprom,
139 .get_settings = usbnet_get_settings,
140 .set_settings = usbnet_set_settings,
141 .nway_reset = usbnet_nway_reset,
142};
143
144static void ax88172_set_multicast(struct net_device *net)
145{
146 struct usbnet *dev = netdev_priv(net);
147 struct asix_data *data = (struct asix_data *)&dev->data;
148 u8 rx_ctl = 0x8c;
149
150 if (net->flags & IFF_PROMISC) {
151 rx_ctl |= 0x01;
152 } else if (net->flags & IFF_ALLMULTI ||
153 netdev_mc_count(net) > AX_MAX_MCAST) {
154 rx_ctl |= 0x02;
155 } else if (netdev_mc_empty(net)) {
156 /* just broadcast and directed */
157 } else {
158 /* We use the 20 byte dev->data
159 * for our 8 byte filter buffer
160 * to avoid allocating memory that
161 * is tricky to free later */
162 struct netdev_hw_addr *ha;
163 u32 crc_bits;
164
165 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
166
167 /* Build the multicast hash filter. */
168 netdev_for_each_mc_addr(ha, net) {
169 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
170 data->multi_filter[crc_bits >> 3] |=
171 1 << (crc_bits & 7);
172 }
173
174 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
175 AX_MCAST_FILTER_SIZE, data->multi_filter);
176
177 rx_ctl |= 0x10;
178 }
179
180 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
181}
182
183static int ax88172_link_reset(struct usbnet *dev)
184{
185 u8 mode;
186 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
187
188 mii_check_media(&dev->mii, 1, 1);
189 mii_ethtool_gset(&dev->mii, &ecmd);
190 mode = AX88172_MEDIUM_DEFAULT;
191
192 if (ecmd.duplex != DUPLEX_FULL)
193 mode |= ~AX88172_MEDIUM_FD;
194
195 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
196 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
197
198 asix_write_medium_mode(dev, mode, 0);
199
200 return 0;
201}
202
203static const struct net_device_ops ax88172_netdev_ops = {
204 .ndo_open = usbnet_open,
205 .ndo_stop = usbnet_stop,
206 .ndo_start_xmit = usbnet_start_xmit,
207 .ndo_tx_timeout = usbnet_tx_timeout,
208 .ndo_change_mtu = usbnet_change_mtu,
209 .ndo_set_mac_address = eth_mac_addr,
210 .ndo_validate_addr = eth_validate_addr,
211 .ndo_do_ioctl = asix_ioctl,
212 .ndo_set_rx_mode = ax88172_set_multicast,
213};
214
215static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits)
216{
217 unsigned int timeout = 5000;
218
219 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);
220
221 /* give phy_id a chance to process reset */
222 udelay(500);
223
224 /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */
225 while (timeout--) {
226 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)
227 & BMCR_RESET)
228 udelay(100);
229 else
230 return;
231 }
232
233 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n",
234 dev->mii.phy_id);
235}
236
237static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
238{
239 int ret = 0;
240 u8 buf[ETH_ALEN];
241 int i;
242 unsigned long gpio_bits = dev->driver_info->data;
243
244 usbnet_get_endpoints(dev,intf);
245
246 /* Toggle the GPIOs in a manufacturer/model specific way */
247 for (i = 2; i >= 0; i--) {
248 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
249 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0);
250 if (ret < 0)
251 goto out;
252 msleep(5);
253 }
254
255 ret = asix_write_rx_ctl(dev, 0x80, 0);
256 if (ret < 0)
257 goto out;
258
259 /* Get the MAC address */
260 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID,
261 0, 0, ETH_ALEN, buf, 0);
262 if (ret < 0) {
263 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
264 ret);
265 goto out;
266 }
267
268 asix_set_netdev_dev_addr(dev, buf);
269
270 /* Initialize MII structure */
271 dev->mii.dev = dev->net;
272 dev->mii.mdio_read = asix_mdio_read;
273 dev->mii.mdio_write = asix_mdio_write;
274 dev->mii.phy_id_mask = 0x3f;
275 dev->mii.reg_num_mask = 0x1f;
276 dev->mii.phy_id = asix_get_phy_addr(dev);
277
278 dev->net->netdev_ops = &ax88172_netdev_ops;
279 dev->net->ethtool_ops = &ax88172_ethtool_ops;
280 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
281 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
282
283 asix_phy_reset(dev, BMCR_RESET);
284 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
285 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
286 mii_nway_restart(&dev->mii);
287
288 return 0;
289
290out:
291 return ret;
292}
293
294static const struct ethtool_ops ax88772_ethtool_ops = {
295 .get_drvinfo = asix_get_drvinfo,
296 .get_link = asix_get_link,
297 .get_msglevel = usbnet_get_msglevel,
298 .set_msglevel = usbnet_set_msglevel,
299 .get_wol = asix_get_wol,
300 .set_wol = asix_set_wol,
301 .get_eeprom_len = asix_get_eeprom_len,
302 .get_eeprom = asix_get_eeprom,
303 .set_eeprom = asix_set_eeprom,
304 .get_settings = usbnet_get_settings,
305 .set_settings = usbnet_set_settings,
306 .nway_reset = usbnet_nway_reset,
307};
308
309static int ax88772_link_reset(struct usbnet *dev)
310{
311 u16 mode;
312 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
313
314 mii_check_media(&dev->mii, 1, 1);
315 mii_ethtool_gset(&dev->mii, &ecmd);
316 mode = AX88772_MEDIUM_DEFAULT;
317
318 if (ethtool_cmd_speed(&ecmd) != SPEED_100)
319 mode &= ~AX_MEDIUM_PS;
320
321 if (ecmd.duplex != DUPLEX_FULL)
322 mode &= ~AX_MEDIUM_FD;
323
324 netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
325 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
326
327 asix_write_medium_mode(dev, mode, 0);
328
329 return 0;
330}
331
332static int ax88772_reset(struct usbnet *dev)
333{
334 struct asix_data *data = (struct asix_data *)&dev->data;
335 int ret;
336
337 /* Rewrite MAC address */
338 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
339 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
340 ETH_ALEN, data->mac_addr, 0);
341 if (ret < 0)
342 goto out;
343
344 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
345 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
346 if (ret < 0)
347 goto out;
348
349 asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0);
350 if (ret < 0)
351 goto out;
352
353 return 0;
354
355out:
356 return ret;
357}
358
359static int ax88772_hw_reset(struct usbnet *dev, int in_pm)
360{
361 struct asix_data *data = (struct asix_data *)&dev->data;
362 int ret, embd_phy;
363 u16 rx_ctl;
364
365 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 |
366 AX_GPIO_GPO2EN, 5, in_pm);
367 if (ret < 0)
368 goto out;
369
370 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
371
372 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy,
373 0, 0, NULL, in_pm);
374 if (ret < 0) {
375 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
376 goto out;
377 }
378
379 if (embd_phy) {
380 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm);
381 if (ret < 0)
382 goto out;
383
384 usleep_range(10000, 11000);
385
386 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
387 if (ret < 0)
388 goto out;
389
390 msleep(60);
391
392 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL,
393 in_pm);
394 if (ret < 0)
395 goto out;
396 } else {
397 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL,
398 in_pm);
399 if (ret < 0)
400 goto out;
401 }
402
403 msleep(150);
404
405 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
406 MII_PHYSID1))){
407 ret = -EIO;
408 goto out;
409 }
410
411 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
412 if (ret < 0)
413 goto out;
414
415 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
416 if (ret < 0)
417 goto out;
418
419 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
420 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
421 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
422 if (ret < 0) {
423 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
424 goto out;
425 }
426
427 /* Rewrite MAC address */
428 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
429 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
430 ETH_ALEN, data->mac_addr, in_pm);
431 if (ret < 0)
432 goto out;
433
434 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
435 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
436 if (ret < 0)
437 goto out;
438
439 rx_ctl = asix_read_rx_ctl(dev, in_pm);
440 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
441 rx_ctl);
442
443 rx_ctl = asix_read_medium_status(dev, in_pm);
444 netdev_dbg(dev->net,
445 "Medium Status is 0x%04x after all initializations\n",
446 rx_ctl);
447
448 return 0;
449
450out:
451 return ret;
452}
453
454static int ax88772a_hw_reset(struct usbnet *dev, int in_pm)
455{
456 struct asix_data *data = (struct asix_data *)&dev->data;
457 int ret, embd_phy;
458 u16 rx_ctl, phy14h, phy15h, phy16h;
459 u8 chipcode = 0;
460
461 ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm);
462 if (ret < 0)
463 goto out;
464
465 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
466
467 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy |
468 AX_PHYSEL_SSEN, 0, 0, NULL, in_pm);
469 if (ret < 0) {
470 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
471 goto out;
472 }
473 usleep_range(10000, 11000);
474
475 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm);
476 if (ret < 0)
477 goto out;
478
479 usleep_range(10000, 11000);
480
481 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
482 if (ret < 0)
483 goto out;
484
485 msleep(160);
486
487 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
488 if (ret < 0)
489 goto out;
490
491 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
492 if (ret < 0)
493 goto out;
494
495 msleep(200);
496
497 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
498 MII_PHYSID1))) {
499 ret = -1;
500 goto out;
501 }
502
503 ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0,
504 0, 1, &chipcode, in_pm);
505 if (ret < 0)
506 goto out;
507
508 if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772B_CHIPCODE) {
509 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001,
510 0, NULL, in_pm);
511 if (ret < 0) {
512 netdev_dbg(dev->net, "Write BQ setting failed: %d\n",
513 ret);
514 goto out;
515 }
516 } else if ((chipcode & AX_CHIPCODE_MASK) == AX_AX88772A_CHIPCODE) {
517 /* Check if the PHY registers have default settings */
518 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
519 AX88772A_PHY14H);
520 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
521 AX88772A_PHY15H);
522 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
523 AX88772A_PHY16H);
524
525 netdev_dbg(dev->net,
526 "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n",
527 phy14h, phy15h, phy16h);
528
529 /* Restore PHY registers default setting if not */
530 if (phy14h != AX88772A_PHY14H_DEFAULT)
531 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
532 AX88772A_PHY14H,
533 AX88772A_PHY14H_DEFAULT);
534 if (phy15h != AX88772A_PHY15H_DEFAULT)
535 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
536 AX88772A_PHY15H,
537 AX88772A_PHY15H_DEFAULT);
538 if (phy16h != AX88772A_PHY16H_DEFAULT)
539 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
540 AX88772A_PHY16H,
541 AX88772A_PHY16H_DEFAULT);
542 }
543
544 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
545 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
546 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
547 if (ret < 0) {
548 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
549 goto out;
550 }
551
552 /* Rewrite MAC address */
553 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
554 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
555 data->mac_addr, in_pm);
556 if (ret < 0)
557 goto out;
558
559 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
560 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
561 if (ret < 0)
562 goto out;
563
564 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
565 if (ret < 0)
566 return ret;
567
568 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
569 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
570 if (ret < 0)
571 goto out;
572
573 rx_ctl = asix_read_rx_ctl(dev, in_pm);
574 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
575 rx_ctl);
576
577 rx_ctl = asix_read_medium_status(dev, in_pm);
578 netdev_dbg(dev->net,
579 "Medium Status is 0x%04x after all initializations\n",
580 rx_ctl);
581
582 return 0;
583
584out:
585 return ret;
586}
587
588static const struct net_device_ops ax88772_netdev_ops = {
589 .ndo_open = usbnet_open,
590 .ndo_stop = usbnet_stop,
591 .ndo_start_xmit = usbnet_start_xmit,
592 .ndo_tx_timeout = usbnet_tx_timeout,
593 .ndo_change_mtu = usbnet_change_mtu,
594 .ndo_set_mac_address = asix_set_mac_address,
595 .ndo_validate_addr = eth_validate_addr,
596 .ndo_do_ioctl = asix_ioctl,
597 .ndo_set_rx_mode = asix_set_multicast,
598};
599
600static void ax88772_suspend(struct usbnet *dev)
601{
602 struct asix_common_private *priv = dev->driver_priv;
603 u16 medium;
604
605 /* Stop MAC operation */
606 medium = asix_read_medium_status(dev, 1);
607 medium &= ~AX_MEDIUM_RE;
608 asix_write_medium_mode(dev, medium, 1);
609
610 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n",
611 asix_read_medium_status(dev, 1));
612
613 /* Preserve BMCR for restoring */
614 priv->presvd_phy_bmcr =
615 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR);
616
617 /* Preserve ANAR for restoring */
618 priv->presvd_phy_advertise =
619 asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE);
620}
621
622static int asix_suspend(struct usb_interface *intf, pm_message_t message)
623{
624 struct usbnet *dev = usb_get_intfdata(intf);
625 struct asix_common_private *priv = dev->driver_priv;
626
627 if (priv->suspend)
628 priv->suspend(dev);
629
630 return usbnet_suspend(intf, message);
631}
632
633static void ax88772_restore_phy(struct usbnet *dev)
634{
635 struct asix_common_private *priv = dev->driver_priv;
636
637 if (priv->presvd_phy_advertise) {
638 /* Restore Advertisement control reg */
639 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE,
640 priv->presvd_phy_advertise);
641
642 /* Restore BMCR */
643 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR,
644 priv->presvd_phy_bmcr);
645
646 mii_nway_restart(&dev->mii);
647 priv->presvd_phy_advertise = 0;
648 priv->presvd_phy_bmcr = 0;
649 }
650}
651
652static void ax88772_resume(struct usbnet *dev)
653{
654 int i;
655
656 for (i = 0; i < 3; i++)
657 if (!ax88772_hw_reset(dev, 1))
658 break;
659 ax88772_restore_phy(dev);
660}
661
662static void ax88772a_resume(struct usbnet *dev)
663{
664 int i;
665
666 for (i = 0; i < 3; i++) {
667 if (!ax88772a_hw_reset(dev, 1))
668 break;
669 }
670
671 ax88772_restore_phy(dev);
672}
673
674static int asix_resume(struct usb_interface *intf)
675{
676 struct usbnet *dev = usb_get_intfdata(intf);
677 struct asix_common_private *priv = dev->driver_priv;
678
679 if (priv->resume)
680 priv->resume(dev);
681
682 return usbnet_resume(intf);
683}
684
685static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
686{
687 int ret, i;
688 u8 buf[ETH_ALEN], chipcode = 0;
689 u32 phyid;
690 struct asix_common_private *priv;
691
692 usbnet_get_endpoints(dev,intf);
693
694 /* Get the MAC address */
695 if (dev->driver_info->data & FLAG_EEPROM_MAC) {
696 for (i = 0; i < (ETH_ALEN >> 1); i++) {
697 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x04 + i,
698 0, 2, buf + i * 2, 0);
699 if (ret < 0)
700 break;
701 }
702 } else {
703 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
704 0, 0, ETH_ALEN, buf, 0);
705 }
706
707 if (ret < 0) {
708 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
709 return ret;
710 }
711
712 asix_set_netdev_dev_addr(dev, buf);
713
714 /* Initialize MII structure */
715 dev->mii.dev = dev->net;
716 dev->mii.mdio_read = asix_mdio_read;
717 dev->mii.mdio_write = asix_mdio_write;
718 dev->mii.phy_id_mask = 0x1f;
719 dev->mii.reg_num_mask = 0x1f;
720 dev->mii.phy_id = asix_get_phy_addr(dev);
721
722 dev->net->netdev_ops = &ax88772_netdev_ops;
723 dev->net->ethtool_ops = &ax88772_ethtool_ops;
724 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
725 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
726
727 asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1, &chipcode, 0);
728 chipcode &= AX_CHIPCODE_MASK;
729
730 (chipcode == AX_AX88772_CHIPCODE) ? ax88772_hw_reset(dev, 0) :
731 ax88772a_hw_reset(dev, 0);
732
733 /* Read PHYID register *AFTER* the PHY was reset properly */
734 phyid = asix_get_phyid(dev);
735 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
736
737 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
738 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
739 /* hard_mtu is still the default - the device does not support
740 jumbo eth frames */
741 dev->rx_urb_size = 2048;
742 }
743
744 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
745 if (!dev->driver_priv)
746 return -ENOMEM;
747
748 priv = dev->driver_priv;
749
750 priv->presvd_phy_bmcr = 0;
751 priv->presvd_phy_advertise = 0;
752 if (chipcode == AX_AX88772_CHIPCODE) {
753 priv->resume = ax88772_resume;
754 priv->suspend = ax88772_suspend;
755 } else {
756 priv->resume = ax88772a_resume;
757 priv->suspend = ax88772_suspend;
758 }
759
760 return 0;
761}
762
763static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf)
764{
765 kfree(dev->driver_priv);
766}
767
768static const struct ethtool_ops ax88178_ethtool_ops = {
769 .get_drvinfo = asix_get_drvinfo,
770 .get_link = asix_get_link,
771 .get_msglevel = usbnet_get_msglevel,
772 .set_msglevel = usbnet_set_msglevel,
773 .get_wol = asix_get_wol,
774 .set_wol = asix_set_wol,
775 .get_eeprom_len = asix_get_eeprom_len,
776 .get_eeprom = asix_get_eeprom,
777 .set_eeprom = asix_set_eeprom,
778 .get_settings = usbnet_get_settings,
779 .set_settings = usbnet_set_settings,
780 .nway_reset = usbnet_nway_reset,
781};
782
783static int marvell_phy_init(struct usbnet *dev)
784{
785 struct asix_data *data = (struct asix_data *)&dev->data;
786 u16 reg;
787
788 netdev_dbg(dev->net, "marvell_phy_init()\n");
789
790 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
791 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
792
793 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
794 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
795
796 if (data->ledmode) {
797 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
798 MII_MARVELL_LED_CTRL);
799 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
800
801 reg &= 0xf8ff;
802 reg |= (1 + 0x0100);
803 asix_mdio_write(dev->net, dev->mii.phy_id,
804 MII_MARVELL_LED_CTRL, reg);
805
806 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
807 MII_MARVELL_LED_CTRL);
808 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
809 reg &= 0xfc0f;
810 }
811
812 return 0;
813}
814
815static int rtl8211cl_phy_init(struct usbnet *dev)
816{
817 struct asix_data *data = (struct asix_data *)&dev->data;
818
819 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
820
821 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
822 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
823 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
824 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
825 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
826
827 if (data->ledmode == 12) {
828 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
829 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
830 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
831 }
832
833 return 0;
834}
835
836static int marvell_led_status(struct usbnet *dev, u16 speed)
837{
838 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
839
840 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
841
842 /* Clear out the center LED bits - 0x03F0 */
843 reg &= 0xfc0f;
844
845 switch (speed) {
846 case SPEED_1000:
847 reg |= 0x03e0;
848 break;
849 case SPEED_100:
850 reg |= 0x03b0;
851 break;
852 default:
853 reg |= 0x02f0;
854 }
855
856 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
857 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
858
859 return 0;
860}
861
862static int ax88178_reset(struct usbnet *dev)
863{
864 struct asix_data *data = (struct asix_data *)&dev->data;
865 int ret;
866 __le16 eeprom;
867 u8 status;
868 int gpio0 = 0;
869 u32 phyid;
870
871 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0);
872 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
873
874 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0);
875 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0);
876 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0);
877
878 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
879
880 if (eeprom == cpu_to_le16(0xffff)) {
881 data->phymode = PHY_MODE_MARVELL;
882 data->ledmode = 0;
883 gpio0 = 1;
884 } else {
885 data->phymode = le16_to_cpu(eeprom) & 0x7F;
886 data->ledmode = le16_to_cpu(eeprom) >> 8;
887 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
888 }
889 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
890
891 /* Power up external GigaPHY through AX88178 GPIO pin */
892 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 |
893 AX_GPIO_GPO1EN, 40, 0);
894 if ((le16_to_cpu(eeprom) >> 8) != 1) {
895 asix_write_gpio(dev, 0x003c, 30, 0);
896 asix_write_gpio(dev, 0x001c, 300, 0);
897 asix_write_gpio(dev, 0x003c, 30, 0);
898 } else {
899 netdev_dbg(dev->net, "gpio phymode == 1 path\n");
900 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0);
901 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0);
902 }
903
904 /* Read PHYID register *AFTER* powering up PHY */
905 phyid = asix_get_phyid(dev);
906 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
907
908 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
909 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0);
910
911 asix_sw_reset(dev, 0, 0);
912 msleep(150);
913
914 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
915 msleep(150);
916
917 asix_write_rx_ctl(dev, 0, 0);
918
919 if (data->phymode == PHY_MODE_MARVELL) {
920 marvell_phy_init(dev);
921 msleep(60);
922 } else if (data->phymode == PHY_MODE_RTL8211CL)
923 rtl8211cl_phy_init(dev);
924
925 asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE);
926 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
927 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
928 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
929 ADVERTISE_1000FULL);
930
931 asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0);
932 mii_nway_restart(&dev->mii);
933
934 /* Rewrite MAC address */
935 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
936 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
937 data->mac_addr, 0);
938 if (ret < 0)
939 return ret;
940
941 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
942 if (ret < 0)
943 return ret;
944
945 return 0;
946}
947
948static int ax88178_link_reset(struct usbnet *dev)
949{
950 u16 mode;
951 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
952 struct asix_data *data = (struct asix_data *)&dev->data;
953 u32 speed;
954
955 netdev_dbg(dev->net, "ax88178_link_reset()\n");
956
957 mii_check_media(&dev->mii, 1, 1);
958 mii_ethtool_gset(&dev->mii, &ecmd);
959 mode = AX88178_MEDIUM_DEFAULT;
960 speed = ethtool_cmd_speed(&ecmd);
961
962 if (speed == SPEED_1000)
963 mode |= AX_MEDIUM_GM;
964 else if (speed == SPEED_100)
965 mode |= AX_MEDIUM_PS;
966 else
967 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
968
969 mode |= AX_MEDIUM_ENCK;
970
971 if (ecmd.duplex == DUPLEX_FULL)
972 mode |= AX_MEDIUM_FD;
973 else
974 mode &= ~AX_MEDIUM_FD;
975
976 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
977 speed, ecmd.duplex, mode);
978
979 asix_write_medium_mode(dev, mode, 0);
980
981 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
982 marvell_led_status(dev, speed);
983
984 return 0;
985}
986
987static void ax88178_set_mfb(struct usbnet *dev)
988{
989 u16 mfb = AX_RX_CTL_MFB_16384;
990 u16 rxctl;
991 u16 medium;
992 int old_rx_urb_size = dev->rx_urb_size;
993
994 if (dev->hard_mtu < 2048) {
995 dev->rx_urb_size = 2048;
996 mfb = AX_RX_CTL_MFB_2048;
997 } else if (dev->hard_mtu < 4096) {
998 dev->rx_urb_size = 4096;
999 mfb = AX_RX_CTL_MFB_4096;
1000 } else if (dev->hard_mtu < 8192) {
1001 dev->rx_urb_size = 8192;
1002 mfb = AX_RX_CTL_MFB_8192;
1003 } else if (dev->hard_mtu < 16384) {
1004 dev->rx_urb_size = 16384;
1005 mfb = AX_RX_CTL_MFB_16384;
1006 }
1007
1008 rxctl = asix_read_rx_ctl(dev, 0);
1009 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0);
1010
1011 medium = asix_read_medium_status(dev, 0);
1012 if (dev->net->mtu > 1500)
1013 medium |= AX_MEDIUM_JFE;
1014 else
1015 medium &= ~AX_MEDIUM_JFE;
1016 asix_write_medium_mode(dev, medium, 0);
1017
1018 if (dev->rx_urb_size > old_rx_urb_size)
1019 usbnet_unlink_rx_urbs(dev);
1020}
1021
1022static int ax88178_change_mtu(struct net_device *net, int new_mtu)
1023{
1024 struct usbnet *dev = netdev_priv(net);
1025 int ll_mtu = new_mtu + net->hard_header_len + 4;
1026
1027 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
1028
1029 if ((ll_mtu % dev->maxpacket) == 0)
1030 return -EDOM;
1031
1032 net->mtu = new_mtu;
1033 dev->hard_mtu = net->mtu + net->hard_header_len;
1034 ax88178_set_mfb(dev);
1035
1036 /* max qlen depend on hard_mtu and rx_urb_size */
1037 usbnet_update_max_qlen(dev);
1038
1039 return 0;
1040}
1041
1042static const struct net_device_ops ax88178_netdev_ops = {
1043 .ndo_open = usbnet_open,
1044 .ndo_stop = usbnet_stop,
1045 .ndo_start_xmit = usbnet_start_xmit,
1046 .ndo_tx_timeout = usbnet_tx_timeout,
1047 .ndo_set_mac_address = asix_set_mac_address,
1048 .ndo_validate_addr = eth_validate_addr,
1049 .ndo_set_rx_mode = asix_set_multicast,
1050 .ndo_do_ioctl = asix_ioctl,
1051 .ndo_change_mtu = ax88178_change_mtu,
1052};
1053
1054static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
1055{
1056 int ret;
1057 u8 buf[ETH_ALEN];
1058
1059 usbnet_get_endpoints(dev,intf);
1060
1061 /* Get the MAC address */
1062 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0);
1063 if (ret < 0) {
1064 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
1065 return ret;
1066 }
1067
1068 asix_set_netdev_dev_addr(dev, buf);
1069
1070 /* Initialize MII structure */
1071 dev->mii.dev = dev->net;
1072 dev->mii.mdio_read = asix_mdio_read;
1073 dev->mii.mdio_write = asix_mdio_write;
1074 dev->mii.phy_id_mask = 0x1f;
1075 dev->mii.reg_num_mask = 0xff;
1076 dev->mii.supports_gmii = 1;
1077 dev->mii.phy_id = asix_get_phy_addr(dev);
1078
1079 dev->net->netdev_ops = &ax88178_netdev_ops;
1080 dev->net->ethtool_ops = &ax88178_ethtool_ops;
1081 dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4);
1082
1083 /* Blink LEDS so users know driver saw dongle */
1084 asix_sw_reset(dev, 0, 0);
1085 msleep(150);
1086
1087 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
1088 msleep(150);
1089
1090 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1091 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1092 /* hard_mtu is still the default - the device does not support
1093 jumbo eth frames */
1094 dev->rx_urb_size = 2048;
1095 }
1096
1097 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
1098 if (!dev->driver_priv)
1099 return -ENOMEM;
1100
1101 return 0;
1102}
1103
1104static const struct driver_info ax8817x_info = {
1105 .description = "ASIX AX8817x USB 2.0 Ethernet",
1106 .bind = ax88172_bind,
1107 .status = asix_status,
1108 .link_reset = ax88172_link_reset,
1109 .reset = ax88172_link_reset,
1110 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1111 .data = 0x00130103,
1112};
1113
1114static const struct driver_info dlink_dub_e100_info = {
1115 .description = "DLink DUB-E100 USB Ethernet",
1116 .bind = ax88172_bind,
1117 .status = asix_status,
1118 .link_reset = ax88172_link_reset,
1119 .reset = ax88172_link_reset,
1120 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1121 .data = 0x009f9d9f,
1122};
1123
1124static const struct driver_info netgear_fa120_info = {
1125 .description = "Netgear FA-120 USB Ethernet",
1126 .bind = ax88172_bind,
1127 .status = asix_status,
1128 .link_reset = ax88172_link_reset,
1129 .reset = ax88172_link_reset,
1130 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1131 .data = 0x00130103,
1132};
1133
1134static const struct driver_info hawking_uf200_info = {
1135 .description = "Hawking UF200 USB Ethernet",
1136 .bind = ax88172_bind,
1137 .status = asix_status,
1138 .link_reset = ax88172_link_reset,
1139 .reset = ax88172_link_reset,
1140 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1141 .data = 0x001f1d1f,
1142};
1143
1144static const struct driver_info ax88772_info = {
1145 .description = "ASIX AX88772 USB 2.0 Ethernet",
1146 .bind = ax88772_bind,
1147 .unbind = ax88772_unbind,
1148 .status = asix_status,
1149 .link_reset = ax88772_link_reset,
1150 .reset = ax88772_reset,
1151 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
1152 .rx_fixup = asix_rx_fixup_common,
1153 .tx_fixup = asix_tx_fixup,
1154};
1155
1156static const struct driver_info ax88772b_info = {
1157 .description = "ASIX AX88772B USB 2.0 Ethernet",
1158 .bind = ax88772_bind,
1159 .unbind = ax88772_unbind,
1160 .status = asix_status,
1161 .link_reset = ax88772_link_reset,
1162 .reset = ax88772_reset,
1163 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1164 FLAG_MULTI_PACKET,
1165 .rx_fixup = asix_rx_fixup_common,
1166 .tx_fixup = asix_tx_fixup,
1167 .data = FLAG_EEPROM_MAC,
1168};
1169
1170static const struct driver_info ax88178_info = {
1171 .description = "ASIX AX88178 USB 2.0 Ethernet",
1172 .bind = ax88178_bind,
1173 .unbind = ax88772_unbind,
1174 .status = asix_status,
1175 .link_reset = ax88178_link_reset,
1176 .reset = ax88178_reset,
1177 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1178 FLAG_MULTI_PACKET,
1179 .rx_fixup = asix_rx_fixup_common,
1180 .tx_fixup = asix_tx_fixup,
1181};
1182
1183/*
1184 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in
1185 * no-name packaging.
1186 * USB device strings are:
1187 * 1: Manufacturer: USBLINK
1188 * 2: Product: HG20F9 USB2.0
1189 * 3: Serial: 000003
1190 * Appears to be compatible with Asix 88772B.
1191 */
1192static const struct driver_info hg20f9_info = {
1193 .description = "HG20F9 USB 2.0 Ethernet",
1194 .bind = ax88772_bind,
1195 .unbind = ax88772_unbind,
1196 .status = asix_status,
1197 .link_reset = ax88772_link_reset,
1198 .reset = ax88772_reset,
1199 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1200 FLAG_MULTI_PACKET,
1201 .rx_fixup = asix_rx_fixup_common,
1202 .tx_fixup = asix_tx_fixup,
1203 .data = FLAG_EEPROM_MAC,
1204};
1205
1206static const struct usb_device_id products [] = {
1207{
1208 // Linksys USB200M
1209 USB_DEVICE (0x077b, 0x2226),
1210 .driver_info = (unsigned long) &ax8817x_info,
1211}, {
1212 // Netgear FA120
1213 USB_DEVICE (0x0846, 0x1040),
1214 .driver_info = (unsigned long) &netgear_fa120_info,
1215}, {
1216 // DLink DUB-E100
1217 USB_DEVICE (0x2001, 0x1a00),
1218 .driver_info = (unsigned long) &dlink_dub_e100_info,
1219}, {
1220 // Intellinet, ST Lab USB Ethernet
1221 USB_DEVICE (0x0b95, 0x1720),
1222 .driver_info = (unsigned long) &ax8817x_info,
1223}, {
1224 // Hawking UF200, TrendNet TU2-ET100
1225 USB_DEVICE (0x07b8, 0x420a),
1226 .driver_info = (unsigned long) &hawking_uf200_info,
1227}, {
1228 // Billionton Systems, USB2AR
1229 USB_DEVICE (0x08dd, 0x90ff),
1230 .driver_info = (unsigned long) &ax8817x_info,
1231}, {
1232 // Billionton Systems, GUSB2AM-1G-B
1233 USB_DEVICE(0x08dd, 0x0114),
1234 .driver_info = (unsigned long) &ax88178_info,
1235}, {
1236 // ATEN UC210T
1237 USB_DEVICE (0x0557, 0x2009),
1238 .driver_info = (unsigned long) &ax8817x_info,
1239}, {
1240 // Buffalo LUA-U2-KTX
1241 USB_DEVICE (0x0411, 0x003d),
1242 .driver_info = (unsigned long) &ax8817x_info,
1243}, {
1244 // Buffalo LUA-U2-GT 10/100/1000
1245 USB_DEVICE (0x0411, 0x006e),
1246 .driver_info = (unsigned long) &ax88178_info,
1247}, {
1248 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1249 USB_DEVICE (0x6189, 0x182d),
1250 .driver_info = (unsigned long) &ax8817x_info,
1251}, {
1252 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
1253 USB_DEVICE (0x0df6, 0x0056),
1254 .driver_info = (unsigned long) &ax88178_info,
1255}, {
1256 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter"
1257 USB_DEVICE (0x0df6, 0x061c),
1258 .driver_info = (unsigned long) &ax88178_info,
1259}, {
1260 // corega FEther USB2-TX
1261 USB_DEVICE (0x07aa, 0x0017),
1262 .driver_info = (unsigned long) &ax8817x_info,
1263}, {
1264 // Surecom EP-1427X-2
1265 USB_DEVICE (0x1189, 0x0893),
1266 .driver_info = (unsigned long) &ax8817x_info,
1267}, {
1268 // goodway corp usb gwusb2e
1269 USB_DEVICE (0x1631, 0x6200),
1270 .driver_info = (unsigned long) &ax8817x_info,
1271}, {
1272 // JVC MP-PRX1 Port Replicator
1273 USB_DEVICE (0x04f1, 0x3008),
1274 .driver_info = (unsigned long) &ax8817x_info,
1275}, {
1276 // Lenovo U2L100P 10/100
1277 USB_DEVICE (0x17ef, 0x7203),
1278 .driver_info = (unsigned long)&ax88772b_info,
1279}, {
1280 // ASIX AX88772B 10/100
1281 USB_DEVICE (0x0b95, 0x772b),
1282 .driver_info = (unsigned long) &ax88772b_info,
1283}, {
1284 // ASIX AX88772 10/100
1285 USB_DEVICE (0x0b95, 0x7720),
1286 .driver_info = (unsigned long) &ax88772_info,
1287}, {
1288 // ASIX AX88178 10/100/1000
1289 USB_DEVICE (0x0b95, 0x1780),
1290 .driver_info = (unsigned long) &ax88178_info,
1291}, {
1292 // Logitec LAN-GTJ/U2A
1293 USB_DEVICE (0x0789, 0x0160),
1294 .driver_info = (unsigned long) &ax88178_info,
1295}, {
1296 // Linksys USB200M Rev 2
1297 USB_DEVICE (0x13b1, 0x0018),
1298 .driver_info = (unsigned long) &ax88772_info,
1299}, {
1300 // 0Q0 cable ethernet
1301 USB_DEVICE (0x1557, 0x7720),
1302 .driver_info = (unsigned long) &ax88772_info,
1303}, {
1304 // DLink DUB-E100 H/W Ver B1
1305 USB_DEVICE (0x07d1, 0x3c05),
1306 .driver_info = (unsigned long) &ax88772_info,
1307}, {
1308 // DLink DUB-E100 H/W Ver B1 Alternate
1309 USB_DEVICE (0x2001, 0x3c05),
1310 .driver_info = (unsigned long) &ax88772_info,
1311}, {
1312 // DLink DUB-E100 H/W Ver C1
1313 USB_DEVICE (0x2001, 0x1a02),
1314 .driver_info = (unsigned long) &ax88772_info,
1315}, {
1316 // Linksys USB1000
1317 USB_DEVICE (0x1737, 0x0039),
1318 .driver_info = (unsigned long) &ax88178_info,
1319}, {
1320 // IO-DATA ETG-US2
1321 USB_DEVICE (0x04bb, 0x0930),
1322 .driver_info = (unsigned long) &ax88178_info,
1323}, {
1324 // Belkin F5D5055
1325 USB_DEVICE(0x050d, 0x5055),
1326 .driver_info = (unsigned long) &ax88178_info,
1327}, {
1328 // Apple USB Ethernet Adapter
1329 USB_DEVICE(0x05ac, 0x1402),
1330 .driver_info = (unsigned long) &ax88772_info,
1331}, {
1332 // Cables-to-Go USB Ethernet Adapter
1333 USB_DEVICE(0x0b95, 0x772a),
1334 .driver_info = (unsigned long) &ax88772_info,
1335}, {
1336 // ABOCOM for pci
1337 USB_DEVICE(0x14ea, 0xab11),
1338 .driver_info = (unsigned long) &ax88178_info,
1339}, {
1340 // ASIX 88772a
1341 USB_DEVICE(0x0db0, 0xa877),
1342 .driver_info = (unsigned long) &ax88772_info,
1343}, {
1344 // Asus USB Ethernet Adapter
1345 USB_DEVICE (0x0b95, 0x7e2b),
1346 .driver_info = (unsigned long)&ax88772b_info,
1347}, {
1348 /* ASIX 88172a demo board */
1349 USB_DEVICE(0x0b95, 0x172a),
1350 .driver_info = (unsigned long) &ax88172a_info,
1351}, {
1352 /*
1353 * USBLINK HG20F9 "USB 2.0 LAN"
1354 * Appears to have gazumped Linksys's manufacturer ID but
1355 * doesn't (yet) conflict with any known Linksys product.
1356 */
1357 USB_DEVICE(0x066b, 0x20f9),
1358 .driver_info = (unsigned long) &hg20f9_info,
1359},
1360 { }, // END
1361};
1362MODULE_DEVICE_TABLE(usb, products);
1363
1364static struct usb_driver asix_driver = {
1365 .name = DRIVER_NAME,
1366 .id_table = products,
1367 .probe = usbnet_probe,
1368 .suspend = asix_suspend,
1369 .resume = asix_resume,
1370 .reset_resume = asix_resume,
1371 .disconnect = usbnet_disconnect,
1372 .supports_autosuspend = 1,
1373 .disable_hub_initiated_lpm = 1,
1374};
1375
1376module_usb_driver(asix_driver);
1377
1378MODULE_AUTHOR("David Hollis");
1379MODULE_VERSION(DRIVER_VERSION);
1380MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1381MODULE_LICENSE("GPL");
1382