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1/*
2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Gated clock implementation
10 */
11
12#include <linux/clk-provider.h>
13#include <linux/module.h>
14#include <linux/slab.h>
15#include <linux/io.h>
16#include <linux/err.h>
17#include <linux/string.h>
18
19/**
20 * DOC: basic gatable clock which can gate and ungate it's ouput
21 *
22 * Traits of this clock:
23 * prepare - clk_(un)prepare only ensures parent is (un)prepared
24 * enable - clk_enable and clk_disable are functional & control gating
25 * rate - inherits rate from parent. No clk_set_rate support
26 * parent - fixed parent. No clk_set_parent support
27 */
28
29#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
30
31/*
32 * It works on following logic:
33 *
34 * For enabling clock, enable = 1
35 * set2dis = 1 -> clear bit -> set = 0
36 * set2dis = 0 -> set bit -> set = 1
37 *
38 * For disabling clock, enable = 0
39 * set2dis = 1 -> set bit -> set = 1
40 * set2dis = 0 -> clear bit -> set = 0
41 *
42 * So, result is always: enable xor set2dis.
43 */
44static void clk_gate_endisable(struct clk_hw *hw, int enable)
45{
46 struct clk_gate *gate = to_clk_gate(hw);
47 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
48 unsigned long flags = 0;
49 u32 reg;
50
51 set ^= enable;
52
53 if (gate->lock)
54 spin_lock_irqsave(gate->lock, flags);
55
56 if (gate->flags & CLK_GATE_HIWORD_MASK) {
57 reg = BIT(gate->bit_idx + 16);
58 if (set)
59 reg |= BIT(gate->bit_idx);
60 } else {
61 reg = clk_readl(gate->reg);
62
63 if (set)
64 reg |= BIT(gate->bit_idx);
65 else
66 reg &= ~BIT(gate->bit_idx);
67 }
68
69 clk_writel(reg, gate->reg);
70
71 if (gate->lock)
72 spin_unlock_irqrestore(gate->lock, flags);
73}
74
75static int clk_gate_enable(struct clk_hw *hw)
76{
77 clk_gate_endisable(hw, 1);
78
79 return 0;
80}
81
82static void clk_gate_disable(struct clk_hw *hw)
83{
84 clk_gate_endisable(hw, 0);
85}
86
87static int clk_gate_is_enabled(struct clk_hw *hw)
88{
89 u32 reg;
90 struct clk_gate *gate = to_clk_gate(hw);
91
92 reg = clk_readl(gate->reg);
93
94 /* if a set bit disables this clk, flip it before masking */
95 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
96 reg ^= BIT(gate->bit_idx);
97
98 reg &= BIT(gate->bit_idx);
99
100 return reg ? 1 : 0;
101}
102
103const struct clk_ops clk_gate_ops = {
104 .enable = clk_gate_enable,
105 .disable = clk_gate_disable,
106 .is_enabled = clk_gate_is_enabled,
107};
108EXPORT_SYMBOL_GPL(clk_gate_ops);
109
110/**
111 * clk_register_gate - register a gate clock with the clock framework
112 * @dev: device that is registering this clock
113 * @name: name of this clock
114 * @parent_name: name of this clock's parent
115 * @flags: framework-specific flags for this clock
116 * @reg: register address to control gating of this clock
117 * @bit_idx: which bit in the register controls gating of this clock
118 * @clk_gate_flags: gate-specific flags for this clock
119 * @lock: shared register lock for this clock
120 */
121struct clk *clk_register_gate(struct device *dev, const char *name,
122 const char *parent_name, unsigned long flags,
123 void __iomem *reg, u8 bit_idx,
124 u8 clk_gate_flags, spinlock_t *lock)
125{
126 struct clk_gate *gate;
127 struct clk *clk;
128 struct clk_init_data init;
129
130 if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
131 if (bit_idx > 16) {
132 pr_err("gate bit exceeds LOWORD field\n");
133 return ERR_PTR(-EINVAL);
134 }
135 }
136
137 /* allocate the gate */
138 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
139 if (!gate) {
140 pr_err("%s: could not allocate gated clk\n", __func__);
141 return ERR_PTR(-ENOMEM);
142 }
143
144 init.name = name;
145 init.ops = &clk_gate_ops;
146 init.flags = flags | CLK_IS_BASIC;
147 init.parent_names = (parent_name ? &parent_name: NULL);
148 init.num_parents = (parent_name ? 1 : 0);
149
150 /* struct clk_gate assignments */
151 gate->reg = reg;
152 gate->bit_idx = bit_idx;
153 gate->flags = clk_gate_flags;
154 gate->lock = lock;
155 gate->hw.init = &init;
156
157 clk = clk_register(dev, &gate->hw);
158
159 if (IS_ERR(clk))
160 kfree(gate);
161
162 return clk;
163}
164EXPORT_SYMBOL_GPL(clk_register_gate);
1/*
2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Gated clock implementation
10 */
11
12#include <linux/clk-provider.h>
13#include <linux/module.h>
14#include <linux/slab.h>
15#include <linux/io.h>
16#include <linux/err.h>
17#include <linux/string.h>
18
19/**
20 * DOC: basic gatable clock which can gate and ungate it's ouput
21 *
22 * Traits of this clock:
23 * prepare - clk_(un)prepare only ensures parent is (un)prepared
24 * enable - clk_enable and clk_disable are functional & control gating
25 * rate - inherits rate from parent. No clk_set_rate support
26 * parent - fixed parent. No clk_set_parent support
27 */
28
29/*
30 * It works on following logic:
31 *
32 * For enabling clock, enable = 1
33 * set2dis = 1 -> clear bit -> set = 0
34 * set2dis = 0 -> set bit -> set = 1
35 *
36 * For disabling clock, enable = 0
37 * set2dis = 1 -> set bit -> set = 1
38 * set2dis = 0 -> clear bit -> set = 0
39 *
40 * So, result is always: enable xor set2dis.
41 */
42static void clk_gate_endisable(struct clk_hw *hw, int enable)
43{
44 struct clk_gate *gate = to_clk_gate(hw);
45 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
46 unsigned long uninitialized_var(flags);
47 u32 reg;
48
49 set ^= enable;
50
51 if (gate->lock)
52 spin_lock_irqsave(gate->lock, flags);
53 else
54 __acquire(gate->lock);
55
56 if (gate->flags & CLK_GATE_HIWORD_MASK) {
57 reg = BIT(gate->bit_idx + 16);
58 if (set)
59 reg |= BIT(gate->bit_idx);
60 } else {
61 reg = clk_readl(gate->reg);
62
63 if (set)
64 reg |= BIT(gate->bit_idx);
65 else
66 reg &= ~BIT(gate->bit_idx);
67 }
68
69 clk_writel(reg, gate->reg);
70
71 if (gate->lock)
72 spin_unlock_irqrestore(gate->lock, flags);
73 else
74 __release(gate->lock);
75}
76
77static int clk_gate_enable(struct clk_hw *hw)
78{
79 clk_gate_endisable(hw, 1);
80
81 return 0;
82}
83
84static void clk_gate_disable(struct clk_hw *hw)
85{
86 clk_gate_endisable(hw, 0);
87}
88
89static int clk_gate_is_enabled(struct clk_hw *hw)
90{
91 u32 reg;
92 struct clk_gate *gate = to_clk_gate(hw);
93
94 reg = clk_readl(gate->reg);
95
96 /* if a set bit disables this clk, flip it before masking */
97 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
98 reg ^= BIT(gate->bit_idx);
99
100 reg &= BIT(gate->bit_idx);
101
102 return reg ? 1 : 0;
103}
104
105const struct clk_ops clk_gate_ops = {
106 .enable = clk_gate_enable,
107 .disable = clk_gate_disable,
108 .is_enabled = clk_gate_is_enabled,
109};
110EXPORT_SYMBOL_GPL(clk_gate_ops);
111
112/**
113 * clk_hw_register_gate - register a gate clock with the clock framework
114 * @dev: device that is registering this clock
115 * @name: name of this clock
116 * @parent_name: name of this clock's parent
117 * @flags: framework-specific flags for this clock
118 * @reg: register address to control gating of this clock
119 * @bit_idx: which bit in the register controls gating of this clock
120 * @clk_gate_flags: gate-specific flags for this clock
121 * @lock: shared register lock for this clock
122 */
123struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
124 const char *parent_name, unsigned long flags,
125 void __iomem *reg, u8 bit_idx,
126 u8 clk_gate_flags, spinlock_t *lock)
127{
128 struct clk_gate *gate;
129 struct clk_hw *hw;
130 struct clk_init_data init;
131 int ret;
132
133 if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
134 if (bit_idx > 15) {
135 pr_err("gate bit exceeds LOWORD field\n");
136 return ERR_PTR(-EINVAL);
137 }
138 }
139
140 /* allocate the gate */
141 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
142 if (!gate)
143 return ERR_PTR(-ENOMEM);
144
145 init.name = name;
146 init.ops = &clk_gate_ops;
147 init.flags = flags | CLK_IS_BASIC;
148 init.parent_names = parent_name ? &parent_name : NULL;
149 init.num_parents = parent_name ? 1 : 0;
150
151 /* struct clk_gate assignments */
152 gate->reg = reg;
153 gate->bit_idx = bit_idx;
154 gate->flags = clk_gate_flags;
155 gate->lock = lock;
156 gate->hw.init = &init;
157
158 hw = &gate->hw;
159 ret = clk_hw_register(dev, hw);
160 if (ret) {
161 kfree(gate);
162 hw = ERR_PTR(ret);
163 }
164
165 return hw;
166}
167EXPORT_SYMBOL_GPL(clk_hw_register_gate);
168
169struct clk *clk_register_gate(struct device *dev, const char *name,
170 const char *parent_name, unsigned long flags,
171 void __iomem *reg, u8 bit_idx,
172 u8 clk_gate_flags, spinlock_t *lock)
173{
174 struct clk_hw *hw;
175
176 hw = clk_hw_register_gate(dev, name, parent_name, flags, reg,
177 bit_idx, clk_gate_flags, lock);
178 if (IS_ERR(hw))
179 return ERR_CAST(hw);
180 return hw->clk;
181}
182EXPORT_SYMBOL_GPL(clk_register_gate);
183
184void clk_unregister_gate(struct clk *clk)
185{
186 struct clk_gate *gate;
187 struct clk_hw *hw;
188
189 hw = __clk_get_hw(clk);
190 if (!hw)
191 return;
192
193 gate = to_clk_gate(hw);
194
195 clk_unregister(clk);
196 kfree(gate);
197}
198EXPORT_SYMBOL_GPL(clk_unregister_gate);
199
200void clk_hw_unregister_gate(struct clk_hw *hw)
201{
202 struct clk_gate *gate;
203
204 gate = to_clk_gate(hw);
205
206 clk_hw_unregister(hw);
207 kfree(gate);
208}
209EXPORT_SYMBOL_GPL(clk_hw_unregister_gate);