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1/**
2 * Freecale 85xx and 86xx Global Utilties register set
3 *
4 * Authors: Jeff Brown
5 * Timur Tabi <timur@freescale.com>
6 *
7 * Copyright 2004,2007,2012 Freescale Semiconductor, Inc
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#ifndef __ASM_POWERPC_FSL_GUTS_H__
16#define __ASM_POWERPC_FSL_GUTS_H__
17#ifdef __KERNEL__
18
19/**
20 * Global Utility Registers.
21 *
22 * Not all registers defined in this structure are available on all chips, so
23 * you are expected to know whether a given register actually exists on your
24 * chip before you access it.
25 *
26 * Also, some registers are similar on different chips but have slightly
27 * different names. In these cases, one name is chosen to avoid extraneous
28 * #ifdefs.
29 */
30struct ccsr_guts {
31 __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
32 __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
33 __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
34 __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35 __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36 __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
37 u8 res018[0x20 - 0x18];
38 __be32 porcir; /* 0x.0020 - POR Configuration Information Register */
39 u8 res024[0x30 - 0x24];
40 __be32 gpiocr; /* 0x.0030 - GPIO Control Register */
41 u8 res034[0x40 - 0x34];
42 __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
43 u8 res044[0x50 - 0x44];
44 __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
45 u8 res054[0x60 - 0x54];
46 __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
47 __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
48 __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
49 u8 res06c[0x70 - 0x6c];
50 __be32 devdisr; /* 0x.0070 - Device Disable Control */
51#define CCSR_GUTS_DEVDISR_TB1 0x00001000
52#define CCSR_GUTS_DEVDISR_TB0 0x00004000
53 __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
54 u8 res078[0x7c - 0x78];
55 __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
56 __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
57 __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
58 __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
59 __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
60 __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
61 __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
62 __be32 ectrstcr; /* 0x.0098 - Exception reset control register */
63 __be32 autorstsr; /* 0x.009c - Automatic reset status register */
64 __be32 pvr; /* 0x.00a0 - Processor Version Register */
65 __be32 svr; /* 0x.00a4 - System Version Register */
66 u8 res0a8[0xb0 - 0xa8];
67 __be32 rstcr; /* 0x.00b0 - Reset Control Register */
68 u8 res0b4[0xc0 - 0xb4];
69 __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
70 Called 'elbcvselcr' on 86xx SOCs */
71 u8 res0c4[0x224 - 0xc4];
72 __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
73 __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
74 u8 res22c[0x604 - 0x22c];
75 __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
76 u8 res608[0x800 - 0x608];
77 __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
78 u8 res804[0x900 - 0x804];
79 __be32 ircr; /* 0x.0900 - Infrared Control Register */
80 u8 res904[0x908 - 0x904];
81 __be32 dmacr; /* 0x.0908 - DMA Control Register */
82 u8 res90c[0x914 - 0x90c];
83 __be32 elbccr; /* 0x.0914 - eLBC Control Register */
84 u8 res918[0xb20 - 0x918];
85 __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
86 __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
87 __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
88 u8 resb2c[0xe00 - 0xb2c];
89 __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
90 u8 rese04[0xe10 - 0xe04];
91 __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
92 u8 rese14[0xe20 - 0xe14];
93 __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
94 __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
95 u8 rese28[0xf04 - 0xe28];
96 __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
97 __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
98 u8 resf0c[0xf2c - 0xf0c];
99 __be32 itcr; /* 0x.0f2c - Internal transaction control register */
100 u8 resf30[0xf40 - 0xf30];
101 __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
102 __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
103} __attribute__ ((packed));
104
105
106/* Alternate function signal multiplex control */
107#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
108
109#ifdef CONFIG_PPC_86xx
110
111#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
112#define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */
113
114/*
115 * Set the DMACR register in the GUTS
116 *
117 * The DMACR register determines the source of initiated transfers for each
118 * channel on each DMA controller. Rather than have a bunch of repetitive
119 * macros for the bit patterns, we just have a function that calculates
120 * them.
121 *
122 * guts: Pointer to GUTS structure
123 * co: The DMA controller (0 or 1)
124 * ch: The channel on the DMA controller (0, 1, 2, or 3)
125 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
126 */
127static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
128 unsigned int co, unsigned int ch, unsigned int device)
129{
130 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
131
132 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
133}
134
135#define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000
136#define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */
137#define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */
138#define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */
139#define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */
140#define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */
141#define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */
142#define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */
143#define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */
144#define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */
145#define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */
146#define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */
147#define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008
148#define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004
149#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
150#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
151
152/*
153 * Set the DMA external control bits in the GUTS
154 *
155 * The DMA external control bits in the PMUXCR are only meaningful for
156 * channels 0 and 3. Any other channels are ignored.
157 *
158 * guts: Pointer to GUTS structure
159 * co: The DMA controller (0 or 1)
160 * ch: The channel on the DMA controller (0, 1, 2, or 3)
161 * value: the new value for the bit (0 or 1)
162 */
163static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
164 unsigned int co, unsigned int ch, unsigned int value)
165{
166 if ((ch == 0) || (ch == 3)) {
167 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
168
169 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
170 }
171}
172
173#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
174#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
175#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
176#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25
177#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000
178#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \
179 (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT)
180#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16
181#define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000
182#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT)
183#define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF
184#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK)
185
186#endif
187
188#endif
189#endif