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1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/usb.h>
24#include <linux/pci.h>
25#include <linux/slab.h>
26#include <linux/dmapool.h>
27#include <linux/dma-mapping.h>
28
29#include "xhci.h"
30#include "xhci-trace.h"
31
32/*
33 * Allocates a generic ring segment from the ring pool, sets the dma address,
34 * initializes the segment to zero, and sets the private next pointer to NULL.
35 *
36 * Section 4.11.1.1:
37 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
38 */
39static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
40 unsigned int cycle_state, gfp_t flags)
41{
42 struct xhci_segment *seg;
43 dma_addr_t dma;
44 int i;
45
46 seg = kzalloc(sizeof *seg, flags);
47 if (!seg)
48 return NULL;
49
50 seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
51 if (!seg->trbs) {
52 kfree(seg);
53 return NULL;
54 }
55
56 memset(seg->trbs, 0, TRB_SEGMENT_SIZE);
57 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
58 if (cycle_state == 0) {
59 for (i = 0; i < TRBS_PER_SEGMENT; i++)
60 seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE);
61 }
62 seg->dma = dma;
63 seg->next = NULL;
64
65 return seg;
66}
67
68static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
69{
70 if (seg->trbs) {
71 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
72 seg->trbs = NULL;
73 }
74 kfree(seg);
75}
76
77static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
78 struct xhci_segment *first)
79{
80 struct xhci_segment *seg;
81
82 seg = first->next;
83 while (seg != first) {
84 struct xhci_segment *next = seg->next;
85 xhci_segment_free(xhci, seg);
86 seg = next;
87 }
88 xhci_segment_free(xhci, first);
89}
90
91/*
92 * Make the prev segment point to the next segment.
93 *
94 * Change the last TRB in the prev segment to be a Link TRB which points to the
95 * DMA address of the next segment. The caller needs to set any Link TRB
96 * related flags, such as End TRB, Toggle Cycle, and no snoop.
97 */
98static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
99 struct xhci_segment *next, enum xhci_ring_type type)
100{
101 u32 val;
102
103 if (!prev || !next)
104 return;
105 prev->next = next;
106 if (type != TYPE_EVENT) {
107 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
108 cpu_to_le64(next->dma);
109
110 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
111 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
112 val &= ~TRB_TYPE_BITMASK;
113 val |= TRB_TYPE(TRB_LINK);
114 /* Always set the chain bit with 0.95 hardware */
115 /* Set chain bit for isoc rings on AMD 0.96 host */
116 if (xhci_link_trb_quirk(xhci) ||
117 (type == TYPE_ISOC &&
118 (xhci->quirks & XHCI_AMD_0x96_HOST)))
119 val |= TRB_CHAIN;
120 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
121 }
122}
123
124/*
125 * Link the ring to the new segments.
126 * Set Toggle Cycle for the new ring if needed.
127 */
128static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
129 struct xhci_segment *first, struct xhci_segment *last,
130 unsigned int num_segs)
131{
132 struct xhci_segment *next;
133
134 if (!ring || !first || !last)
135 return;
136
137 next = ring->enq_seg->next;
138 xhci_link_segments(xhci, ring->enq_seg, first, ring->type);
139 xhci_link_segments(xhci, last, next, ring->type);
140 ring->num_segs += num_segs;
141 ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
142
143 if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
144 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
145 &= ~cpu_to_le32(LINK_TOGGLE);
146 last->trbs[TRBS_PER_SEGMENT-1].link.control
147 |= cpu_to_le32(LINK_TOGGLE);
148 ring->last_seg = last;
149 }
150}
151
152/*
153 * We need a radix tree for mapping physical addresses of TRBs to which stream
154 * ID they belong to. We need to do this because the host controller won't tell
155 * us which stream ring the TRB came from. We could store the stream ID in an
156 * event data TRB, but that doesn't help us for the cancellation case, since the
157 * endpoint may stop before it reaches that event data TRB.
158 *
159 * The radix tree maps the upper portion of the TRB DMA address to a ring
160 * segment that has the same upper portion of DMA addresses. For example, say I
161 * have segments of size 1KB, that are always 1KB aligned. A segment may
162 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
163 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
164 * pass the radix tree a key to get the right stream ID:
165 *
166 * 0x10c90fff >> 10 = 0x43243
167 * 0x10c912c0 >> 10 = 0x43244
168 * 0x10c91400 >> 10 = 0x43245
169 *
170 * Obviously, only those TRBs with DMA addresses that are within the segment
171 * will make the radix tree return the stream ID for that ring.
172 *
173 * Caveats for the radix tree:
174 *
175 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
176 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
177 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
178 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
179 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
180 * extended systems (where the DMA address can be bigger than 32-bits),
181 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
182 */
183static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map,
184 struct xhci_ring *ring,
185 struct xhci_segment *seg,
186 gfp_t mem_flags)
187{
188 unsigned long key;
189 int ret;
190
191 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
192 /* Skip any segments that were already added. */
193 if (radix_tree_lookup(trb_address_map, key))
194 return 0;
195
196 ret = radix_tree_maybe_preload(mem_flags);
197 if (ret)
198 return ret;
199 ret = radix_tree_insert(trb_address_map,
200 key, ring);
201 radix_tree_preload_end();
202 return ret;
203}
204
205static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map,
206 struct xhci_segment *seg)
207{
208 unsigned long key;
209
210 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
211 if (radix_tree_lookup(trb_address_map, key))
212 radix_tree_delete(trb_address_map, key);
213}
214
215static int xhci_update_stream_segment_mapping(
216 struct radix_tree_root *trb_address_map,
217 struct xhci_ring *ring,
218 struct xhci_segment *first_seg,
219 struct xhci_segment *last_seg,
220 gfp_t mem_flags)
221{
222 struct xhci_segment *seg;
223 struct xhci_segment *failed_seg;
224 int ret;
225
226 if (WARN_ON_ONCE(trb_address_map == NULL))
227 return 0;
228
229 seg = first_seg;
230 do {
231 ret = xhci_insert_segment_mapping(trb_address_map,
232 ring, seg, mem_flags);
233 if (ret)
234 goto remove_streams;
235 if (seg == last_seg)
236 return 0;
237 seg = seg->next;
238 } while (seg != first_seg);
239
240 return 0;
241
242remove_streams:
243 failed_seg = seg;
244 seg = first_seg;
245 do {
246 xhci_remove_segment_mapping(trb_address_map, seg);
247 if (seg == failed_seg)
248 return ret;
249 seg = seg->next;
250 } while (seg != first_seg);
251
252 return ret;
253}
254
255static void xhci_remove_stream_mapping(struct xhci_ring *ring)
256{
257 struct xhci_segment *seg;
258
259 if (WARN_ON_ONCE(ring->trb_address_map == NULL))
260 return;
261
262 seg = ring->first_seg;
263 do {
264 xhci_remove_segment_mapping(ring->trb_address_map, seg);
265 seg = seg->next;
266 } while (seg != ring->first_seg);
267}
268
269static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags)
270{
271 return xhci_update_stream_segment_mapping(ring->trb_address_map, ring,
272 ring->first_seg, ring->last_seg, mem_flags);
273}
274
275/* XXX: Do we need the hcd structure in all these functions? */
276void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
277{
278 if (!ring)
279 return;
280
281 if (ring->first_seg) {
282 if (ring->type == TYPE_STREAM)
283 xhci_remove_stream_mapping(ring);
284 xhci_free_segments_for_ring(xhci, ring->first_seg);
285 }
286
287 kfree(ring);
288}
289
290static void xhci_initialize_ring_info(struct xhci_ring *ring,
291 unsigned int cycle_state)
292{
293 /* The ring is empty, so the enqueue pointer == dequeue pointer */
294 ring->enqueue = ring->first_seg->trbs;
295 ring->enq_seg = ring->first_seg;
296 ring->dequeue = ring->enqueue;
297 ring->deq_seg = ring->first_seg;
298 /* The ring is initialized to 0. The producer must write 1 to the cycle
299 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
300 * compare CCS to the cycle bit to check ownership, so CCS = 1.
301 *
302 * New rings are initialized with cycle state equal to 1; if we are
303 * handling ring expansion, set the cycle state equal to the old ring.
304 */
305 ring->cycle_state = cycle_state;
306 /* Not necessary for new rings, but needed for re-initialized rings */
307 ring->enq_updates = 0;
308 ring->deq_updates = 0;
309
310 /*
311 * Each segment has a link TRB, and leave an extra TRB for SW
312 * accounting purpose
313 */
314 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
315}
316
317/* Allocate segments and link them for a ring */
318static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
319 struct xhci_segment **first, struct xhci_segment **last,
320 unsigned int num_segs, unsigned int cycle_state,
321 enum xhci_ring_type type, gfp_t flags)
322{
323 struct xhci_segment *prev;
324
325 prev = xhci_segment_alloc(xhci, cycle_state, flags);
326 if (!prev)
327 return -ENOMEM;
328 num_segs--;
329
330 *first = prev;
331 while (num_segs > 0) {
332 struct xhci_segment *next;
333
334 next = xhci_segment_alloc(xhci, cycle_state, flags);
335 if (!next) {
336 prev = *first;
337 while (prev) {
338 next = prev->next;
339 xhci_segment_free(xhci, prev);
340 prev = next;
341 }
342 return -ENOMEM;
343 }
344 xhci_link_segments(xhci, prev, next, type);
345
346 prev = next;
347 num_segs--;
348 }
349 xhci_link_segments(xhci, prev, *first, type);
350 *last = prev;
351
352 return 0;
353}
354
355/**
356 * Create a new ring with zero or more segments.
357 *
358 * Link each segment together into a ring.
359 * Set the end flag and the cycle toggle bit on the last segment.
360 * See section 4.9.1 and figures 15 and 16.
361 */
362static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
363 unsigned int num_segs, unsigned int cycle_state,
364 enum xhci_ring_type type, gfp_t flags)
365{
366 struct xhci_ring *ring;
367 int ret;
368
369 ring = kzalloc(sizeof *(ring), flags);
370 if (!ring)
371 return NULL;
372
373 ring->num_segs = num_segs;
374 INIT_LIST_HEAD(&ring->td_list);
375 ring->type = type;
376 if (num_segs == 0)
377 return ring;
378
379 ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
380 &ring->last_seg, num_segs, cycle_state, type, flags);
381 if (ret)
382 goto fail;
383
384 /* Only event ring does not use link TRB */
385 if (type != TYPE_EVENT) {
386 /* See section 4.9.2.1 and 6.4.4.1 */
387 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
388 cpu_to_le32(LINK_TOGGLE);
389 }
390 xhci_initialize_ring_info(ring, cycle_state);
391 return ring;
392
393fail:
394 kfree(ring);
395 return NULL;
396}
397
398void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
399 struct xhci_virt_device *virt_dev,
400 unsigned int ep_index)
401{
402 int rings_cached;
403
404 rings_cached = virt_dev->num_rings_cached;
405 if (rings_cached < XHCI_MAX_RINGS_CACHED) {
406 virt_dev->ring_cache[rings_cached] =
407 virt_dev->eps[ep_index].ring;
408 virt_dev->num_rings_cached++;
409 xhci_dbg(xhci, "Cached old ring, "
410 "%d ring%s cached\n",
411 virt_dev->num_rings_cached,
412 (virt_dev->num_rings_cached > 1) ? "s" : "");
413 } else {
414 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
415 xhci_dbg(xhci, "Ring cache full (%d rings), "
416 "freeing ring\n",
417 virt_dev->num_rings_cached);
418 }
419 virt_dev->eps[ep_index].ring = NULL;
420}
421
422/* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
423 * pointers to the beginning of the ring.
424 */
425static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
426 struct xhci_ring *ring, unsigned int cycle_state,
427 enum xhci_ring_type type)
428{
429 struct xhci_segment *seg = ring->first_seg;
430 int i;
431
432 do {
433 memset(seg->trbs, 0,
434 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
435 if (cycle_state == 0) {
436 for (i = 0; i < TRBS_PER_SEGMENT; i++)
437 seg->trbs[i].link.control |=
438 cpu_to_le32(TRB_CYCLE);
439 }
440 /* All endpoint rings have link TRBs */
441 xhci_link_segments(xhci, seg, seg->next, type);
442 seg = seg->next;
443 } while (seg != ring->first_seg);
444 ring->type = type;
445 xhci_initialize_ring_info(ring, cycle_state);
446 /* td list should be empty since all URBs have been cancelled,
447 * but just in case...
448 */
449 INIT_LIST_HEAD(&ring->td_list);
450}
451
452/*
453 * Expand an existing ring.
454 * Look for a cached ring or allocate a new ring which has same segment numbers
455 * and link the two rings.
456 */
457int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
458 unsigned int num_trbs, gfp_t flags)
459{
460 struct xhci_segment *first;
461 struct xhci_segment *last;
462 unsigned int num_segs;
463 unsigned int num_segs_needed;
464 int ret;
465
466 num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) /
467 (TRBS_PER_SEGMENT - 1);
468
469 /* Allocate number of segments we needed, or double the ring size */
470 num_segs = ring->num_segs > num_segs_needed ?
471 ring->num_segs : num_segs_needed;
472
473 ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
474 num_segs, ring->cycle_state, ring->type, flags);
475 if (ret)
476 return -ENOMEM;
477
478 if (ring->type == TYPE_STREAM)
479 ret = xhci_update_stream_segment_mapping(ring->trb_address_map,
480 ring, first, last, flags);
481 if (ret) {
482 struct xhci_segment *next;
483 do {
484 next = first->next;
485 xhci_segment_free(xhci, first);
486 if (first == last)
487 break;
488 first = next;
489 } while (true);
490 return ret;
491 }
492
493 xhci_link_rings(xhci, ring, first, last, num_segs);
494 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
495 "ring expansion succeed, now has %d segments",
496 ring->num_segs);
497
498 return 0;
499}
500
501#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
502
503static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
504 int type, gfp_t flags)
505{
506 struct xhci_container_ctx *ctx;
507
508 if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT))
509 return NULL;
510
511 ctx = kzalloc(sizeof(*ctx), flags);
512 if (!ctx)
513 return NULL;
514
515 ctx->type = type;
516 ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
517 if (type == XHCI_CTX_TYPE_INPUT)
518 ctx->size += CTX_SIZE(xhci->hcc_params);
519
520 ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
521 if (!ctx->bytes) {
522 kfree(ctx);
523 return NULL;
524 }
525 memset(ctx->bytes, 0, ctx->size);
526 return ctx;
527}
528
529static void xhci_free_container_ctx(struct xhci_hcd *xhci,
530 struct xhci_container_ctx *ctx)
531{
532 if (!ctx)
533 return;
534 dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
535 kfree(ctx);
536}
537
538struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
539 struct xhci_container_ctx *ctx)
540{
541 if (ctx->type != XHCI_CTX_TYPE_INPUT)
542 return NULL;
543
544 return (struct xhci_input_control_ctx *)ctx->bytes;
545}
546
547struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
548 struct xhci_container_ctx *ctx)
549{
550 if (ctx->type == XHCI_CTX_TYPE_DEVICE)
551 return (struct xhci_slot_ctx *)ctx->bytes;
552
553 return (struct xhci_slot_ctx *)
554 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
555}
556
557struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
558 struct xhci_container_ctx *ctx,
559 unsigned int ep_index)
560{
561 /* increment ep index by offset of start of ep ctx array */
562 ep_index++;
563 if (ctx->type == XHCI_CTX_TYPE_INPUT)
564 ep_index++;
565
566 return (struct xhci_ep_ctx *)
567 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
568}
569
570
571/***************** Streams structures manipulation *************************/
572
573static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
574 unsigned int num_stream_ctxs,
575 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
576{
577 struct device *dev = xhci_to_hcd(xhci)->self.controller;
578 size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
579
580 if (size > MEDIUM_STREAM_ARRAY_SIZE)
581 dma_free_coherent(dev, size,
582 stream_ctx, dma);
583 else if (size <= SMALL_STREAM_ARRAY_SIZE)
584 return dma_pool_free(xhci->small_streams_pool,
585 stream_ctx, dma);
586 else
587 return dma_pool_free(xhci->medium_streams_pool,
588 stream_ctx, dma);
589}
590
591/*
592 * The stream context array for each endpoint with bulk streams enabled can
593 * vary in size, based on:
594 * - how many streams the endpoint supports,
595 * - the maximum primary stream array size the host controller supports,
596 * - and how many streams the device driver asks for.
597 *
598 * The stream context array must be a power of 2, and can be as small as
599 * 64 bytes or as large as 1MB.
600 */
601static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
602 unsigned int num_stream_ctxs, dma_addr_t *dma,
603 gfp_t mem_flags)
604{
605 struct device *dev = xhci_to_hcd(xhci)->self.controller;
606 size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
607
608 if (size > MEDIUM_STREAM_ARRAY_SIZE)
609 return dma_alloc_coherent(dev, size,
610 dma, mem_flags);
611 else if (size <= SMALL_STREAM_ARRAY_SIZE)
612 return dma_pool_alloc(xhci->small_streams_pool,
613 mem_flags, dma);
614 else
615 return dma_pool_alloc(xhci->medium_streams_pool,
616 mem_flags, dma);
617}
618
619struct xhci_ring *xhci_dma_to_transfer_ring(
620 struct xhci_virt_ep *ep,
621 u64 address)
622{
623 if (ep->ep_state & EP_HAS_STREAMS)
624 return radix_tree_lookup(&ep->stream_info->trb_address_map,
625 address >> TRB_SEGMENT_SHIFT);
626 return ep->ring;
627}
628
629struct xhci_ring *xhci_stream_id_to_ring(
630 struct xhci_virt_device *dev,
631 unsigned int ep_index,
632 unsigned int stream_id)
633{
634 struct xhci_virt_ep *ep = &dev->eps[ep_index];
635
636 if (stream_id == 0)
637 return ep->ring;
638 if (!ep->stream_info)
639 return NULL;
640
641 if (stream_id > ep->stream_info->num_streams)
642 return NULL;
643 return ep->stream_info->stream_rings[stream_id];
644}
645
646/*
647 * Change an endpoint's internal structure so it supports stream IDs. The
648 * number of requested streams includes stream 0, which cannot be used by device
649 * drivers.
650 *
651 * The number of stream contexts in the stream context array may be bigger than
652 * the number of streams the driver wants to use. This is because the number of
653 * stream context array entries must be a power of two.
654 */
655struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
656 unsigned int num_stream_ctxs,
657 unsigned int num_streams, gfp_t mem_flags)
658{
659 struct xhci_stream_info *stream_info;
660 u32 cur_stream;
661 struct xhci_ring *cur_ring;
662 u64 addr;
663 int ret;
664
665 xhci_dbg(xhci, "Allocating %u streams and %u "
666 "stream context array entries.\n",
667 num_streams, num_stream_ctxs);
668 if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
669 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
670 return NULL;
671 }
672 xhci->cmd_ring_reserved_trbs++;
673
674 stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
675 if (!stream_info)
676 goto cleanup_trbs;
677
678 stream_info->num_streams = num_streams;
679 stream_info->num_stream_ctxs = num_stream_ctxs;
680
681 /* Initialize the array of virtual pointers to stream rings. */
682 stream_info->stream_rings = kzalloc(
683 sizeof(struct xhci_ring *)*num_streams,
684 mem_flags);
685 if (!stream_info->stream_rings)
686 goto cleanup_info;
687
688 /* Initialize the array of DMA addresses for stream rings for the HW. */
689 stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
690 num_stream_ctxs, &stream_info->ctx_array_dma,
691 mem_flags);
692 if (!stream_info->stream_ctx_array)
693 goto cleanup_ctx;
694 memset(stream_info->stream_ctx_array, 0,
695 sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
696
697 /* Allocate everything needed to free the stream rings later */
698 stream_info->free_streams_command =
699 xhci_alloc_command(xhci, true, true, mem_flags);
700 if (!stream_info->free_streams_command)
701 goto cleanup_ctx;
702
703 INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
704
705 /* Allocate rings for all the streams that the driver will use,
706 * and add their segment DMA addresses to the radix tree.
707 * Stream 0 is reserved.
708 */
709 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
710 stream_info->stream_rings[cur_stream] =
711 xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, mem_flags);
712 cur_ring = stream_info->stream_rings[cur_stream];
713 if (!cur_ring)
714 goto cleanup_rings;
715 cur_ring->stream_id = cur_stream;
716 cur_ring->trb_address_map = &stream_info->trb_address_map;
717 /* Set deq ptr, cycle bit, and stream context type */
718 addr = cur_ring->first_seg->dma |
719 SCT_FOR_CTX(SCT_PRI_TR) |
720 cur_ring->cycle_state;
721 stream_info->stream_ctx_array[cur_stream].stream_ring =
722 cpu_to_le64(addr);
723 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
724 cur_stream, (unsigned long long) addr);
725
726 ret = xhci_update_stream_mapping(cur_ring, mem_flags);
727 if (ret) {
728 xhci_ring_free(xhci, cur_ring);
729 stream_info->stream_rings[cur_stream] = NULL;
730 goto cleanup_rings;
731 }
732 }
733 /* Leave the other unused stream ring pointers in the stream context
734 * array initialized to zero. This will cause the xHC to give us an
735 * error if the device asks for a stream ID we don't have setup (if it
736 * was any other way, the host controller would assume the ring is
737 * "empty" and wait forever for data to be queued to that stream ID).
738 */
739
740 return stream_info;
741
742cleanup_rings:
743 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
744 cur_ring = stream_info->stream_rings[cur_stream];
745 if (cur_ring) {
746 xhci_ring_free(xhci, cur_ring);
747 stream_info->stream_rings[cur_stream] = NULL;
748 }
749 }
750 xhci_free_command(xhci, stream_info->free_streams_command);
751cleanup_ctx:
752 kfree(stream_info->stream_rings);
753cleanup_info:
754 kfree(stream_info);
755cleanup_trbs:
756 xhci->cmd_ring_reserved_trbs--;
757 return NULL;
758}
759/*
760 * Sets the MaxPStreams field and the Linear Stream Array field.
761 * Sets the dequeue pointer to the stream context array.
762 */
763void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
764 struct xhci_ep_ctx *ep_ctx,
765 struct xhci_stream_info *stream_info)
766{
767 u32 max_primary_streams;
768 /* MaxPStreams is the number of stream context array entries, not the
769 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
770 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
771 */
772 max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
773 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
774 "Setting number of stream ctx array entries to %u",
775 1 << (max_primary_streams + 1));
776 ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
777 ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
778 | EP_HAS_LSA);
779 ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
780}
781
782/*
783 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
784 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
785 * not at the beginning of the ring).
786 */
787void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
788 struct xhci_ep_ctx *ep_ctx,
789 struct xhci_virt_ep *ep)
790{
791 dma_addr_t addr;
792 ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
793 addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
794 ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state);
795}
796
797/* Frees all stream contexts associated with the endpoint,
798 *
799 * Caller should fix the endpoint context streams fields.
800 */
801void xhci_free_stream_info(struct xhci_hcd *xhci,
802 struct xhci_stream_info *stream_info)
803{
804 int cur_stream;
805 struct xhci_ring *cur_ring;
806
807 if (!stream_info)
808 return;
809
810 for (cur_stream = 1; cur_stream < stream_info->num_streams;
811 cur_stream++) {
812 cur_ring = stream_info->stream_rings[cur_stream];
813 if (cur_ring) {
814 xhci_ring_free(xhci, cur_ring);
815 stream_info->stream_rings[cur_stream] = NULL;
816 }
817 }
818 xhci_free_command(xhci, stream_info->free_streams_command);
819 xhci->cmd_ring_reserved_trbs--;
820 if (stream_info->stream_ctx_array)
821 xhci_free_stream_ctx(xhci,
822 stream_info->num_stream_ctxs,
823 stream_info->stream_ctx_array,
824 stream_info->ctx_array_dma);
825
826 kfree(stream_info->stream_rings);
827 kfree(stream_info);
828}
829
830
831/***************** Device context manipulation *************************/
832
833static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
834 struct xhci_virt_ep *ep)
835{
836 init_timer(&ep->stop_cmd_timer);
837 ep->stop_cmd_timer.data = (unsigned long) ep;
838 ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
839 ep->xhci = xhci;
840}
841
842static void xhci_free_tt_info(struct xhci_hcd *xhci,
843 struct xhci_virt_device *virt_dev,
844 int slot_id)
845{
846 struct list_head *tt_list_head;
847 struct xhci_tt_bw_info *tt_info, *next;
848 bool slot_found = false;
849
850 /* If the device never made it past the Set Address stage,
851 * it may not have the real_port set correctly.
852 */
853 if (virt_dev->real_port == 0 ||
854 virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
855 xhci_dbg(xhci, "Bad real port.\n");
856 return;
857 }
858
859 tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
860 list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
861 /* Multi-TT hubs will have more than one entry */
862 if (tt_info->slot_id == slot_id) {
863 slot_found = true;
864 list_del(&tt_info->tt_list);
865 kfree(tt_info);
866 } else if (slot_found) {
867 break;
868 }
869 }
870}
871
872int xhci_alloc_tt_info(struct xhci_hcd *xhci,
873 struct xhci_virt_device *virt_dev,
874 struct usb_device *hdev,
875 struct usb_tt *tt, gfp_t mem_flags)
876{
877 struct xhci_tt_bw_info *tt_info;
878 unsigned int num_ports;
879 int i, j;
880
881 if (!tt->multi)
882 num_ports = 1;
883 else
884 num_ports = hdev->maxchild;
885
886 for (i = 0; i < num_ports; i++, tt_info++) {
887 struct xhci_interval_bw_table *bw_table;
888
889 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
890 if (!tt_info)
891 goto free_tts;
892 INIT_LIST_HEAD(&tt_info->tt_list);
893 list_add(&tt_info->tt_list,
894 &xhci->rh_bw[virt_dev->real_port - 1].tts);
895 tt_info->slot_id = virt_dev->udev->slot_id;
896 if (tt->multi)
897 tt_info->ttport = i+1;
898 bw_table = &tt_info->bw_table;
899 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
900 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
901 }
902 return 0;
903
904free_tts:
905 xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
906 return -ENOMEM;
907}
908
909
910/* All the xhci_tds in the ring's TD list should be freed at this point.
911 * Should be called with xhci->lock held if there is any chance the TT lists
912 * will be manipulated by the configure endpoint, allocate device, or update
913 * hub functions while this function is removing the TT entries from the list.
914 */
915void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
916{
917 struct xhci_virt_device *dev;
918 int i;
919 int old_active_eps = 0;
920
921 /* Slot ID 0 is reserved */
922 if (slot_id == 0 || !xhci->devs[slot_id])
923 return;
924
925 dev = xhci->devs[slot_id];
926 xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
927 if (!dev)
928 return;
929
930 if (dev->tt_info)
931 old_active_eps = dev->tt_info->active_eps;
932
933 for (i = 0; i < 31; ++i) {
934 if (dev->eps[i].ring)
935 xhci_ring_free(xhci, dev->eps[i].ring);
936 if (dev->eps[i].stream_info)
937 xhci_free_stream_info(xhci,
938 dev->eps[i].stream_info);
939 /* Endpoints on the TT/root port lists should have been removed
940 * when usb_disable_device() was called for the device.
941 * We can't drop them anyway, because the udev might have gone
942 * away by this point, and we can't tell what speed it was.
943 */
944 if (!list_empty(&dev->eps[i].bw_endpoint_list))
945 xhci_warn(xhci, "Slot %u endpoint %u "
946 "not removed from BW list!\n",
947 slot_id, i);
948 }
949 /* If this is a hub, free the TT(s) from the TT list */
950 xhci_free_tt_info(xhci, dev, slot_id);
951 /* If necessary, update the number of active TTs on this root port */
952 xhci_update_tt_active_eps(xhci, dev, old_active_eps);
953
954 if (dev->ring_cache) {
955 for (i = 0; i < dev->num_rings_cached; i++)
956 xhci_ring_free(xhci, dev->ring_cache[i]);
957 kfree(dev->ring_cache);
958 }
959
960 if (dev->in_ctx)
961 xhci_free_container_ctx(xhci, dev->in_ctx);
962 if (dev->out_ctx)
963 xhci_free_container_ctx(xhci, dev->out_ctx);
964
965 kfree(xhci->devs[slot_id]);
966 xhci->devs[slot_id] = NULL;
967}
968
969int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
970 struct usb_device *udev, gfp_t flags)
971{
972 struct xhci_virt_device *dev;
973 int i;
974
975 /* Slot ID 0 is reserved */
976 if (slot_id == 0 || xhci->devs[slot_id]) {
977 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
978 return 0;
979 }
980
981 xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
982 if (!xhci->devs[slot_id])
983 return 0;
984 dev = xhci->devs[slot_id];
985
986 /* Allocate the (output) device context that will be used in the HC. */
987 dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
988 if (!dev->out_ctx)
989 goto fail;
990
991 xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
992 (unsigned long long)dev->out_ctx->dma);
993
994 /* Allocate the (input) device context for address device command */
995 dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
996 if (!dev->in_ctx)
997 goto fail;
998
999 xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
1000 (unsigned long long)dev->in_ctx->dma);
1001
1002 /* Initialize the cancellation list and watchdog timers for each ep */
1003 for (i = 0; i < 31; i++) {
1004 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
1005 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
1006 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
1007 }
1008
1009 /* Allocate endpoint 0 ring */
1010 dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, flags);
1011 if (!dev->eps[0].ring)
1012 goto fail;
1013
1014 /* Allocate pointers to the ring cache */
1015 dev->ring_cache = kzalloc(
1016 sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
1017 flags);
1018 if (!dev->ring_cache)
1019 goto fail;
1020 dev->num_rings_cached = 0;
1021
1022 init_completion(&dev->cmd_completion);
1023 INIT_LIST_HEAD(&dev->cmd_list);
1024 dev->udev = udev;
1025
1026 /* Point to output device context in dcbaa. */
1027 xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
1028 xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
1029 slot_id,
1030 &xhci->dcbaa->dev_context_ptrs[slot_id],
1031 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
1032
1033 return 1;
1034fail:
1035 xhci_free_virt_device(xhci, slot_id);
1036 return 0;
1037}
1038
1039void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1040 struct usb_device *udev)
1041{
1042 struct xhci_virt_device *virt_dev;
1043 struct xhci_ep_ctx *ep0_ctx;
1044 struct xhci_ring *ep_ring;
1045
1046 virt_dev = xhci->devs[udev->slot_id];
1047 ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1048 ep_ring = virt_dev->eps[0].ring;
1049 /*
1050 * FIXME we don't keep track of the dequeue pointer very well after a
1051 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1052 * host to our enqueue pointer. This should only be called after a
1053 * configured device has reset, so all control transfers should have
1054 * been completed or cancelled before the reset.
1055 */
1056 ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1057 ep_ring->enqueue)
1058 | ep_ring->cycle_state);
1059}
1060
1061/*
1062 * The xHCI roothub may have ports of differing speeds in any order in the port
1063 * status registers. xhci->port_array provides an array of the port speed for
1064 * each offset into the port status registers.
1065 *
1066 * The xHCI hardware wants to know the roothub port number that the USB device
1067 * is attached to (or the roothub port its ancestor hub is attached to). All we
1068 * know is the index of that port under either the USB 2.0 or the USB 3.0
1069 * roothub, but that doesn't give us the real index into the HW port status
1070 * registers. Call xhci_find_raw_port_number() to get real index.
1071 */
1072static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1073 struct usb_device *udev)
1074{
1075 struct usb_device *top_dev;
1076 struct usb_hcd *hcd;
1077
1078 if (udev->speed == USB_SPEED_SUPER)
1079 hcd = xhci->shared_hcd;
1080 else
1081 hcd = xhci->main_hcd;
1082
1083 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1084 top_dev = top_dev->parent)
1085 /* Found device below root hub */;
1086
1087 return xhci_find_raw_port_number(hcd, top_dev->portnum);
1088}
1089
1090/* Setup an xHCI virtual device for a Set Address command */
1091int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1092{
1093 struct xhci_virt_device *dev;
1094 struct xhci_ep_ctx *ep0_ctx;
1095 struct xhci_slot_ctx *slot_ctx;
1096 u32 port_num;
1097 u32 max_packets;
1098 struct usb_device *top_dev;
1099
1100 dev = xhci->devs[udev->slot_id];
1101 /* Slot ID 0 is reserved */
1102 if (udev->slot_id == 0 || !dev) {
1103 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1104 udev->slot_id);
1105 return -EINVAL;
1106 }
1107 ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1108 slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1109
1110 /* 3) Only the control endpoint is valid - one endpoint context */
1111 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1112 switch (udev->speed) {
1113 case USB_SPEED_SUPER:
1114 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1115 max_packets = MAX_PACKET(512);
1116 break;
1117 case USB_SPEED_HIGH:
1118 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1119 max_packets = MAX_PACKET(64);
1120 break;
1121 /* USB core guesses at a 64-byte max packet first for FS devices */
1122 case USB_SPEED_FULL:
1123 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1124 max_packets = MAX_PACKET(64);
1125 break;
1126 case USB_SPEED_LOW:
1127 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1128 max_packets = MAX_PACKET(8);
1129 break;
1130 case USB_SPEED_WIRELESS:
1131 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1132 return -EINVAL;
1133 break;
1134 default:
1135 /* Speed was set earlier, this shouldn't happen. */
1136 return -EINVAL;
1137 }
1138 /* Find the root hub port this device is under */
1139 port_num = xhci_find_real_port_number(xhci, udev);
1140 if (!port_num)
1141 return -EINVAL;
1142 slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1143 /* Set the port number in the virtual_device to the faked port number */
1144 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1145 top_dev = top_dev->parent)
1146 /* Found device below root hub */;
1147 dev->fake_port = top_dev->portnum;
1148 dev->real_port = port_num;
1149 xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1150 xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1151
1152 /* Find the right bandwidth table that this device will be a part of.
1153 * If this is a full speed device attached directly to a root port (or a
1154 * decendent of one), it counts as a primary bandwidth domain, not a
1155 * secondary bandwidth domain under a TT. An xhci_tt_info structure
1156 * will never be created for the HS root hub.
1157 */
1158 if (!udev->tt || !udev->tt->hub->parent) {
1159 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1160 } else {
1161 struct xhci_root_port_bw_info *rh_bw;
1162 struct xhci_tt_bw_info *tt_bw;
1163
1164 rh_bw = &xhci->rh_bw[port_num - 1];
1165 /* Find the right TT. */
1166 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1167 if (tt_bw->slot_id != udev->tt->hub->slot_id)
1168 continue;
1169
1170 if (!dev->udev->tt->multi ||
1171 (udev->tt->multi &&
1172 tt_bw->ttport == dev->udev->ttport)) {
1173 dev->bw_table = &tt_bw->bw_table;
1174 dev->tt_info = tt_bw;
1175 break;
1176 }
1177 }
1178 if (!dev->tt_info)
1179 xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1180 }
1181
1182 /* Is this a LS/FS device under an external HS hub? */
1183 if (udev->tt && udev->tt->hub->parent) {
1184 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1185 (udev->ttport << 8));
1186 if (udev->tt->multi)
1187 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1188 }
1189 xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1190 xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1191
1192 /* Step 4 - ring already allocated */
1193 /* Step 5 */
1194 ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1195
1196 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1197 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1198 max_packets);
1199
1200 ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1201 dev->eps[0].ring->cycle_state);
1202
1203 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1204
1205 return 0;
1206}
1207
1208/*
1209 * Convert interval expressed as 2^(bInterval - 1) == interval into
1210 * straight exponent value 2^n == interval.
1211 *
1212 */
1213static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1214 struct usb_host_endpoint *ep)
1215{
1216 unsigned int interval;
1217
1218 interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1219 if (interval != ep->desc.bInterval - 1)
1220 dev_warn(&udev->dev,
1221 "ep %#x - rounding interval to %d %sframes\n",
1222 ep->desc.bEndpointAddress,
1223 1 << interval,
1224 udev->speed == USB_SPEED_FULL ? "" : "micro");
1225
1226 if (udev->speed == USB_SPEED_FULL) {
1227 /*
1228 * Full speed isoc endpoints specify interval in frames,
1229 * not microframes. We are using microframes everywhere,
1230 * so adjust accordingly.
1231 */
1232 interval += 3; /* 1 frame = 2^3 uframes */
1233 }
1234
1235 return interval;
1236}
1237
1238/*
1239 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1240 * microframes, rounded down to nearest power of 2.
1241 */
1242static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1243 struct usb_host_endpoint *ep, unsigned int desc_interval,
1244 unsigned int min_exponent, unsigned int max_exponent)
1245{
1246 unsigned int interval;
1247
1248 interval = fls(desc_interval) - 1;
1249 interval = clamp_val(interval, min_exponent, max_exponent);
1250 if ((1 << interval) != desc_interval)
1251 dev_warn(&udev->dev,
1252 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1253 ep->desc.bEndpointAddress,
1254 1 << interval,
1255 desc_interval);
1256
1257 return interval;
1258}
1259
1260static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1261 struct usb_host_endpoint *ep)
1262{
1263 if (ep->desc.bInterval == 0)
1264 return 0;
1265 return xhci_microframes_to_exponent(udev, ep,
1266 ep->desc.bInterval, 0, 15);
1267}
1268
1269
1270static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1271 struct usb_host_endpoint *ep)
1272{
1273 return xhci_microframes_to_exponent(udev, ep,
1274 ep->desc.bInterval * 8, 3, 10);
1275}
1276
1277/* Return the polling or NAK interval.
1278 *
1279 * The polling interval is expressed in "microframes". If xHCI's Interval field
1280 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1281 *
1282 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1283 * is set to 0.
1284 */
1285static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1286 struct usb_host_endpoint *ep)
1287{
1288 unsigned int interval = 0;
1289
1290 switch (udev->speed) {
1291 case USB_SPEED_HIGH:
1292 /* Max NAK rate */
1293 if (usb_endpoint_xfer_control(&ep->desc) ||
1294 usb_endpoint_xfer_bulk(&ep->desc)) {
1295 interval = xhci_parse_microframe_interval(udev, ep);
1296 break;
1297 }
1298 /* Fall through - SS and HS isoc/int have same decoding */
1299
1300 case USB_SPEED_SUPER:
1301 if (usb_endpoint_xfer_int(&ep->desc) ||
1302 usb_endpoint_xfer_isoc(&ep->desc)) {
1303 interval = xhci_parse_exponent_interval(udev, ep);
1304 }
1305 break;
1306
1307 case USB_SPEED_FULL:
1308 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1309 interval = xhci_parse_exponent_interval(udev, ep);
1310 break;
1311 }
1312 /*
1313 * Fall through for interrupt endpoint interval decoding
1314 * since it uses the same rules as low speed interrupt
1315 * endpoints.
1316 */
1317
1318 case USB_SPEED_LOW:
1319 if (usb_endpoint_xfer_int(&ep->desc) ||
1320 usb_endpoint_xfer_isoc(&ep->desc)) {
1321
1322 interval = xhci_parse_frame_interval(udev, ep);
1323 }
1324 break;
1325
1326 default:
1327 BUG();
1328 }
1329 return EP_INTERVAL(interval);
1330}
1331
1332/* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1333 * High speed endpoint descriptors can define "the number of additional
1334 * transaction opportunities per microframe", but that goes in the Max Burst
1335 * endpoint context field.
1336 */
1337static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1338 struct usb_host_endpoint *ep)
1339{
1340 if (udev->speed != USB_SPEED_SUPER ||
1341 !usb_endpoint_xfer_isoc(&ep->desc))
1342 return 0;
1343 return ep->ss_ep_comp.bmAttributes;
1344}
1345
1346static u32 xhci_get_endpoint_type(struct usb_device *udev,
1347 struct usb_host_endpoint *ep)
1348{
1349 int in;
1350 u32 type;
1351
1352 in = usb_endpoint_dir_in(&ep->desc);
1353 if (usb_endpoint_xfer_control(&ep->desc)) {
1354 type = EP_TYPE(CTRL_EP);
1355 } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1356 if (in)
1357 type = EP_TYPE(BULK_IN_EP);
1358 else
1359 type = EP_TYPE(BULK_OUT_EP);
1360 } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1361 if (in)
1362 type = EP_TYPE(ISOC_IN_EP);
1363 else
1364 type = EP_TYPE(ISOC_OUT_EP);
1365 } else if (usb_endpoint_xfer_int(&ep->desc)) {
1366 if (in)
1367 type = EP_TYPE(INT_IN_EP);
1368 else
1369 type = EP_TYPE(INT_OUT_EP);
1370 } else {
1371 type = 0;
1372 }
1373 return type;
1374}
1375
1376/* Return the maximum endpoint service interval time (ESIT) payload.
1377 * Basically, this is the maxpacket size, multiplied by the burst size
1378 * and mult size.
1379 */
1380static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1381 struct usb_device *udev,
1382 struct usb_host_endpoint *ep)
1383{
1384 int max_burst;
1385 int max_packet;
1386
1387 /* Only applies for interrupt or isochronous endpoints */
1388 if (usb_endpoint_xfer_control(&ep->desc) ||
1389 usb_endpoint_xfer_bulk(&ep->desc))
1390 return 0;
1391
1392 if (udev->speed == USB_SPEED_SUPER)
1393 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1394
1395 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1396 max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1397 /* A 0 in max burst means 1 transfer per ESIT */
1398 return max_packet * (max_burst + 1);
1399}
1400
1401/* Set up an endpoint with one ring segment. Do not allocate stream rings.
1402 * Drivers will have to call usb_alloc_streams() to do that.
1403 */
1404int xhci_endpoint_init(struct xhci_hcd *xhci,
1405 struct xhci_virt_device *virt_dev,
1406 struct usb_device *udev,
1407 struct usb_host_endpoint *ep,
1408 gfp_t mem_flags)
1409{
1410 unsigned int ep_index;
1411 struct xhci_ep_ctx *ep_ctx;
1412 struct xhci_ring *ep_ring;
1413 unsigned int max_packet;
1414 unsigned int max_burst;
1415 enum xhci_ring_type type;
1416 u32 max_esit_payload;
1417 u32 endpoint_type;
1418
1419 ep_index = xhci_get_endpoint_index(&ep->desc);
1420 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1421
1422 endpoint_type = xhci_get_endpoint_type(udev, ep);
1423 if (!endpoint_type)
1424 return -EINVAL;
1425 ep_ctx->ep_info2 = cpu_to_le32(endpoint_type);
1426
1427 type = usb_endpoint_type(&ep->desc);
1428 /* Set up the endpoint ring */
1429 virt_dev->eps[ep_index].new_ring =
1430 xhci_ring_alloc(xhci, 2, 1, type, mem_flags);
1431 if (!virt_dev->eps[ep_index].new_ring) {
1432 /* Attempt to use the ring cache */
1433 if (virt_dev->num_rings_cached == 0)
1434 return -ENOMEM;
1435 virt_dev->eps[ep_index].new_ring =
1436 virt_dev->ring_cache[virt_dev->num_rings_cached];
1437 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1438 virt_dev->num_rings_cached--;
1439 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1440 1, type);
1441 }
1442 virt_dev->eps[ep_index].skip = false;
1443 ep_ring = virt_dev->eps[ep_index].new_ring;
1444 ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1445
1446 ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1447 | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1448
1449 /* FIXME dig Mult and streams info out of ep companion desc */
1450
1451 /* Allow 3 retries for everything but isoc;
1452 * CErr shall be set to 0 for Isoch endpoints.
1453 */
1454 if (!usb_endpoint_xfer_isoc(&ep->desc))
1455 ep_ctx->ep_info2 |= cpu_to_le32(ERROR_COUNT(3));
1456 else
1457 ep_ctx->ep_info2 |= cpu_to_le32(ERROR_COUNT(0));
1458
1459 /* Set the max packet size and max burst */
1460 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1461 max_burst = 0;
1462 switch (udev->speed) {
1463 case USB_SPEED_SUPER:
1464 /* dig out max burst from ep companion desc */
1465 max_burst = ep->ss_ep_comp.bMaxBurst;
1466 break;
1467 case USB_SPEED_HIGH:
1468 /* Some devices get this wrong */
1469 if (usb_endpoint_xfer_bulk(&ep->desc))
1470 max_packet = 512;
1471 /* bits 11:12 specify the number of additional transaction
1472 * opportunities per microframe (USB 2.0, section 9.6.6)
1473 */
1474 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1475 usb_endpoint_xfer_int(&ep->desc)) {
1476 max_burst = (usb_endpoint_maxp(&ep->desc)
1477 & 0x1800) >> 11;
1478 }
1479 break;
1480 case USB_SPEED_FULL:
1481 case USB_SPEED_LOW:
1482 break;
1483 default:
1484 BUG();
1485 }
1486 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet) |
1487 MAX_BURST(max_burst));
1488 max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1489 ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1490
1491 /*
1492 * XXX no idea how to calculate the average TRB buffer length for bulk
1493 * endpoints, as the driver gives us no clue how big each scatter gather
1494 * list entry (or buffer) is going to be.
1495 *
1496 * For isochronous and interrupt endpoints, we set it to the max
1497 * available, until we have new API in the USB core to allow drivers to
1498 * declare how much bandwidth they actually need.
1499 *
1500 * Normally, it would be calculated by taking the total of the buffer
1501 * lengths in the TD and then dividing by the number of TRBs in a TD,
1502 * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't
1503 * use Event Data TRBs, and we don't chain in a link TRB on short
1504 * transfers, we're basically dividing by 1.
1505 *
1506 * xHCI 1.0 specification indicates that the Average TRB Length should
1507 * be set to 8 for control endpoints.
1508 */
1509 if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1510 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1511 else
1512 ep_ctx->tx_info |=
1513 cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1514
1515 /* FIXME Debug endpoint context */
1516 return 0;
1517}
1518
1519void xhci_endpoint_zero(struct xhci_hcd *xhci,
1520 struct xhci_virt_device *virt_dev,
1521 struct usb_host_endpoint *ep)
1522{
1523 unsigned int ep_index;
1524 struct xhci_ep_ctx *ep_ctx;
1525
1526 ep_index = xhci_get_endpoint_index(&ep->desc);
1527 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1528
1529 ep_ctx->ep_info = 0;
1530 ep_ctx->ep_info2 = 0;
1531 ep_ctx->deq = 0;
1532 ep_ctx->tx_info = 0;
1533 /* Don't free the endpoint ring until the set interface or configuration
1534 * request succeeds.
1535 */
1536}
1537
1538void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1539{
1540 bw_info->ep_interval = 0;
1541 bw_info->mult = 0;
1542 bw_info->num_packets = 0;
1543 bw_info->max_packet_size = 0;
1544 bw_info->type = 0;
1545 bw_info->max_esit_payload = 0;
1546}
1547
1548void xhci_update_bw_info(struct xhci_hcd *xhci,
1549 struct xhci_container_ctx *in_ctx,
1550 struct xhci_input_control_ctx *ctrl_ctx,
1551 struct xhci_virt_device *virt_dev)
1552{
1553 struct xhci_bw_info *bw_info;
1554 struct xhci_ep_ctx *ep_ctx;
1555 unsigned int ep_type;
1556 int i;
1557
1558 for (i = 1; i < 31; ++i) {
1559 bw_info = &virt_dev->eps[i].bw_info;
1560
1561 /* We can't tell what endpoint type is being dropped, but
1562 * unconditionally clearing the bandwidth info for non-periodic
1563 * endpoints should be harmless because the info will never be
1564 * set in the first place.
1565 */
1566 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1567 /* Dropped endpoint */
1568 xhci_clear_endpoint_bw_info(bw_info);
1569 continue;
1570 }
1571
1572 if (EP_IS_ADDED(ctrl_ctx, i)) {
1573 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1574 ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1575
1576 /* Ignore non-periodic endpoints */
1577 if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1578 ep_type != ISOC_IN_EP &&
1579 ep_type != INT_IN_EP)
1580 continue;
1581
1582 /* Added or changed endpoint */
1583 bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1584 le32_to_cpu(ep_ctx->ep_info));
1585 /* Number of packets and mult are zero-based in the
1586 * input context, but we want one-based for the
1587 * interval table.
1588 */
1589 bw_info->mult = CTX_TO_EP_MULT(
1590 le32_to_cpu(ep_ctx->ep_info)) + 1;
1591 bw_info->num_packets = CTX_TO_MAX_BURST(
1592 le32_to_cpu(ep_ctx->ep_info2)) + 1;
1593 bw_info->max_packet_size = MAX_PACKET_DECODED(
1594 le32_to_cpu(ep_ctx->ep_info2));
1595 bw_info->type = ep_type;
1596 bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1597 le32_to_cpu(ep_ctx->tx_info));
1598 }
1599 }
1600}
1601
1602/* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1603 * Useful when you want to change one particular aspect of the endpoint and then
1604 * issue a configure endpoint command.
1605 */
1606void xhci_endpoint_copy(struct xhci_hcd *xhci,
1607 struct xhci_container_ctx *in_ctx,
1608 struct xhci_container_ctx *out_ctx,
1609 unsigned int ep_index)
1610{
1611 struct xhci_ep_ctx *out_ep_ctx;
1612 struct xhci_ep_ctx *in_ep_ctx;
1613
1614 out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1615 in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1616
1617 in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1618 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1619 in_ep_ctx->deq = out_ep_ctx->deq;
1620 in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1621}
1622
1623/* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1624 * Useful when you want to change one particular aspect of the endpoint and then
1625 * issue a configure endpoint command. Only the context entries field matters,
1626 * but we'll copy the whole thing anyway.
1627 */
1628void xhci_slot_copy(struct xhci_hcd *xhci,
1629 struct xhci_container_ctx *in_ctx,
1630 struct xhci_container_ctx *out_ctx)
1631{
1632 struct xhci_slot_ctx *in_slot_ctx;
1633 struct xhci_slot_ctx *out_slot_ctx;
1634
1635 in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1636 out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1637
1638 in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1639 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1640 in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1641 in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1642}
1643
1644/* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1645static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1646{
1647 int i;
1648 struct device *dev = xhci_to_hcd(xhci)->self.controller;
1649 int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1650
1651 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1652 "Allocating %d scratchpad buffers", num_sp);
1653
1654 if (!num_sp)
1655 return 0;
1656
1657 xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1658 if (!xhci->scratchpad)
1659 goto fail_sp;
1660
1661 xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1662 num_sp * sizeof(u64),
1663 &xhci->scratchpad->sp_dma, flags);
1664 if (!xhci->scratchpad->sp_array)
1665 goto fail_sp2;
1666
1667 xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1668 if (!xhci->scratchpad->sp_buffers)
1669 goto fail_sp3;
1670
1671 xhci->scratchpad->sp_dma_buffers =
1672 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1673
1674 if (!xhci->scratchpad->sp_dma_buffers)
1675 goto fail_sp4;
1676
1677 xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1678 for (i = 0; i < num_sp; i++) {
1679 dma_addr_t dma;
1680 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1681 flags);
1682 if (!buf)
1683 goto fail_sp5;
1684
1685 xhci->scratchpad->sp_array[i] = dma;
1686 xhci->scratchpad->sp_buffers[i] = buf;
1687 xhci->scratchpad->sp_dma_buffers[i] = dma;
1688 }
1689
1690 return 0;
1691
1692 fail_sp5:
1693 for (i = i - 1; i >= 0; i--) {
1694 dma_free_coherent(dev, xhci->page_size,
1695 xhci->scratchpad->sp_buffers[i],
1696 xhci->scratchpad->sp_dma_buffers[i]);
1697 }
1698 kfree(xhci->scratchpad->sp_dma_buffers);
1699
1700 fail_sp4:
1701 kfree(xhci->scratchpad->sp_buffers);
1702
1703 fail_sp3:
1704 dma_free_coherent(dev, num_sp * sizeof(u64),
1705 xhci->scratchpad->sp_array,
1706 xhci->scratchpad->sp_dma);
1707
1708 fail_sp2:
1709 kfree(xhci->scratchpad);
1710 xhci->scratchpad = NULL;
1711
1712 fail_sp:
1713 return -ENOMEM;
1714}
1715
1716static void scratchpad_free(struct xhci_hcd *xhci)
1717{
1718 int num_sp;
1719 int i;
1720 struct device *dev = xhci_to_hcd(xhci)->self.controller;
1721
1722 if (!xhci->scratchpad)
1723 return;
1724
1725 num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1726
1727 for (i = 0; i < num_sp; i++) {
1728 dma_free_coherent(dev, xhci->page_size,
1729 xhci->scratchpad->sp_buffers[i],
1730 xhci->scratchpad->sp_dma_buffers[i]);
1731 }
1732 kfree(xhci->scratchpad->sp_dma_buffers);
1733 kfree(xhci->scratchpad->sp_buffers);
1734 dma_free_coherent(dev, num_sp * sizeof(u64),
1735 xhci->scratchpad->sp_array,
1736 xhci->scratchpad->sp_dma);
1737 kfree(xhci->scratchpad);
1738 xhci->scratchpad = NULL;
1739}
1740
1741struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1742 bool allocate_in_ctx, bool allocate_completion,
1743 gfp_t mem_flags)
1744{
1745 struct xhci_command *command;
1746
1747 command = kzalloc(sizeof(*command), mem_flags);
1748 if (!command)
1749 return NULL;
1750
1751 if (allocate_in_ctx) {
1752 command->in_ctx =
1753 xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1754 mem_flags);
1755 if (!command->in_ctx) {
1756 kfree(command);
1757 return NULL;
1758 }
1759 }
1760
1761 if (allocate_completion) {
1762 command->completion =
1763 kzalloc(sizeof(struct completion), mem_flags);
1764 if (!command->completion) {
1765 xhci_free_container_ctx(xhci, command->in_ctx);
1766 kfree(command);
1767 return NULL;
1768 }
1769 init_completion(command->completion);
1770 }
1771
1772 command->status = 0;
1773 INIT_LIST_HEAD(&command->cmd_list);
1774 return command;
1775}
1776
1777void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1778{
1779 if (urb_priv) {
1780 kfree(urb_priv->td[0]);
1781 kfree(urb_priv);
1782 }
1783}
1784
1785void xhci_free_command(struct xhci_hcd *xhci,
1786 struct xhci_command *command)
1787{
1788 xhci_free_container_ctx(xhci,
1789 command->in_ctx);
1790 kfree(command->completion);
1791 kfree(command);
1792}
1793
1794void xhci_mem_cleanup(struct xhci_hcd *xhci)
1795{
1796 struct device *dev = xhci_to_hcd(xhci)->self.controller;
1797 struct xhci_cd *cur_cd, *next_cd;
1798 int size;
1799 int i, j, num_ports;
1800
1801 /* Free the Event Ring Segment Table and the actual Event Ring */
1802 size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1803 if (xhci->erst.entries)
1804 dma_free_coherent(dev, size,
1805 xhci->erst.entries, xhci->erst.erst_dma_addr);
1806 xhci->erst.entries = NULL;
1807 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed ERST");
1808 if (xhci->event_ring)
1809 xhci_ring_free(xhci, xhci->event_ring);
1810 xhci->event_ring = NULL;
1811 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring");
1812
1813 if (xhci->lpm_command)
1814 xhci_free_command(xhci, xhci->lpm_command);
1815 if (xhci->cmd_ring)
1816 xhci_ring_free(xhci, xhci->cmd_ring);
1817 xhci->cmd_ring = NULL;
1818 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring");
1819 list_for_each_entry_safe(cur_cd, next_cd,
1820 &xhci->cancel_cmd_list, cancel_cmd_list) {
1821 list_del(&cur_cd->cancel_cmd_list);
1822 kfree(cur_cd);
1823 }
1824
1825 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1826 for (i = 0; i < num_ports; i++) {
1827 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1828 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1829 struct list_head *ep = &bwt->interval_bw[j].endpoints;
1830 while (!list_empty(ep))
1831 list_del_init(ep->next);
1832 }
1833 }
1834
1835 for (i = 1; i < MAX_HC_SLOTS; ++i)
1836 xhci_free_virt_device(xhci, i);
1837
1838 if (xhci->segment_pool)
1839 dma_pool_destroy(xhci->segment_pool);
1840 xhci->segment_pool = NULL;
1841 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool");
1842
1843 if (xhci->device_pool)
1844 dma_pool_destroy(xhci->device_pool);
1845 xhci->device_pool = NULL;
1846 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool");
1847
1848 if (xhci->small_streams_pool)
1849 dma_pool_destroy(xhci->small_streams_pool);
1850 xhci->small_streams_pool = NULL;
1851 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1852 "Freed small stream array pool");
1853
1854 if (xhci->medium_streams_pool)
1855 dma_pool_destroy(xhci->medium_streams_pool);
1856 xhci->medium_streams_pool = NULL;
1857 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1858 "Freed medium stream array pool");
1859
1860 if (xhci->dcbaa)
1861 dma_free_coherent(dev, sizeof(*xhci->dcbaa),
1862 xhci->dcbaa, xhci->dcbaa->dma);
1863 xhci->dcbaa = NULL;
1864
1865 scratchpad_free(xhci);
1866
1867 if (!xhci->rh_bw)
1868 goto no_bw;
1869
1870 for (i = 0; i < num_ports; i++) {
1871 struct xhci_tt_bw_info *tt, *n;
1872 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1873 list_del(&tt->tt_list);
1874 kfree(tt);
1875 }
1876 }
1877
1878no_bw:
1879 xhci->cmd_ring_reserved_trbs = 0;
1880 xhci->num_usb2_ports = 0;
1881 xhci->num_usb3_ports = 0;
1882 xhci->num_active_eps = 0;
1883 kfree(xhci->usb2_ports);
1884 kfree(xhci->usb3_ports);
1885 kfree(xhci->port_array);
1886 kfree(xhci->rh_bw);
1887 kfree(xhci->ext_caps);
1888
1889 xhci->page_size = 0;
1890 xhci->page_shift = 0;
1891 xhci->bus_state[0].bus_suspended = 0;
1892 xhci->bus_state[1].bus_suspended = 0;
1893}
1894
1895static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1896 struct xhci_segment *input_seg,
1897 union xhci_trb *start_trb,
1898 union xhci_trb *end_trb,
1899 dma_addr_t input_dma,
1900 struct xhci_segment *result_seg,
1901 char *test_name, int test_number)
1902{
1903 unsigned long long start_dma;
1904 unsigned long long end_dma;
1905 struct xhci_segment *seg;
1906
1907 start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1908 end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1909
1910 seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1911 if (seg != result_seg) {
1912 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1913 test_name, test_number);
1914 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1915 "input DMA 0x%llx\n",
1916 input_seg,
1917 (unsigned long long) input_dma);
1918 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1919 "ending TRB %p (0x%llx DMA)\n",
1920 start_trb, start_dma,
1921 end_trb, end_dma);
1922 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1923 result_seg, seg);
1924 return -1;
1925 }
1926 return 0;
1927}
1928
1929/* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1930static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1931{
1932 struct {
1933 dma_addr_t input_dma;
1934 struct xhci_segment *result_seg;
1935 } simple_test_vector [] = {
1936 /* A zeroed DMA field should fail */
1937 { 0, NULL },
1938 /* One TRB before the ring start should fail */
1939 { xhci->event_ring->first_seg->dma - 16, NULL },
1940 /* One byte before the ring start should fail */
1941 { xhci->event_ring->first_seg->dma - 1, NULL },
1942 /* Starting TRB should succeed */
1943 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1944 /* Ending TRB should succeed */
1945 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1946 xhci->event_ring->first_seg },
1947 /* One byte after the ring end should fail */
1948 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1949 /* One TRB after the ring end should fail */
1950 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1951 /* An address of all ones should fail */
1952 { (dma_addr_t) (~0), NULL },
1953 };
1954 struct {
1955 struct xhci_segment *input_seg;
1956 union xhci_trb *start_trb;
1957 union xhci_trb *end_trb;
1958 dma_addr_t input_dma;
1959 struct xhci_segment *result_seg;
1960 } complex_test_vector [] = {
1961 /* Test feeding a valid DMA address from a different ring */
1962 { .input_seg = xhci->event_ring->first_seg,
1963 .start_trb = xhci->event_ring->first_seg->trbs,
1964 .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1965 .input_dma = xhci->cmd_ring->first_seg->dma,
1966 .result_seg = NULL,
1967 },
1968 /* Test feeding a valid end TRB from a different ring */
1969 { .input_seg = xhci->event_ring->first_seg,
1970 .start_trb = xhci->event_ring->first_seg->trbs,
1971 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1972 .input_dma = xhci->cmd_ring->first_seg->dma,
1973 .result_seg = NULL,
1974 },
1975 /* Test feeding a valid start and end TRB from a different ring */
1976 { .input_seg = xhci->event_ring->first_seg,
1977 .start_trb = xhci->cmd_ring->first_seg->trbs,
1978 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1979 .input_dma = xhci->cmd_ring->first_seg->dma,
1980 .result_seg = NULL,
1981 },
1982 /* TRB in this ring, but after this TD */
1983 { .input_seg = xhci->event_ring->first_seg,
1984 .start_trb = &xhci->event_ring->first_seg->trbs[0],
1985 .end_trb = &xhci->event_ring->first_seg->trbs[3],
1986 .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1987 .result_seg = NULL,
1988 },
1989 /* TRB in this ring, but before this TD */
1990 { .input_seg = xhci->event_ring->first_seg,
1991 .start_trb = &xhci->event_ring->first_seg->trbs[3],
1992 .end_trb = &xhci->event_ring->first_seg->trbs[6],
1993 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1994 .result_seg = NULL,
1995 },
1996 /* TRB in this ring, but after this wrapped TD */
1997 { .input_seg = xhci->event_ring->first_seg,
1998 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1999 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2000 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
2001 .result_seg = NULL,
2002 },
2003 /* TRB in this ring, but before this wrapped TD */
2004 { .input_seg = xhci->event_ring->first_seg,
2005 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2006 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2007 .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
2008 .result_seg = NULL,
2009 },
2010 /* TRB not in this ring, and we have a wrapped TD */
2011 { .input_seg = xhci->event_ring->first_seg,
2012 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2013 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2014 .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
2015 .result_seg = NULL,
2016 },
2017 };
2018
2019 unsigned int num_tests;
2020 int i, ret;
2021
2022 num_tests = ARRAY_SIZE(simple_test_vector);
2023 for (i = 0; i < num_tests; i++) {
2024 ret = xhci_test_trb_in_td(xhci,
2025 xhci->event_ring->first_seg,
2026 xhci->event_ring->first_seg->trbs,
2027 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2028 simple_test_vector[i].input_dma,
2029 simple_test_vector[i].result_seg,
2030 "Simple", i);
2031 if (ret < 0)
2032 return ret;
2033 }
2034
2035 num_tests = ARRAY_SIZE(complex_test_vector);
2036 for (i = 0; i < num_tests; i++) {
2037 ret = xhci_test_trb_in_td(xhci,
2038 complex_test_vector[i].input_seg,
2039 complex_test_vector[i].start_trb,
2040 complex_test_vector[i].end_trb,
2041 complex_test_vector[i].input_dma,
2042 complex_test_vector[i].result_seg,
2043 "Complex", i);
2044 if (ret < 0)
2045 return ret;
2046 }
2047 xhci_dbg(xhci, "TRB math tests passed.\n");
2048 return 0;
2049}
2050
2051static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
2052{
2053 u64 temp;
2054 dma_addr_t deq;
2055
2056 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2057 xhci->event_ring->dequeue);
2058 if (deq == 0 && !in_interrupt())
2059 xhci_warn(xhci, "WARN something wrong with SW event ring "
2060 "dequeue ptr.\n");
2061 /* Update HC event ring dequeue pointer */
2062 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2063 temp &= ERST_PTR_MASK;
2064 /* Don't clear the EHB bit (which is RW1C) because
2065 * there might be more events to service.
2066 */
2067 temp &= ~ERST_EHB;
2068 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2069 "// Write event ring dequeue pointer, "
2070 "preserving EHB bit");
2071 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2072 &xhci->ir_set->erst_dequeue);
2073}
2074
2075static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2076 __le32 __iomem *addr, u8 major_revision, int max_caps)
2077{
2078 u32 temp, port_offset, port_count;
2079 int i;
2080
2081 if (major_revision > 0x03) {
2082 xhci_warn(xhci, "Ignoring unknown port speed, "
2083 "Ext Cap %p, revision = 0x%x\n",
2084 addr, major_revision);
2085 /* Ignoring port protocol we can't understand. FIXME */
2086 return;
2087 }
2088
2089 /* Port offset and count in the third dword, see section 7.2 */
2090 temp = readl(addr + 2);
2091 port_offset = XHCI_EXT_PORT_OFF(temp);
2092 port_count = XHCI_EXT_PORT_COUNT(temp);
2093 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2094 "Ext Cap %p, port offset = %u, "
2095 "count = %u, revision = 0x%x",
2096 addr, port_offset, port_count, major_revision);
2097 /* Port count includes the current port offset */
2098 if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2099 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2100 return;
2101
2102 /* cache usb2 port capabilities */
2103 if (major_revision < 0x03 && xhci->num_ext_caps < max_caps)
2104 xhci->ext_caps[xhci->num_ext_caps++] = temp;
2105
2106 /* Check the host's USB2 LPM capability */
2107 if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
2108 (temp & XHCI_L1C)) {
2109 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2110 "xHCI 0.96: support USB2 software lpm");
2111 xhci->sw_lpm_support = 1;
2112 }
2113
2114 if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2115 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2116 "xHCI 1.0: support USB2 software lpm");
2117 xhci->sw_lpm_support = 1;
2118 if (temp & XHCI_HLC) {
2119 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2120 "xHCI 1.0: support USB2 hardware lpm");
2121 xhci->hw_lpm_support = 1;
2122 }
2123 }
2124
2125 port_offset--;
2126 for (i = port_offset; i < (port_offset + port_count); i++) {
2127 /* Duplicate entry. Ignore the port if the revisions differ. */
2128 if (xhci->port_array[i] != 0) {
2129 xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2130 " port %u\n", addr, i);
2131 xhci_warn(xhci, "Port was marked as USB %u, "
2132 "duplicated as USB %u\n",
2133 xhci->port_array[i], major_revision);
2134 /* Only adjust the roothub port counts if we haven't
2135 * found a similar duplicate.
2136 */
2137 if (xhci->port_array[i] != major_revision &&
2138 xhci->port_array[i] != DUPLICATE_ENTRY) {
2139 if (xhci->port_array[i] == 0x03)
2140 xhci->num_usb3_ports--;
2141 else
2142 xhci->num_usb2_ports--;
2143 xhci->port_array[i] = DUPLICATE_ENTRY;
2144 }
2145 /* FIXME: Should we disable the port? */
2146 continue;
2147 }
2148 xhci->port_array[i] = major_revision;
2149 if (major_revision == 0x03)
2150 xhci->num_usb3_ports++;
2151 else
2152 xhci->num_usb2_ports++;
2153 }
2154 /* FIXME: Should we disable ports not in the Extended Capabilities? */
2155}
2156
2157/*
2158 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2159 * specify what speeds each port is supposed to be. We can't count on the port
2160 * speed bits in the PORTSC register being correct until a device is connected,
2161 * but we need to set up the two fake roothubs with the correct number of USB
2162 * 3.0 and USB 2.0 ports at host controller initialization time.
2163 */
2164static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2165{
2166 __le32 __iomem *addr, *tmp_addr;
2167 u32 offset, tmp_offset;
2168 unsigned int num_ports;
2169 int i, j, port_index;
2170 int cap_count = 0;
2171
2172 addr = &xhci->cap_regs->hcc_params;
2173 offset = XHCI_HCC_EXT_CAPS(readl(addr));
2174 if (offset == 0) {
2175 xhci_err(xhci, "No Extended Capability registers, "
2176 "unable to set up roothub.\n");
2177 return -ENODEV;
2178 }
2179
2180 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2181 xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2182 if (!xhci->port_array)
2183 return -ENOMEM;
2184
2185 xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2186 if (!xhci->rh_bw)
2187 return -ENOMEM;
2188 for (i = 0; i < num_ports; i++) {
2189 struct xhci_interval_bw_table *bw_table;
2190
2191 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2192 bw_table = &xhci->rh_bw[i].bw_table;
2193 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2194 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2195 }
2196
2197 /*
2198 * For whatever reason, the first capability offset is from the
2199 * capability register base, not from the HCCPARAMS register.
2200 * See section 5.3.6 for offset calculation.
2201 */
2202 addr = &xhci->cap_regs->hc_capbase + offset;
2203
2204 tmp_addr = addr;
2205 tmp_offset = offset;
2206
2207 /* count extended protocol capability entries for later caching */
2208 do {
2209 u32 cap_id;
2210 cap_id = readl(tmp_addr);
2211 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2212 cap_count++;
2213 tmp_offset = XHCI_EXT_CAPS_NEXT(cap_id);
2214 tmp_addr += tmp_offset;
2215 } while (tmp_offset);
2216
2217 xhci->ext_caps = kzalloc(sizeof(*xhci->ext_caps) * cap_count, flags);
2218 if (!xhci->ext_caps)
2219 return -ENOMEM;
2220
2221 while (1) {
2222 u32 cap_id;
2223
2224 cap_id = readl(addr);
2225 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2226 xhci_add_in_port(xhci, num_ports, addr,
2227 (u8) XHCI_EXT_PORT_MAJOR(cap_id),
2228 cap_count);
2229 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2230 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2231 == num_ports)
2232 break;
2233 /*
2234 * Once you're into the Extended Capabilities, the offset is
2235 * always relative to the register holding the offset.
2236 */
2237 addr += offset;
2238 }
2239
2240 if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2241 xhci_warn(xhci, "No ports on the roothubs?\n");
2242 return -ENODEV;
2243 }
2244 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2245 "Found %u USB 2.0 ports and %u USB 3.0 ports.",
2246 xhci->num_usb2_ports, xhci->num_usb3_ports);
2247
2248 /* Place limits on the number of roothub ports so that the hub
2249 * descriptors aren't longer than the USB core will allocate.
2250 */
2251 if (xhci->num_usb3_ports > 15) {
2252 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2253 "Limiting USB 3.0 roothub ports to 15.");
2254 xhci->num_usb3_ports = 15;
2255 }
2256 if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2257 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2258 "Limiting USB 2.0 roothub ports to %u.",
2259 USB_MAXCHILDREN);
2260 xhci->num_usb2_ports = USB_MAXCHILDREN;
2261 }
2262
2263 /*
2264 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2265 * Not sure how the USB core will handle a hub with no ports...
2266 */
2267 if (xhci->num_usb2_ports) {
2268 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2269 xhci->num_usb2_ports, flags);
2270 if (!xhci->usb2_ports)
2271 return -ENOMEM;
2272
2273 port_index = 0;
2274 for (i = 0; i < num_ports; i++) {
2275 if (xhci->port_array[i] == 0x03 ||
2276 xhci->port_array[i] == 0 ||
2277 xhci->port_array[i] == DUPLICATE_ENTRY)
2278 continue;
2279
2280 xhci->usb2_ports[port_index] =
2281 &xhci->op_regs->port_status_base +
2282 NUM_PORT_REGS*i;
2283 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2284 "USB 2.0 port at index %u, "
2285 "addr = %p", i,
2286 xhci->usb2_ports[port_index]);
2287 port_index++;
2288 if (port_index == xhci->num_usb2_ports)
2289 break;
2290 }
2291 }
2292 if (xhci->num_usb3_ports) {
2293 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2294 xhci->num_usb3_ports, flags);
2295 if (!xhci->usb3_ports)
2296 return -ENOMEM;
2297
2298 port_index = 0;
2299 for (i = 0; i < num_ports; i++)
2300 if (xhci->port_array[i] == 0x03) {
2301 xhci->usb3_ports[port_index] =
2302 &xhci->op_regs->port_status_base +
2303 NUM_PORT_REGS*i;
2304 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2305 "USB 3.0 port at index %u, "
2306 "addr = %p", i,
2307 xhci->usb3_ports[port_index]);
2308 port_index++;
2309 if (port_index == xhci->num_usb3_ports)
2310 break;
2311 }
2312 }
2313 return 0;
2314}
2315
2316int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2317{
2318 dma_addr_t dma;
2319 struct device *dev = xhci_to_hcd(xhci)->self.controller;
2320 unsigned int val, val2;
2321 u64 val_64;
2322 struct xhci_segment *seg;
2323 u32 page_size, temp;
2324 int i;
2325
2326 INIT_LIST_HEAD(&xhci->cancel_cmd_list);
2327
2328 page_size = readl(&xhci->op_regs->page_size);
2329 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2330 "Supported page size register = 0x%x", page_size);
2331 for (i = 0; i < 16; i++) {
2332 if ((0x1 & page_size) != 0)
2333 break;
2334 page_size = page_size >> 1;
2335 }
2336 if (i < 16)
2337 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2338 "Supported page size of %iK", (1 << (i+12)) / 1024);
2339 else
2340 xhci_warn(xhci, "WARN: no supported page size\n");
2341 /* Use 4K pages, since that's common and the minimum the HC supports */
2342 xhci->page_shift = 12;
2343 xhci->page_size = 1 << xhci->page_shift;
2344 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2345 "HCD page size set to %iK", xhci->page_size / 1024);
2346
2347 /*
2348 * Program the Number of Device Slots Enabled field in the CONFIG
2349 * register with the max value of slots the HC can handle.
2350 */
2351 val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1));
2352 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2353 "// xHC can handle at most %d device slots.", val);
2354 val2 = readl(&xhci->op_regs->config_reg);
2355 val |= (val2 & ~HCS_SLOTS_MASK);
2356 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2357 "// Setting Max device slots reg = 0x%x.", val);
2358 writel(val, &xhci->op_regs->config_reg);
2359
2360 /*
2361 * Section 5.4.8 - doorbell array must be
2362 * "physically contiguous and 64-byte (cache line) aligned".
2363 */
2364 xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2365 GFP_KERNEL);
2366 if (!xhci->dcbaa)
2367 goto fail;
2368 memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2369 xhci->dcbaa->dma = dma;
2370 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2371 "// Device context base array address = 0x%llx (DMA), %p (virt)",
2372 (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2373 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2374
2375 /*
2376 * Initialize the ring segment pool. The ring must be a contiguous
2377 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
2378 * however, the command ring segment needs 64-byte aligned segments
2379 * and our use of dma addresses in the trb_address_map radix tree needs
2380 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
2381 */
2382 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2383 TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
2384
2385 /* See Table 46 and Note on Figure 55 */
2386 xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2387 2112, 64, xhci->page_size);
2388 if (!xhci->segment_pool || !xhci->device_pool)
2389 goto fail;
2390
2391 /* Linear stream context arrays don't have any boundary restrictions,
2392 * and only need to be 16-byte aligned.
2393 */
2394 xhci->small_streams_pool =
2395 dma_pool_create("xHCI 256 byte stream ctx arrays",
2396 dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2397 xhci->medium_streams_pool =
2398 dma_pool_create("xHCI 1KB stream ctx arrays",
2399 dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2400 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2401 * will be allocated with dma_alloc_coherent()
2402 */
2403
2404 if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2405 goto fail;
2406
2407 /* Set up the command ring to have one segments for now. */
2408 xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags);
2409 if (!xhci->cmd_ring)
2410 goto fail;
2411 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2412 "Allocated command ring at %p", xhci->cmd_ring);
2413 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%llx",
2414 (unsigned long long)xhci->cmd_ring->first_seg->dma);
2415
2416 /* Set the address in the Command Ring Control register */
2417 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2418 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2419 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2420 xhci->cmd_ring->cycle_state;
2421 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2422 "// Setting command ring address to 0x%x", val);
2423 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2424 xhci_dbg_cmd_ptrs(xhci);
2425
2426 xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
2427 if (!xhci->lpm_command)
2428 goto fail;
2429
2430 /* Reserve one command ring TRB for disabling LPM.
2431 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2432 * disabling LPM, we only need to reserve one TRB for all devices.
2433 */
2434 xhci->cmd_ring_reserved_trbs++;
2435
2436 val = readl(&xhci->cap_regs->db_off);
2437 val &= DBOFF_MASK;
2438 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2439 "// Doorbell array is located at offset 0x%x"
2440 " from cap regs base addr", val);
2441 xhci->dba = (void __iomem *) xhci->cap_regs + val;
2442 xhci_dbg_regs(xhci);
2443 xhci_print_run_regs(xhci);
2444 /* Set ir_set to interrupt register set 0 */
2445 xhci->ir_set = &xhci->run_regs->ir_set[0];
2446
2447 /*
2448 * Event ring setup: Allocate a normal ring, but also setup
2449 * the event ring segment table (ERST). Section 4.9.3.
2450 */
2451 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Allocating event ring");
2452 xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2453 flags);
2454 if (!xhci->event_ring)
2455 goto fail;
2456 if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2457 goto fail;
2458
2459 xhci->erst.entries = dma_alloc_coherent(dev,
2460 sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2461 GFP_KERNEL);
2462 if (!xhci->erst.entries)
2463 goto fail;
2464 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2465 "// Allocated event ring segment table at 0x%llx",
2466 (unsigned long long)dma);
2467
2468 memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2469 xhci->erst.num_entries = ERST_NUM_SEGS;
2470 xhci->erst.erst_dma_addr = dma;
2471 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2472 "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx",
2473 xhci->erst.num_entries,
2474 xhci->erst.entries,
2475 (unsigned long long)xhci->erst.erst_dma_addr);
2476
2477 /* set ring base address and size for each segment table entry */
2478 for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2479 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2480 entry->seg_addr = cpu_to_le64(seg->dma);
2481 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2482 entry->rsvd = 0;
2483 seg = seg->next;
2484 }
2485
2486 /* set ERST count with the number of entries in the segment table */
2487 val = readl(&xhci->ir_set->erst_size);
2488 val &= ERST_SIZE_MASK;
2489 val |= ERST_NUM_SEGS;
2490 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2491 "// Write ERST size = %i to ir_set 0 (some bits preserved)",
2492 val);
2493 writel(val, &xhci->ir_set->erst_size);
2494
2495 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2496 "// Set ERST entries to point to event ring.");
2497 /* set the segment table base address */
2498 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2499 "// Set ERST base address for ir_set 0 = 0x%llx",
2500 (unsigned long long)xhci->erst.erst_dma_addr);
2501 val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2502 val_64 &= ERST_PTR_MASK;
2503 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2504 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2505
2506 /* Set the event ring dequeue address */
2507 xhci_set_hc_event_deq(xhci);
2508 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2509 "Wrote ERST address to ir_set 0.");
2510 xhci_print_ir_set(xhci, 0);
2511
2512 /*
2513 * XXX: Might need to set the Interrupter Moderation Register to
2514 * something other than the default (~1ms minimum between interrupts).
2515 * See section 5.5.1.2.
2516 */
2517 init_completion(&xhci->addr_dev);
2518 for (i = 0; i < MAX_HC_SLOTS; ++i)
2519 xhci->devs[i] = NULL;
2520 for (i = 0; i < USB_MAXCHILDREN; ++i) {
2521 xhci->bus_state[0].resume_done[i] = 0;
2522 xhci->bus_state[1].resume_done[i] = 0;
2523 /* Only the USB 2.0 completions will ever be used. */
2524 init_completion(&xhci->bus_state[1].rexit_done[i]);
2525 }
2526
2527 if (scratchpad_alloc(xhci, flags))
2528 goto fail;
2529 if (xhci_setup_port_arrays(xhci, flags))
2530 goto fail;
2531
2532 /* Enable USB 3.0 device notifications for function remote wake, which
2533 * is necessary for allowing USB 3.0 devices to do remote wakeup from
2534 * U3 (device suspend).
2535 */
2536 temp = readl(&xhci->op_regs->dev_notification);
2537 temp &= ~DEV_NOTE_MASK;
2538 temp |= DEV_NOTE_FWAKE;
2539 writel(temp, &xhci->op_regs->dev_notification);
2540
2541 return 0;
2542
2543fail:
2544 xhci_warn(xhci, "Couldn't initialize memory\n");
2545 xhci_halt(xhci);
2546 xhci_reset(xhci);
2547 xhci_mem_cleanup(xhci);
2548 return -ENOMEM;
2549}
1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/usb.h>
24#include <linux/pci.h>
25#include <linux/slab.h>
26#include <linux/dmapool.h>
27
28#include "xhci.h"
29
30/*
31 * Allocates a generic ring segment from the ring pool, sets the dma address,
32 * initializes the segment to zero, and sets the private next pointer to NULL.
33 *
34 * Section 4.11.1.1:
35 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
36 */
37static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
38 unsigned int cycle_state, gfp_t flags)
39{
40 struct xhci_segment *seg;
41 dma_addr_t dma;
42 int i;
43
44 seg = kzalloc(sizeof *seg, flags);
45 if (!seg)
46 return NULL;
47
48 seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
49 if (!seg->trbs) {
50 kfree(seg);
51 return NULL;
52 }
53
54 memset(seg->trbs, 0, SEGMENT_SIZE);
55 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
56 if (cycle_state == 0) {
57 for (i = 0; i < TRBS_PER_SEGMENT; i++)
58 seg->trbs[i].link.control |= TRB_CYCLE;
59 }
60 seg->dma = dma;
61 seg->next = NULL;
62
63 return seg;
64}
65
66static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
67{
68 if (seg->trbs) {
69 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
70 seg->trbs = NULL;
71 }
72 kfree(seg);
73}
74
75static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
76 struct xhci_segment *first)
77{
78 struct xhci_segment *seg;
79
80 seg = first->next;
81 while (seg != first) {
82 struct xhci_segment *next = seg->next;
83 xhci_segment_free(xhci, seg);
84 seg = next;
85 }
86 xhci_segment_free(xhci, first);
87}
88
89/*
90 * Make the prev segment point to the next segment.
91 *
92 * Change the last TRB in the prev segment to be a Link TRB which points to the
93 * DMA address of the next segment. The caller needs to set any Link TRB
94 * related flags, such as End TRB, Toggle Cycle, and no snoop.
95 */
96static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
97 struct xhci_segment *next, enum xhci_ring_type type)
98{
99 u32 val;
100
101 if (!prev || !next)
102 return;
103 prev->next = next;
104 if (type != TYPE_EVENT) {
105 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
106 cpu_to_le64(next->dma);
107
108 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
109 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
110 val &= ~TRB_TYPE_BITMASK;
111 val |= TRB_TYPE(TRB_LINK);
112 /* Always set the chain bit with 0.95 hardware */
113 /* Set chain bit for isoc rings on AMD 0.96 host */
114 if (xhci_link_trb_quirk(xhci) ||
115 (type == TYPE_ISOC &&
116 (xhci->quirks & XHCI_AMD_0x96_HOST)))
117 val |= TRB_CHAIN;
118 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
119 }
120}
121
122/*
123 * Link the ring to the new segments.
124 * Set Toggle Cycle for the new ring if needed.
125 */
126static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
127 struct xhci_segment *first, struct xhci_segment *last,
128 unsigned int num_segs)
129{
130 struct xhci_segment *next;
131
132 if (!ring || !first || !last)
133 return;
134
135 next = ring->enq_seg->next;
136 xhci_link_segments(xhci, ring->enq_seg, first, ring->type);
137 xhci_link_segments(xhci, last, next, ring->type);
138 ring->num_segs += num_segs;
139 ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
140
141 if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
142 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
143 &= ~cpu_to_le32(LINK_TOGGLE);
144 last->trbs[TRBS_PER_SEGMENT-1].link.control
145 |= cpu_to_le32(LINK_TOGGLE);
146 ring->last_seg = last;
147 }
148}
149
150/* XXX: Do we need the hcd structure in all these functions? */
151void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
152{
153 if (!ring)
154 return;
155
156 if (ring->first_seg)
157 xhci_free_segments_for_ring(xhci, ring->first_seg);
158
159 kfree(ring);
160}
161
162static void xhci_initialize_ring_info(struct xhci_ring *ring,
163 unsigned int cycle_state)
164{
165 /* The ring is empty, so the enqueue pointer == dequeue pointer */
166 ring->enqueue = ring->first_seg->trbs;
167 ring->enq_seg = ring->first_seg;
168 ring->dequeue = ring->enqueue;
169 ring->deq_seg = ring->first_seg;
170 /* The ring is initialized to 0. The producer must write 1 to the cycle
171 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
172 * compare CCS to the cycle bit to check ownership, so CCS = 1.
173 *
174 * New rings are initialized with cycle state equal to 1; if we are
175 * handling ring expansion, set the cycle state equal to the old ring.
176 */
177 ring->cycle_state = cycle_state;
178 /* Not necessary for new rings, but needed for re-initialized rings */
179 ring->enq_updates = 0;
180 ring->deq_updates = 0;
181
182 /*
183 * Each segment has a link TRB, and leave an extra TRB for SW
184 * accounting purpose
185 */
186 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
187}
188
189/* Allocate segments and link them for a ring */
190static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
191 struct xhci_segment **first, struct xhci_segment **last,
192 unsigned int num_segs, unsigned int cycle_state,
193 enum xhci_ring_type type, gfp_t flags)
194{
195 struct xhci_segment *prev;
196
197 prev = xhci_segment_alloc(xhci, cycle_state, flags);
198 if (!prev)
199 return -ENOMEM;
200 num_segs--;
201
202 *first = prev;
203 while (num_segs > 0) {
204 struct xhci_segment *next;
205
206 next = xhci_segment_alloc(xhci, cycle_state, flags);
207 if (!next) {
208 xhci_free_segments_for_ring(xhci, *first);
209 return -ENOMEM;
210 }
211 xhci_link_segments(xhci, prev, next, type);
212
213 prev = next;
214 num_segs--;
215 }
216 xhci_link_segments(xhci, prev, *first, type);
217 *last = prev;
218
219 return 0;
220}
221
222/**
223 * Create a new ring with zero or more segments.
224 *
225 * Link each segment together into a ring.
226 * Set the end flag and the cycle toggle bit on the last segment.
227 * See section 4.9.1 and figures 15 and 16.
228 */
229static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
230 unsigned int num_segs, unsigned int cycle_state,
231 enum xhci_ring_type type, gfp_t flags)
232{
233 struct xhci_ring *ring;
234 int ret;
235
236 ring = kzalloc(sizeof *(ring), flags);
237 if (!ring)
238 return NULL;
239
240 ring->num_segs = num_segs;
241 INIT_LIST_HEAD(&ring->td_list);
242 ring->type = type;
243 if (num_segs == 0)
244 return ring;
245
246 ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
247 &ring->last_seg, num_segs, cycle_state, type, flags);
248 if (ret)
249 goto fail;
250
251 /* Only event ring does not use link TRB */
252 if (type != TYPE_EVENT) {
253 /* See section 4.9.2.1 and 6.4.4.1 */
254 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
255 cpu_to_le32(LINK_TOGGLE);
256 }
257 xhci_initialize_ring_info(ring, cycle_state);
258 return ring;
259
260fail:
261 xhci_ring_free(xhci, ring);
262 return NULL;
263}
264
265void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
266 struct xhci_virt_device *virt_dev,
267 unsigned int ep_index)
268{
269 int rings_cached;
270
271 rings_cached = virt_dev->num_rings_cached;
272 if (rings_cached < XHCI_MAX_RINGS_CACHED) {
273 virt_dev->ring_cache[rings_cached] =
274 virt_dev->eps[ep_index].ring;
275 virt_dev->num_rings_cached++;
276 xhci_dbg(xhci, "Cached old ring, "
277 "%d ring%s cached\n",
278 virt_dev->num_rings_cached,
279 (virt_dev->num_rings_cached > 1) ? "s" : "");
280 } else {
281 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
282 xhci_dbg(xhci, "Ring cache full (%d rings), "
283 "freeing ring\n",
284 virt_dev->num_rings_cached);
285 }
286 virt_dev->eps[ep_index].ring = NULL;
287}
288
289/* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
290 * pointers to the beginning of the ring.
291 */
292static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
293 struct xhci_ring *ring, unsigned int cycle_state,
294 enum xhci_ring_type type)
295{
296 struct xhci_segment *seg = ring->first_seg;
297 int i;
298
299 do {
300 memset(seg->trbs, 0,
301 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
302 if (cycle_state == 0) {
303 for (i = 0; i < TRBS_PER_SEGMENT; i++)
304 seg->trbs[i].link.control |= TRB_CYCLE;
305 }
306 /* All endpoint rings have link TRBs */
307 xhci_link_segments(xhci, seg, seg->next, type);
308 seg = seg->next;
309 } while (seg != ring->first_seg);
310 ring->type = type;
311 xhci_initialize_ring_info(ring, cycle_state);
312 /* td list should be empty since all URBs have been cancelled,
313 * but just in case...
314 */
315 INIT_LIST_HEAD(&ring->td_list);
316}
317
318/*
319 * Expand an existing ring.
320 * Look for a cached ring or allocate a new ring which has same segment numbers
321 * and link the two rings.
322 */
323int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
324 unsigned int num_trbs, gfp_t flags)
325{
326 struct xhci_segment *first;
327 struct xhci_segment *last;
328 unsigned int num_segs;
329 unsigned int num_segs_needed;
330 int ret;
331
332 num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) /
333 (TRBS_PER_SEGMENT - 1);
334
335 /* Allocate number of segments we needed, or double the ring size */
336 num_segs = ring->num_segs > num_segs_needed ?
337 ring->num_segs : num_segs_needed;
338
339 ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
340 num_segs, ring->cycle_state, ring->type, flags);
341 if (ret)
342 return -ENOMEM;
343
344 xhci_link_rings(xhci, ring, first, last, num_segs);
345 xhci_dbg(xhci, "ring expansion succeed, now has %d segments\n",
346 ring->num_segs);
347
348 return 0;
349}
350
351#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
352
353static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
354 int type, gfp_t flags)
355{
356 struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
357 if (!ctx)
358 return NULL;
359
360 BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
361 ctx->type = type;
362 ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
363 if (type == XHCI_CTX_TYPE_INPUT)
364 ctx->size += CTX_SIZE(xhci->hcc_params);
365
366 ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
367 memset(ctx->bytes, 0, ctx->size);
368 return ctx;
369}
370
371static void xhci_free_container_ctx(struct xhci_hcd *xhci,
372 struct xhci_container_ctx *ctx)
373{
374 if (!ctx)
375 return;
376 dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
377 kfree(ctx);
378}
379
380struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
381 struct xhci_container_ctx *ctx)
382{
383 BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
384 return (struct xhci_input_control_ctx *)ctx->bytes;
385}
386
387struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
388 struct xhci_container_ctx *ctx)
389{
390 if (ctx->type == XHCI_CTX_TYPE_DEVICE)
391 return (struct xhci_slot_ctx *)ctx->bytes;
392
393 return (struct xhci_slot_ctx *)
394 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
395}
396
397struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
398 struct xhci_container_ctx *ctx,
399 unsigned int ep_index)
400{
401 /* increment ep index by offset of start of ep ctx array */
402 ep_index++;
403 if (ctx->type == XHCI_CTX_TYPE_INPUT)
404 ep_index++;
405
406 return (struct xhci_ep_ctx *)
407 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
408}
409
410
411/***************** Streams structures manipulation *************************/
412
413static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
414 unsigned int num_stream_ctxs,
415 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
416{
417 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
418
419 if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
420 dma_free_coherent(&pdev->dev,
421 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
422 stream_ctx, dma);
423 else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
424 return dma_pool_free(xhci->small_streams_pool,
425 stream_ctx, dma);
426 else
427 return dma_pool_free(xhci->medium_streams_pool,
428 stream_ctx, dma);
429}
430
431/*
432 * The stream context array for each endpoint with bulk streams enabled can
433 * vary in size, based on:
434 * - how many streams the endpoint supports,
435 * - the maximum primary stream array size the host controller supports,
436 * - and how many streams the device driver asks for.
437 *
438 * The stream context array must be a power of 2, and can be as small as
439 * 64 bytes or as large as 1MB.
440 */
441static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
442 unsigned int num_stream_ctxs, dma_addr_t *dma,
443 gfp_t mem_flags)
444{
445 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
446
447 if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
448 return dma_alloc_coherent(&pdev->dev,
449 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
450 dma, mem_flags);
451 else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
452 return dma_pool_alloc(xhci->small_streams_pool,
453 mem_flags, dma);
454 else
455 return dma_pool_alloc(xhci->medium_streams_pool,
456 mem_flags, dma);
457}
458
459struct xhci_ring *xhci_dma_to_transfer_ring(
460 struct xhci_virt_ep *ep,
461 u64 address)
462{
463 if (ep->ep_state & EP_HAS_STREAMS)
464 return radix_tree_lookup(&ep->stream_info->trb_address_map,
465 address >> SEGMENT_SHIFT);
466 return ep->ring;
467}
468
469/* Only use this when you know stream_info is valid */
470#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
471static struct xhci_ring *dma_to_stream_ring(
472 struct xhci_stream_info *stream_info,
473 u64 address)
474{
475 return radix_tree_lookup(&stream_info->trb_address_map,
476 address >> SEGMENT_SHIFT);
477}
478#endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */
479
480struct xhci_ring *xhci_stream_id_to_ring(
481 struct xhci_virt_device *dev,
482 unsigned int ep_index,
483 unsigned int stream_id)
484{
485 struct xhci_virt_ep *ep = &dev->eps[ep_index];
486
487 if (stream_id == 0)
488 return ep->ring;
489 if (!ep->stream_info)
490 return NULL;
491
492 if (stream_id > ep->stream_info->num_streams)
493 return NULL;
494 return ep->stream_info->stream_rings[stream_id];
495}
496
497#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
498static int xhci_test_radix_tree(struct xhci_hcd *xhci,
499 unsigned int num_streams,
500 struct xhci_stream_info *stream_info)
501{
502 u32 cur_stream;
503 struct xhci_ring *cur_ring;
504 u64 addr;
505
506 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
507 struct xhci_ring *mapped_ring;
508 int trb_size = sizeof(union xhci_trb);
509
510 cur_ring = stream_info->stream_rings[cur_stream];
511 for (addr = cur_ring->first_seg->dma;
512 addr < cur_ring->first_seg->dma + SEGMENT_SIZE;
513 addr += trb_size) {
514 mapped_ring = dma_to_stream_ring(stream_info, addr);
515 if (cur_ring != mapped_ring) {
516 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
517 "didn't map to stream ID %u; "
518 "mapped to ring %p\n",
519 (unsigned long long) addr,
520 cur_stream,
521 mapped_ring);
522 return -EINVAL;
523 }
524 }
525 /* One TRB after the end of the ring segment shouldn't return a
526 * pointer to the current ring (although it may be a part of a
527 * different ring).
528 */
529 mapped_ring = dma_to_stream_ring(stream_info, addr);
530 if (mapped_ring != cur_ring) {
531 /* One TRB before should also fail */
532 addr = cur_ring->first_seg->dma - trb_size;
533 mapped_ring = dma_to_stream_ring(stream_info, addr);
534 }
535 if (mapped_ring == cur_ring) {
536 xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
537 "mapped to valid stream ID %u; "
538 "mapped ring = %p\n",
539 (unsigned long long) addr,
540 cur_stream,
541 mapped_ring);
542 return -EINVAL;
543 }
544 }
545 return 0;
546}
547#endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */
548
549/*
550 * Change an endpoint's internal structure so it supports stream IDs. The
551 * number of requested streams includes stream 0, which cannot be used by device
552 * drivers.
553 *
554 * The number of stream contexts in the stream context array may be bigger than
555 * the number of streams the driver wants to use. This is because the number of
556 * stream context array entries must be a power of two.
557 *
558 * We need a radix tree for mapping physical addresses of TRBs to which stream
559 * ID they belong to. We need to do this because the host controller won't tell
560 * us which stream ring the TRB came from. We could store the stream ID in an
561 * event data TRB, but that doesn't help us for the cancellation case, since the
562 * endpoint may stop before it reaches that event data TRB.
563 *
564 * The radix tree maps the upper portion of the TRB DMA address to a ring
565 * segment that has the same upper portion of DMA addresses. For example, say I
566 * have segments of size 1KB, that are always 64-byte aligned. A segment may
567 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
568 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
569 * pass the radix tree a key to get the right stream ID:
570 *
571 * 0x10c90fff >> 10 = 0x43243
572 * 0x10c912c0 >> 10 = 0x43244
573 * 0x10c91400 >> 10 = 0x43245
574 *
575 * Obviously, only those TRBs with DMA addresses that are within the segment
576 * will make the radix tree return the stream ID for that ring.
577 *
578 * Caveats for the radix tree:
579 *
580 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
581 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
582 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
583 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
584 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
585 * extended systems (where the DMA address can be bigger than 32-bits),
586 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
587 */
588struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
589 unsigned int num_stream_ctxs,
590 unsigned int num_streams, gfp_t mem_flags)
591{
592 struct xhci_stream_info *stream_info;
593 u32 cur_stream;
594 struct xhci_ring *cur_ring;
595 unsigned long key;
596 u64 addr;
597 int ret;
598
599 xhci_dbg(xhci, "Allocating %u streams and %u "
600 "stream context array entries.\n",
601 num_streams, num_stream_ctxs);
602 if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
603 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
604 return NULL;
605 }
606 xhci->cmd_ring_reserved_trbs++;
607
608 stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
609 if (!stream_info)
610 goto cleanup_trbs;
611
612 stream_info->num_streams = num_streams;
613 stream_info->num_stream_ctxs = num_stream_ctxs;
614
615 /* Initialize the array of virtual pointers to stream rings. */
616 stream_info->stream_rings = kzalloc(
617 sizeof(struct xhci_ring *)*num_streams,
618 mem_flags);
619 if (!stream_info->stream_rings)
620 goto cleanup_info;
621
622 /* Initialize the array of DMA addresses for stream rings for the HW. */
623 stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
624 num_stream_ctxs, &stream_info->ctx_array_dma,
625 mem_flags);
626 if (!stream_info->stream_ctx_array)
627 goto cleanup_ctx;
628 memset(stream_info->stream_ctx_array, 0,
629 sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
630
631 /* Allocate everything needed to free the stream rings later */
632 stream_info->free_streams_command =
633 xhci_alloc_command(xhci, true, true, mem_flags);
634 if (!stream_info->free_streams_command)
635 goto cleanup_ctx;
636
637 INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
638
639 /* Allocate rings for all the streams that the driver will use,
640 * and add their segment DMA addresses to the radix tree.
641 * Stream 0 is reserved.
642 */
643 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
644 stream_info->stream_rings[cur_stream] =
645 xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, mem_flags);
646 cur_ring = stream_info->stream_rings[cur_stream];
647 if (!cur_ring)
648 goto cleanup_rings;
649 cur_ring->stream_id = cur_stream;
650 /* Set deq ptr, cycle bit, and stream context type */
651 addr = cur_ring->first_seg->dma |
652 SCT_FOR_CTX(SCT_PRI_TR) |
653 cur_ring->cycle_state;
654 stream_info->stream_ctx_array[cur_stream].stream_ring =
655 cpu_to_le64(addr);
656 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
657 cur_stream, (unsigned long long) addr);
658
659 key = (unsigned long)
660 (cur_ring->first_seg->dma >> SEGMENT_SHIFT);
661 ret = radix_tree_insert(&stream_info->trb_address_map,
662 key, cur_ring);
663 if (ret) {
664 xhci_ring_free(xhci, cur_ring);
665 stream_info->stream_rings[cur_stream] = NULL;
666 goto cleanup_rings;
667 }
668 }
669 /* Leave the other unused stream ring pointers in the stream context
670 * array initialized to zero. This will cause the xHC to give us an
671 * error if the device asks for a stream ID we don't have setup (if it
672 * was any other way, the host controller would assume the ring is
673 * "empty" and wait forever for data to be queued to that stream ID).
674 */
675#if XHCI_DEBUG
676 /* Do a little test on the radix tree to make sure it returns the
677 * correct values.
678 */
679 if (xhci_test_radix_tree(xhci, num_streams, stream_info))
680 goto cleanup_rings;
681#endif
682
683 return stream_info;
684
685cleanup_rings:
686 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
687 cur_ring = stream_info->stream_rings[cur_stream];
688 if (cur_ring) {
689 addr = cur_ring->first_seg->dma;
690 radix_tree_delete(&stream_info->trb_address_map,
691 addr >> SEGMENT_SHIFT);
692 xhci_ring_free(xhci, cur_ring);
693 stream_info->stream_rings[cur_stream] = NULL;
694 }
695 }
696 xhci_free_command(xhci, stream_info->free_streams_command);
697cleanup_ctx:
698 kfree(stream_info->stream_rings);
699cleanup_info:
700 kfree(stream_info);
701cleanup_trbs:
702 xhci->cmd_ring_reserved_trbs--;
703 return NULL;
704}
705/*
706 * Sets the MaxPStreams field and the Linear Stream Array field.
707 * Sets the dequeue pointer to the stream context array.
708 */
709void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
710 struct xhci_ep_ctx *ep_ctx,
711 struct xhci_stream_info *stream_info)
712{
713 u32 max_primary_streams;
714 /* MaxPStreams is the number of stream context array entries, not the
715 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
716 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
717 */
718 max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
719 xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
720 1 << (max_primary_streams + 1));
721 ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
722 ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
723 | EP_HAS_LSA);
724 ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
725}
726
727/*
728 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
729 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
730 * not at the beginning of the ring).
731 */
732void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
733 struct xhci_ep_ctx *ep_ctx,
734 struct xhci_virt_ep *ep)
735{
736 dma_addr_t addr;
737 ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
738 addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
739 ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state);
740}
741
742/* Frees all stream contexts associated with the endpoint,
743 *
744 * Caller should fix the endpoint context streams fields.
745 */
746void xhci_free_stream_info(struct xhci_hcd *xhci,
747 struct xhci_stream_info *stream_info)
748{
749 int cur_stream;
750 struct xhci_ring *cur_ring;
751 dma_addr_t addr;
752
753 if (!stream_info)
754 return;
755
756 for (cur_stream = 1; cur_stream < stream_info->num_streams;
757 cur_stream++) {
758 cur_ring = stream_info->stream_rings[cur_stream];
759 if (cur_ring) {
760 addr = cur_ring->first_seg->dma;
761 radix_tree_delete(&stream_info->trb_address_map,
762 addr >> SEGMENT_SHIFT);
763 xhci_ring_free(xhci, cur_ring);
764 stream_info->stream_rings[cur_stream] = NULL;
765 }
766 }
767 xhci_free_command(xhci, stream_info->free_streams_command);
768 xhci->cmd_ring_reserved_trbs--;
769 if (stream_info->stream_ctx_array)
770 xhci_free_stream_ctx(xhci,
771 stream_info->num_stream_ctxs,
772 stream_info->stream_ctx_array,
773 stream_info->ctx_array_dma);
774
775 if (stream_info)
776 kfree(stream_info->stream_rings);
777 kfree(stream_info);
778}
779
780
781/***************** Device context manipulation *************************/
782
783static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
784 struct xhci_virt_ep *ep)
785{
786 init_timer(&ep->stop_cmd_timer);
787 ep->stop_cmd_timer.data = (unsigned long) ep;
788 ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
789 ep->xhci = xhci;
790}
791
792static void xhci_free_tt_info(struct xhci_hcd *xhci,
793 struct xhci_virt_device *virt_dev,
794 int slot_id)
795{
796 struct list_head *tt_list_head;
797 struct xhci_tt_bw_info *tt_info, *next;
798 bool slot_found = false;
799
800 /* If the device never made it past the Set Address stage,
801 * it may not have the real_port set correctly.
802 */
803 if (virt_dev->real_port == 0 ||
804 virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
805 xhci_dbg(xhci, "Bad real port.\n");
806 return;
807 }
808
809 tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
810 list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
811 /* Multi-TT hubs will have more than one entry */
812 if (tt_info->slot_id == slot_id) {
813 slot_found = true;
814 list_del(&tt_info->tt_list);
815 kfree(tt_info);
816 } else if (slot_found) {
817 break;
818 }
819 }
820}
821
822int xhci_alloc_tt_info(struct xhci_hcd *xhci,
823 struct xhci_virt_device *virt_dev,
824 struct usb_device *hdev,
825 struct usb_tt *tt, gfp_t mem_flags)
826{
827 struct xhci_tt_bw_info *tt_info;
828 unsigned int num_ports;
829 int i, j;
830
831 if (!tt->multi)
832 num_ports = 1;
833 else
834 num_ports = hdev->maxchild;
835
836 for (i = 0; i < num_ports; i++, tt_info++) {
837 struct xhci_interval_bw_table *bw_table;
838
839 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
840 if (!tt_info)
841 goto free_tts;
842 INIT_LIST_HEAD(&tt_info->tt_list);
843 list_add(&tt_info->tt_list,
844 &xhci->rh_bw[virt_dev->real_port - 1].tts);
845 tt_info->slot_id = virt_dev->udev->slot_id;
846 if (tt->multi)
847 tt_info->ttport = i+1;
848 bw_table = &tt_info->bw_table;
849 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
850 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
851 }
852 return 0;
853
854free_tts:
855 xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
856 return -ENOMEM;
857}
858
859
860/* All the xhci_tds in the ring's TD list should be freed at this point.
861 * Should be called with xhci->lock held if there is any chance the TT lists
862 * will be manipulated by the configure endpoint, allocate device, or update
863 * hub functions while this function is removing the TT entries from the list.
864 */
865void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
866{
867 struct xhci_virt_device *dev;
868 int i;
869 int old_active_eps = 0;
870
871 /* Slot ID 0 is reserved */
872 if (slot_id == 0 || !xhci->devs[slot_id])
873 return;
874
875 dev = xhci->devs[slot_id];
876 xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
877 if (!dev)
878 return;
879
880 if (dev->tt_info)
881 old_active_eps = dev->tt_info->active_eps;
882
883 for (i = 0; i < 31; ++i) {
884 if (dev->eps[i].ring)
885 xhci_ring_free(xhci, dev->eps[i].ring);
886 if (dev->eps[i].stream_info)
887 xhci_free_stream_info(xhci,
888 dev->eps[i].stream_info);
889 /* Endpoints on the TT/root port lists should have been removed
890 * when usb_disable_device() was called for the device.
891 * We can't drop them anyway, because the udev might have gone
892 * away by this point, and we can't tell what speed it was.
893 */
894 if (!list_empty(&dev->eps[i].bw_endpoint_list))
895 xhci_warn(xhci, "Slot %u endpoint %u "
896 "not removed from BW list!\n",
897 slot_id, i);
898 }
899 /* If this is a hub, free the TT(s) from the TT list */
900 xhci_free_tt_info(xhci, dev, slot_id);
901 /* If necessary, update the number of active TTs on this root port */
902 xhci_update_tt_active_eps(xhci, dev, old_active_eps);
903
904 if (dev->ring_cache) {
905 for (i = 0; i < dev->num_rings_cached; i++)
906 xhci_ring_free(xhci, dev->ring_cache[i]);
907 kfree(dev->ring_cache);
908 }
909
910 if (dev->in_ctx)
911 xhci_free_container_ctx(xhci, dev->in_ctx);
912 if (dev->out_ctx)
913 xhci_free_container_ctx(xhci, dev->out_ctx);
914
915 kfree(xhci->devs[slot_id]);
916 xhci->devs[slot_id] = NULL;
917}
918
919int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
920 struct usb_device *udev, gfp_t flags)
921{
922 struct xhci_virt_device *dev;
923 int i;
924
925 /* Slot ID 0 is reserved */
926 if (slot_id == 0 || xhci->devs[slot_id]) {
927 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
928 return 0;
929 }
930
931 xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
932 if (!xhci->devs[slot_id])
933 return 0;
934 dev = xhci->devs[slot_id];
935
936 /* Allocate the (output) device context that will be used in the HC. */
937 dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
938 if (!dev->out_ctx)
939 goto fail;
940
941 xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
942 (unsigned long long)dev->out_ctx->dma);
943
944 /* Allocate the (input) device context for address device command */
945 dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
946 if (!dev->in_ctx)
947 goto fail;
948
949 xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
950 (unsigned long long)dev->in_ctx->dma);
951
952 /* Initialize the cancellation list and watchdog timers for each ep */
953 for (i = 0; i < 31; i++) {
954 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
955 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
956 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
957 }
958
959 /* Allocate endpoint 0 ring */
960 dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, flags);
961 if (!dev->eps[0].ring)
962 goto fail;
963
964 /* Allocate pointers to the ring cache */
965 dev->ring_cache = kzalloc(
966 sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
967 flags);
968 if (!dev->ring_cache)
969 goto fail;
970 dev->num_rings_cached = 0;
971
972 init_completion(&dev->cmd_completion);
973 INIT_LIST_HEAD(&dev->cmd_list);
974 dev->udev = udev;
975
976 /* Point to output device context in dcbaa. */
977 xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
978 xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
979 slot_id,
980 &xhci->dcbaa->dev_context_ptrs[slot_id],
981 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
982
983 return 1;
984fail:
985 xhci_free_virt_device(xhci, slot_id);
986 return 0;
987}
988
989void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
990 struct usb_device *udev)
991{
992 struct xhci_virt_device *virt_dev;
993 struct xhci_ep_ctx *ep0_ctx;
994 struct xhci_ring *ep_ring;
995
996 virt_dev = xhci->devs[udev->slot_id];
997 ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
998 ep_ring = virt_dev->eps[0].ring;
999 /*
1000 * FIXME we don't keep track of the dequeue pointer very well after a
1001 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1002 * host to our enqueue pointer. This should only be called after a
1003 * configured device has reset, so all control transfers should have
1004 * been completed or cancelled before the reset.
1005 */
1006 ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1007 ep_ring->enqueue)
1008 | ep_ring->cycle_state);
1009}
1010
1011/*
1012 * The xHCI roothub may have ports of differing speeds in any order in the port
1013 * status registers. xhci->port_array provides an array of the port speed for
1014 * each offset into the port status registers.
1015 *
1016 * The xHCI hardware wants to know the roothub port number that the USB device
1017 * is attached to (or the roothub port its ancestor hub is attached to). All we
1018 * know is the index of that port under either the USB 2.0 or the USB 3.0
1019 * roothub, but that doesn't give us the real index into the HW port status
1020 * registers. Scan through the xHCI roothub port array, looking for the Nth
1021 * entry of the correct port speed. Return the port number of that entry.
1022 */
1023static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1024 struct usb_device *udev)
1025{
1026 struct usb_device *top_dev;
1027 unsigned int num_similar_speed_ports;
1028 unsigned int faked_port_num;
1029 int i;
1030
1031 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1032 top_dev = top_dev->parent)
1033 /* Found device below root hub */;
1034 faked_port_num = top_dev->portnum;
1035 for (i = 0, num_similar_speed_ports = 0;
1036 i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
1037 u8 port_speed = xhci->port_array[i];
1038
1039 /*
1040 * Skip ports that don't have known speeds, or have duplicate
1041 * Extended Capabilities port speed entries.
1042 */
1043 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1044 continue;
1045
1046 /*
1047 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1048 * 1.1 ports are under the USB 2.0 hub. If the port speed
1049 * matches the device speed, it's a similar speed port.
1050 */
1051 if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER))
1052 num_similar_speed_ports++;
1053 if (num_similar_speed_ports == faked_port_num)
1054 /* Roothub ports are numbered from 1 to N */
1055 return i+1;
1056 }
1057 return 0;
1058}
1059
1060/* Setup an xHCI virtual device for a Set Address command */
1061int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1062{
1063 struct xhci_virt_device *dev;
1064 struct xhci_ep_ctx *ep0_ctx;
1065 struct xhci_slot_ctx *slot_ctx;
1066 u32 port_num;
1067 struct usb_device *top_dev;
1068
1069 dev = xhci->devs[udev->slot_id];
1070 /* Slot ID 0 is reserved */
1071 if (udev->slot_id == 0 || !dev) {
1072 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1073 udev->slot_id);
1074 return -EINVAL;
1075 }
1076 ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1077 slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1078
1079 /* 3) Only the control endpoint is valid - one endpoint context */
1080 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1081 switch (udev->speed) {
1082 case USB_SPEED_SUPER:
1083 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1084 break;
1085 case USB_SPEED_HIGH:
1086 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1087 break;
1088 case USB_SPEED_FULL:
1089 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1090 break;
1091 case USB_SPEED_LOW:
1092 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1093 break;
1094 case USB_SPEED_WIRELESS:
1095 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1096 return -EINVAL;
1097 break;
1098 default:
1099 /* Speed was set earlier, this shouldn't happen. */
1100 BUG();
1101 }
1102 /* Find the root hub port this device is under */
1103 port_num = xhci_find_real_port_number(xhci, udev);
1104 if (!port_num)
1105 return -EINVAL;
1106 slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1107 /* Set the port number in the virtual_device to the faked port number */
1108 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1109 top_dev = top_dev->parent)
1110 /* Found device below root hub */;
1111 dev->fake_port = top_dev->portnum;
1112 dev->real_port = port_num;
1113 xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1114 xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1115
1116 /* Find the right bandwidth table that this device will be a part of.
1117 * If this is a full speed device attached directly to a root port (or a
1118 * decendent of one), it counts as a primary bandwidth domain, not a
1119 * secondary bandwidth domain under a TT. An xhci_tt_info structure
1120 * will never be created for the HS root hub.
1121 */
1122 if (!udev->tt || !udev->tt->hub->parent) {
1123 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1124 } else {
1125 struct xhci_root_port_bw_info *rh_bw;
1126 struct xhci_tt_bw_info *tt_bw;
1127
1128 rh_bw = &xhci->rh_bw[port_num - 1];
1129 /* Find the right TT. */
1130 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1131 if (tt_bw->slot_id != udev->tt->hub->slot_id)
1132 continue;
1133
1134 if (!dev->udev->tt->multi ||
1135 (udev->tt->multi &&
1136 tt_bw->ttport == dev->udev->ttport)) {
1137 dev->bw_table = &tt_bw->bw_table;
1138 dev->tt_info = tt_bw;
1139 break;
1140 }
1141 }
1142 if (!dev->tt_info)
1143 xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1144 }
1145
1146 /* Is this a LS/FS device under an external HS hub? */
1147 if (udev->tt && udev->tt->hub->parent) {
1148 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1149 (udev->ttport << 8));
1150 if (udev->tt->multi)
1151 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1152 }
1153 xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1154 xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1155
1156 /* Step 4 - ring already allocated */
1157 /* Step 5 */
1158 ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1159 /*
1160 * XXX: Not sure about wireless USB devices.
1161 */
1162 switch (udev->speed) {
1163 case USB_SPEED_SUPER:
1164 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
1165 break;
1166 case USB_SPEED_HIGH:
1167 /* USB core guesses at a 64-byte max packet first for FS devices */
1168 case USB_SPEED_FULL:
1169 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
1170 break;
1171 case USB_SPEED_LOW:
1172 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
1173 break;
1174 case USB_SPEED_WIRELESS:
1175 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1176 return -EINVAL;
1177 break;
1178 default:
1179 /* New speed? */
1180 BUG();
1181 }
1182 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1183 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
1184
1185 ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1186 dev->eps[0].ring->cycle_state);
1187
1188 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1189
1190 return 0;
1191}
1192
1193/*
1194 * Convert interval expressed as 2^(bInterval - 1) == interval into
1195 * straight exponent value 2^n == interval.
1196 *
1197 */
1198static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1199 struct usb_host_endpoint *ep)
1200{
1201 unsigned int interval;
1202
1203 interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1204 if (interval != ep->desc.bInterval - 1)
1205 dev_warn(&udev->dev,
1206 "ep %#x - rounding interval to %d %sframes\n",
1207 ep->desc.bEndpointAddress,
1208 1 << interval,
1209 udev->speed == USB_SPEED_FULL ? "" : "micro");
1210
1211 if (udev->speed == USB_SPEED_FULL) {
1212 /*
1213 * Full speed isoc endpoints specify interval in frames,
1214 * not microframes. We are using microframes everywhere,
1215 * so adjust accordingly.
1216 */
1217 interval += 3; /* 1 frame = 2^3 uframes */
1218 }
1219
1220 return interval;
1221}
1222
1223/*
1224 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1225 * microframes, rounded down to nearest power of 2.
1226 */
1227static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1228 struct usb_host_endpoint *ep, unsigned int desc_interval,
1229 unsigned int min_exponent, unsigned int max_exponent)
1230{
1231 unsigned int interval;
1232
1233 interval = fls(desc_interval) - 1;
1234 interval = clamp_val(interval, min_exponent, max_exponent);
1235 if ((1 << interval) != desc_interval)
1236 dev_warn(&udev->dev,
1237 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1238 ep->desc.bEndpointAddress,
1239 1 << interval,
1240 desc_interval);
1241
1242 return interval;
1243}
1244
1245static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1246 struct usb_host_endpoint *ep)
1247{
1248 return xhci_microframes_to_exponent(udev, ep,
1249 ep->desc.bInterval, 0, 15);
1250}
1251
1252
1253static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1254 struct usb_host_endpoint *ep)
1255{
1256 return xhci_microframes_to_exponent(udev, ep,
1257 ep->desc.bInterval * 8, 3, 10);
1258}
1259
1260/* Return the polling or NAK interval.
1261 *
1262 * The polling interval is expressed in "microframes". If xHCI's Interval field
1263 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1264 *
1265 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1266 * is set to 0.
1267 */
1268static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1269 struct usb_host_endpoint *ep)
1270{
1271 unsigned int interval = 0;
1272
1273 switch (udev->speed) {
1274 case USB_SPEED_HIGH:
1275 /* Max NAK rate */
1276 if (usb_endpoint_xfer_control(&ep->desc) ||
1277 usb_endpoint_xfer_bulk(&ep->desc)) {
1278 interval = xhci_parse_microframe_interval(udev, ep);
1279 break;
1280 }
1281 /* Fall through - SS and HS isoc/int have same decoding */
1282
1283 case USB_SPEED_SUPER:
1284 if (usb_endpoint_xfer_int(&ep->desc) ||
1285 usb_endpoint_xfer_isoc(&ep->desc)) {
1286 interval = xhci_parse_exponent_interval(udev, ep);
1287 }
1288 break;
1289
1290 case USB_SPEED_FULL:
1291 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1292 interval = xhci_parse_exponent_interval(udev, ep);
1293 break;
1294 }
1295 /*
1296 * Fall through for interrupt endpoint interval decoding
1297 * since it uses the same rules as low speed interrupt
1298 * endpoints.
1299 */
1300
1301 case USB_SPEED_LOW:
1302 if (usb_endpoint_xfer_int(&ep->desc) ||
1303 usb_endpoint_xfer_isoc(&ep->desc)) {
1304
1305 interval = xhci_parse_frame_interval(udev, ep);
1306 }
1307 break;
1308
1309 default:
1310 BUG();
1311 }
1312 return EP_INTERVAL(interval);
1313}
1314
1315/* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1316 * High speed endpoint descriptors can define "the number of additional
1317 * transaction opportunities per microframe", but that goes in the Max Burst
1318 * endpoint context field.
1319 */
1320static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1321 struct usb_host_endpoint *ep)
1322{
1323 if (udev->speed != USB_SPEED_SUPER ||
1324 !usb_endpoint_xfer_isoc(&ep->desc))
1325 return 0;
1326 return ep->ss_ep_comp.bmAttributes;
1327}
1328
1329static u32 xhci_get_endpoint_type(struct usb_device *udev,
1330 struct usb_host_endpoint *ep)
1331{
1332 int in;
1333 u32 type;
1334
1335 in = usb_endpoint_dir_in(&ep->desc);
1336 if (usb_endpoint_xfer_control(&ep->desc)) {
1337 type = EP_TYPE(CTRL_EP);
1338 } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1339 if (in)
1340 type = EP_TYPE(BULK_IN_EP);
1341 else
1342 type = EP_TYPE(BULK_OUT_EP);
1343 } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1344 if (in)
1345 type = EP_TYPE(ISOC_IN_EP);
1346 else
1347 type = EP_TYPE(ISOC_OUT_EP);
1348 } else if (usb_endpoint_xfer_int(&ep->desc)) {
1349 if (in)
1350 type = EP_TYPE(INT_IN_EP);
1351 else
1352 type = EP_TYPE(INT_OUT_EP);
1353 } else {
1354 BUG();
1355 }
1356 return type;
1357}
1358
1359/* Return the maximum endpoint service interval time (ESIT) payload.
1360 * Basically, this is the maxpacket size, multiplied by the burst size
1361 * and mult size.
1362 */
1363static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1364 struct usb_device *udev,
1365 struct usb_host_endpoint *ep)
1366{
1367 int max_burst;
1368 int max_packet;
1369
1370 /* Only applies for interrupt or isochronous endpoints */
1371 if (usb_endpoint_xfer_control(&ep->desc) ||
1372 usb_endpoint_xfer_bulk(&ep->desc))
1373 return 0;
1374
1375 if (udev->speed == USB_SPEED_SUPER)
1376 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1377
1378 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1379 max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1380 /* A 0 in max burst means 1 transfer per ESIT */
1381 return max_packet * (max_burst + 1);
1382}
1383
1384/* Set up an endpoint with one ring segment. Do not allocate stream rings.
1385 * Drivers will have to call usb_alloc_streams() to do that.
1386 */
1387int xhci_endpoint_init(struct xhci_hcd *xhci,
1388 struct xhci_virt_device *virt_dev,
1389 struct usb_device *udev,
1390 struct usb_host_endpoint *ep,
1391 gfp_t mem_flags)
1392{
1393 unsigned int ep_index;
1394 struct xhci_ep_ctx *ep_ctx;
1395 struct xhci_ring *ep_ring;
1396 unsigned int max_packet;
1397 unsigned int max_burst;
1398 enum xhci_ring_type type;
1399 u32 max_esit_payload;
1400
1401 ep_index = xhci_get_endpoint_index(&ep->desc);
1402 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1403
1404 type = usb_endpoint_type(&ep->desc);
1405 /* Set up the endpoint ring */
1406 virt_dev->eps[ep_index].new_ring =
1407 xhci_ring_alloc(xhci, 2, 1, type, mem_flags);
1408 if (!virt_dev->eps[ep_index].new_ring) {
1409 /* Attempt to use the ring cache */
1410 if (virt_dev->num_rings_cached == 0)
1411 return -ENOMEM;
1412 virt_dev->eps[ep_index].new_ring =
1413 virt_dev->ring_cache[virt_dev->num_rings_cached];
1414 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1415 virt_dev->num_rings_cached--;
1416 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1417 1, type);
1418 }
1419 virt_dev->eps[ep_index].skip = false;
1420 ep_ring = virt_dev->eps[ep_index].new_ring;
1421 ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1422
1423 ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1424 | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1425
1426 /* FIXME dig Mult and streams info out of ep companion desc */
1427
1428 /* Allow 3 retries for everything but isoc;
1429 * CErr shall be set to 0 for Isoch endpoints.
1430 */
1431 if (!usb_endpoint_xfer_isoc(&ep->desc))
1432 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
1433 else
1434 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
1435
1436 ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
1437
1438 /* Set the max packet size and max burst */
1439 switch (udev->speed) {
1440 case USB_SPEED_SUPER:
1441 max_packet = usb_endpoint_maxp(&ep->desc);
1442 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1443 /* dig out max burst from ep companion desc */
1444 max_packet = ep->ss_ep_comp.bMaxBurst;
1445 ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet));
1446 break;
1447 case USB_SPEED_HIGH:
1448 /* bits 11:12 specify the number of additional transaction
1449 * opportunities per microframe (USB 2.0, section 9.6.6)
1450 */
1451 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1452 usb_endpoint_xfer_int(&ep->desc)) {
1453 max_burst = (usb_endpoint_maxp(&ep->desc)
1454 & 0x1800) >> 11;
1455 ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst));
1456 }
1457 /* Fall through */
1458 case USB_SPEED_FULL:
1459 case USB_SPEED_LOW:
1460 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1461 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1462 break;
1463 default:
1464 BUG();
1465 }
1466 max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1467 ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1468
1469 /*
1470 * XXX no idea how to calculate the average TRB buffer length for bulk
1471 * endpoints, as the driver gives us no clue how big each scatter gather
1472 * list entry (or buffer) is going to be.
1473 *
1474 * For isochronous and interrupt endpoints, we set it to the max
1475 * available, until we have new API in the USB core to allow drivers to
1476 * declare how much bandwidth they actually need.
1477 *
1478 * Normally, it would be calculated by taking the total of the buffer
1479 * lengths in the TD and then dividing by the number of TRBs in a TD,
1480 * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't
1481 * use Event Data TRBs, and we don't chain in a link TRB on short
1482 * transfers, we're basically dividing by 1.
1483 *
1484 * xHCI 1.0 specification indicates that the Average TRB Length should
1485 * be set to 8 for control endpoints.
1486 */
1487 if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1488 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1489 else
1490 ep_ctx->tx_info |=
1491 cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1492
1493 /* FIXME Debug endpoint context */
1494 return 0;
1495}
1496
1497void xhci_endpoint_zero(struct xhci_hcd *xhci,
1498 struct xhci_virt_device *virt_dev,
1499 struct usb_host_endpoint *ep)
1500{
1501 unsigned int ep_index;
1502 struct xhci_ep_ctx *ep_ctx;
1503
1504 ep_index = xhci_get_endpoint_index(&ep->desc);
1505 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1506
1507 ep_ctx->ep_info = 0;
1508 ep_ctx->ep_info2 = 0;
1509 ep_ctx->deq = 0;
1510 ep_ctx->tx_info = 0;
1511 /* Don't free the endpoint ring until the set interface or configuration
1512 * request succeeds.
1513 */
1514}
1515
1516void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1517{
1518 bw_info->ep_interval = 0;
1519 bw_info->mult = 0;
1520 bw_info->num_packets = 0;
1521 bw_info->max_packet_size = 0;
1522 bw_info->type = 0;
1523 bw_info->max_esit_payload = 0;
1524}
1525
1526void xhci_update_bw_info(struct xhci_hcd *xhci,
1527 struct xhci_container_ctx *in_ctx,
1528 struct xhci_input_control_ctx *ctrl_ctx,
1529 struct xhci_virt_device *virt_dev)
1530{
1531 struct xhci_bw_info *bw_info;
1532 struct xhci_ep_ctx *ep_ctx;
1533 unsigned int ep_type;
1534 int i;
1535
1536 for (i = 1; i < 31; ++i) {
1537 bw_info = &virt_dev->eps[i].bw_info;
1538
1539 /* We can't tell what endpoint type is being dropped, but
1540 * unconditionally clearing the bandwidth info for non-periodic
1541 * endpoints should be harmless because the info will never be
1542 * set in the first place.
1543 */
1544 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1545 /* Dropped endpoint */
1546 xhci_clear_endpoint_bw_info(bw_info);
1547 continue;
1548 }
1549
1550 if (EP_IS_ADDED(ctrl_ctx, i)) {
1551 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1552 ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1553
1554 /* Ignore non-periodic endpoints */
1555 if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1556 ep_type != ISOC_IN_EP &&
1557 ep_type != INT_IN_EP)
1558 continue;
1559
1560 /* Added or changed endpoint */
1561 bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1562 le32_to_cpu(ep_ctx->ep_info));
1563 /* Number of packets and mult are zero-based in the
1564 * input context, but we want one-based for the
1565 * interval table.
1566 */
1567 bw_info->mult = CTX_TO_EP_MULT(
1568 le32_to_cpu(ep_ctx->ep_info)) + 1;
1569 bw_info->num_packets = CTX_TO_MAX_BURST(
1570 le32_to_cpu(ep_ctx->ep_info2)) + 1;
1571 bw_info->max_packet_size = MAX_PACKET_DECODED(
1572 le32_to_cpu(ep_ctx->ep_info2));
1573 bw_info->type = ep_type;
1574 bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1575 le32_to_cpu(ep_ctx->tx_info));
1576 }
1577 }
1578}
1579
1580/* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1581 * Useful when you want to change one particular aspect of the endpoint and then
1582 * issue a configure endpoint command.
1583 */
1584void xhci_endpoint_copy(struct xhci_hcd *xhci,
1585 struct xhci_container_ctx *in_ctx,
1586 struct xhci_container_ctx *out_ctx,
1587 unsigned int ep_index)
1588{
1589 struct xhci_ep_ctx *out_ep_ctx;
1590 struct xhci_ep_ctx *in_ep_ctx;
1591
1592 out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1593 in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1594
1595 in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1596 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1597 in_ep_ctx->deq = out_ep_ctx->deq;
1598 in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1599}
1600
1601/* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1602 * Useful when you want to change one particular aspect of the endpoint and then
1603 * issue a configure endpoint command. Only the context entries field matters,
1604 * but we'll copy the whole thing anyway.
1605 */
1606void xhci_slot_copy(struct xhci_hcd *xhci,
1607 struct xhci_container_ctx *in_ctx,
1608 struct xhci_container_ctx *out_ctx)
1609{
1610 struct xhci_slot_ctx *in_slot_ctx;
1611 struct xhci_slot_ctx *out_slot_ctx;
1612
1613 in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1614 out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1615
1616 in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1617 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1618 in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1619 in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1620}
1621
1622/* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1623static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1624{
1625 int i;
1626 struct device *dev = xhci_to_hcd(xhci)->self.controller;
1627 int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1628
1629 xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1630
1631 if (!num_sp)
1632 return 0;
1633
1634 xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1635 if (!xhci->scratchpad)
1636 goto fail_sp;
1637
1638 xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1639 num_sp * sizeof(u64),
1640 &xhci->scratchpad->sp_dma, flags);
1641 if (!xhci->scratchpad->sp_array)
1642 goto fail_sp2;
1643
1644 xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1645 if (!xhci->scratchpad->sp_buffers)
1646 goto fail_sp3;
1647
1648 xhci->scratchpad->sp_dma_buffers =
1649 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1650
1651 if (!xhci->scratchpad->sp_dma_buffers)
1652 goto fail_sp4;
1653
1654 xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1655 for (i = 0; i < num_sp; i++) {
1656 dma_addr_t dma;
1657 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1658 flags);
1659 if (!buf)
1660 goto fail_sp5;
1661
1662 xhci->scratchpad->sp_array[i] = dma;
1663 xhci->scratchpad->sp_buffers[i] = buf;
1664 xhci->scratchpad->sp_dma_buffers[i] = dma;
1665 }
1666
1667 return 0;
1668
1669 fail_sp5:
1670 for (i = i - 1; i >= 0; i--) {
1671 dma_free_coherent(dev, xhci->page_size,
1672 xhci->scratchpad->sp_buffers[i],
1673 xhci->scratchpad->sp_dma_buffers[i]);
1674 }
1675 kfree(xhci->scratchpad->sp_dma_buffers);
1676
1677 fail_sp4:
1678 kfree(xhci->scratchpad->sp_buffers);
1679
1680 fail_sp3:
1681 dma_free_coherent(dev, num_sp * sizeof(u64),
1682 xhci->scratchpad->sp_array,
1683 xhci->scratchpad->sp_dma);
1684
1685 fail_sp2:
1686 kfree(xhci->scratchpad);
1687 xhci->scratchpad = NULL;
1688
1689 fail_sp:
1690 return -ENOMEM;
1691}
1692
1693static void scratchpad_free(struct xhci_hcd *xhci)
1694{
1695 int num_sp;
1696 int i;
1697 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1698
1699 if (!xhci->scratchpad)
1700 return;
1701
1702 num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1703
1704 for (i = 0; i < num_sp; i++) {
1705 dma_free_coherent(&pdev->dev, xhci->page_size,
1706 xhci->scratchpad->sp_buffers[i],
1707 xhci->scratchpad->sp_dma_buffers[i]);
1708 }
1709 kfree(xhci->scratchpad->sp_dma_buffers);
1710 kfree(xhci->scratchpad->sp_buffers);
1711 dma_free_coherent(&pdev->dev, num_sp * sizeof(u64),
1712 xhci->scratchpad->sp_array,
1713 xhci->scratchpad->sp_dma);
1714 kfree(xhci->scratchpad);
1715 xhci->scratchpad = NULL;
1716}
1717
1718struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1719 bool allocate_in_ctx, bool allocate_completion,
1720 gfp_t mem_flags)
1721{
1722 struct xhci_command *command;
1723
1724 command = kzalloc(sizeof(*command), mem_flags);
1725 if (!command)
1726 return NULL;
1727
1728 if (allocate_in_ctx) {
1729 command->in_ctx =
1730 xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1731 mem_flags);
1732 if (!command->in_ctx) {
1733 kfree(command);
1734 return NULL;
1735 }
1736 }
1737
1738 if (allocate_completion) {
1739 command->completion =
1740 kzalloc(sizeof(struct completion), mem_flags);
1741 if (!command->completion) {
1742 xhci_free_container_ctx(xhci, command->in_ctx);
1743 kfree(command);
1744 return NULL;
1745 }
1746 init_completion(command->completion);
1747 }
1748
1749 command->status = 0;
1750 INIT_LIST_HEAD(&command->cmd_list);
1751 return command;
1752}
1753
1754void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1755{
1756 if (urb_priv) {
1757 kfree(urb_priv->td[0]);
1758 kfree(urb_priv);
1759 }
1760}
1761
1762void xhci_free_command(struct xhci_hcd *xhci,
1763 struct xhci_command *command)
1764{
1765 xhci_free_container_ctx(xhci,
1766 command->in_ctx);
1767 kfree(command->completion);
1768 kfree(command);
1769}
1770
1771void xhci_mem_cleanup(struct xhci_hcd *xhci)
1772{
1773 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1774 struct dev_info *dev_info, *next;
1775 struct xhci_cd *cur_cd, *next_cd;
1776 unsigned long flags;
1777 int size;
1778 int i, j, num_ports;
1779
1780 /* Free the Event Ring Segment Table and the actual Event Ring */
1781 size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1782 if (xhci->erst.entries)
1783 dma_free_coherent(&pdev->dev, size,
1784 xhci->erst.entries, xhci->erst.erst_dma_addr);
1785 xhci->erst.entries = NULL;
1786 xhci_dbg(xhci, "Freed ERST\n");
1787 if (xhci->event_ring)
1788 xhci_ring_free(xhci, xhci->event_ring);
1789 xhci->event_ring = NULL;
1790 xhci_dbg(xhci, "Freed event ring\n");
1791
1792 if (xhci->lpm_command)
1793 xhci_free_command(xhci, xhci->lpm_command);
1794 xhci->cmd_ring_reserved_trbs = 0;
1795 if (xhci->cmd_ring)
1796 xhci_ring_free(xhci, xhci->cmd_ring);
1797 xhci->cmd_ring = NULL;
1798 xhci_dbg(xhci, "Freed command ring\n");
1799 list_for_each_entry_safe(cur_cd, next_cd,
1800 &xhci->cancel_cmd_list, cancel_cmd_list) {
1801 list_del(&cur_cd->cancel_cmd_list);
1802 kfree(cur_cd);
1803 }
1804
1805 for (i = 1; i < MAX_HC_SLOTS; ++i)
1806 xhci_free_virt_device(xhci, i);
1807
1808 if (xhci->segment_pool)
1809 dma_pool_destroy(xhci->segment_pool);
1810 xhci->segment_pool = NULL;
1811 xhci_dbg(xhci, "Freed segment pool\n");
1812
1813 if (xhci->device_pool)
1814 dma_pool_destroy(xhci->device_pool);
1815 xhci->device_pool = NULL;
1816 xhci_dbg(xhci, "Freed device context pool\n");
1817
1818 if (xhci->small_streams_pool)
1819 dma_pool_destroy(xhci->small_streams_pool);
1820 xhci->small_streams_pool = NULL;
1821 xhci_dbg(xhci, "Freed small stream array pool\n");
1822
1823 if (xhci->medium_streams_pool)
1824 dma_pool_destroy(xhci->medium_streams_pool);
1825 xhci->medium_streams_pool = NULL;
1826 xhci_dbg(xhci, "Freed medium stream array pool\n");
1827
1828 if (xhci->dcbaa)
1829 dma_free_coherent(&pdev->dev, sizeof(*xhci->dcbaa),
1830 xhci->dcbaa, xhci->dcbaa->dma);
1831 xhci->dcbaa = NULL;
1832
1833 scratchpad_free(xhci);
1834
1835 spin_lock_irqsave(&xhci->lock, flags);
1836 list_for_each_entry_safe(dev_info, next, &xhci->lpm_failed_devs, list) {
1837 list_del(&dev_info->list);
1838 kfree(dev_info);
1839 }
1840 spin_unlock_irqrestore(&xhci->lock, flags);
1841
1842 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1843 for (i = 0; i < num_ports; i++) {
1844 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1845 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1846 struct list_head *ep = &bwt->interval_bw[j].endpoints;
1847 while (!list_empty(ep))
1848 list_del_init(ep->next);
1849 }
1850 }
1851
1852 for (i = 0; i < num_ports; i++) {
1853 struct xhci_tt_bw_info *tt, *n;
1854 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1855 list_del(&tt->tt_list);
1856 kfree(tt);
1857 }
1858 }
1859
1860 xhci->num_usb2_ports = 0;
1861 xhci->num_usb3_ports = 0;
1862 xhci->num_active_eps = 0;
1863 kfree(xhci->usb2_ports);
1864 kfree(xhci->usb3_ports);
1865 kfree(xhci->port_array);
1866 kfree(xhci->rh_bw);
1867
1868 xhci->page_size = 0;
1869 xhci->page_shift = 0;
1870 xhci->bus_state[0].bus_suspended = 0;
1871 xhci->bus_state[1].bus_suspended = 0;
1872}
1873
1874static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1875 struct xhci_segment *input_seg,
1876 union xhci_trb *start_trb,
1877 union xhci_trb *end_trb,
1878 dma_addr_t input_dma,
1879 struct xhci_segment *result_seg,
1880 char *test_name, int test_number)
1881{
1882 unsigned long long start_dma;
1883 unsigned long long end_dma;
1884 struct xhci_segment *seg;
1885
1886 start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1887 end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1888
1889 seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1890 if (seg != result_seg) {
1891 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1892 test_name, test_number);
1893 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1894 "input DMA 0x%llx\n",
1895 input_seg,
1896 (unsigned long long) input_dma);
1897 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1898 "ending TRB %p (0x%llx DMA)\n",
1899 start_trb, start_dma,
1900 end_trb, end_dma);
1901 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1902 result_seg, seg);
1903 return -1;
1904 }
1905 return 0;
1906}
1907
1908/* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1909static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1910{
1911 struct {
1912 dma_addr_t input_dma;
1913 struct xhci_segment *result_seg;
1914 } simple_test_vector [] = {
1915 /* A zeroed DMA field should fail */
1916 { 0, NULL },
1917 /* One TRB before the ring start should fail */
1918 { xhci->event_ring->first_seg->dma - 16, NULL },
1919 /* One byte before the ring start should fail */
1920 { xhci->event_ring->first_seg->dma - 1, NULL },
1921 /* Starting TRB should succeed */
1922 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1923 /* Ending TRB should succeed */
1924 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1925 xhci->event_ring->first_seg },
1926 /* One byte after the ring end should fail */
1927 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1928 /* One TRB after the ring end should fail */
1929 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1930 /* An address of all ones should fail */
1931 { (dma_addr_t) (~0), NULL },
1932 };
1933 struct {
1934 struct xhci_segment *input_seg;
1935 union xhci_trb *start_trb;
1936 union xhci_trb *end_trb;
1937 dma_addr_t input_dma;
1938 struct xhci_segment *result_seg;
1939 } complex_test_vector [] = {
1940 /* Test feeding a valid DMA address from a different ring */
1941 { .input_seg = xhci->event_ring->first_seg,
1942 .start_trb = xhci->event_ring->first_seg->trbs,
1943 .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1944 .input_dma = xhci->cmd_ring->first_seg->dma,
1945 .result_seg = NULL,
1946 },
1947 /* Test feeding a valid end TRB from a different ring */
1948 { .input_seg = xhci->event_ring->first_seg,
1949 .start_trb = xhci->event_ring->first_seg->trbs,
1950 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1951 .input_dma = xhci->cmd_ring->first_seg->dma,
1952 .result_seg = NULL,
1953 },
1954 /* Test feeding a valid start and end TRB from a different ring */
1955 { .input_seg = xhci->event_ring->first_seg,
1956 .start_trb = xhci->cmd_ring->first_seg->trbs,
1957 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1958 .input_dma = xhci->cmd_ring->first_seg->dma,
1959 .result_seg = NULL,
1960 },
1961 /* TRB in this ring, but after this TD */
1962 { .input_seg = xhci->event_ring->first_seg,
1963 .start_trb = &xhci->event_ring->first_seg->trbs[0],
1964 .end_trb = &xhci->event_ring->first_seg->trbs[3],
1965 .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1966 .result_seg = NULL,
1967 },
1968 /* TRB in this ring, but before this TD */
1969 { .input_seg = xhci->event_ring->first_seg,
1970 .start_trb = &xhci->event_ring->first_seg->trbs[3],
1971 .end_trb = &xhci->event_ring->first_seg->trbs[6],
1972 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1973 .result_seg = NULL,
1974 },
1975 /* TRB in this ring, but after this wrapped TD */
1976 { .input_seg = xhci->event_ring->first_seg,
1977 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1978 .end_trb = &xhci->event_ring->first_seg->trbs[1],
1979 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1980 .result_seg = NULL,
1981 },
1982 /* TRB in this ring, but before this wrapped TD */
1983 { .input_seg = xhci->event_ring->first_seg,
1984 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1985 .end_trb = &xhci->event_ring->first_seg->trbs[1],
1986 .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1987 .result_seg = NULL,
1988 },
1989 /* TRB not in this ring, and we have a wrapped TD */
1990 { .input_seg = xhci->event_ring->first_seg,
1991 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1992 .end_trb = &xhci->event_ring->first_seg->trbs[1],
1993 .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1994 .result_seg = NULL,
1995 },
1996 };
1997
1998 unsigned int num_tests;
1999 int i, ret;
2000
2001 num_tests = ARRAY_SIZE(simple_test_vector);
2002 for (i = 0; i < num_tests; i++) {
2003 ret = xhci_test_trb_in_td(xhci,
2004 xhci->event_ring->first_seg,
2005 xhci->event_ring->first_seg->trbs,
2006 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2007 simple_test_vector[i].input_dma,
2008 simple_test_vector[i].result_seg,
2009 "Simple", i);
2010 if (ret < 0)
2011 return ret;
2012 }
2013
2014 num_tests = ARRAY_SIZE(complex_test_vector);
2015 for (i = 0; i < num_tests; i++) {
2016 ret = xhci_test_trb_in_td(xhci,
2017 complex_test_vector[i].input_seg,
2018 complex_test_vector[i].start_trb,
2019 complex_test_vector[i].end_trb,
2020 complex_test_vector[i].input_dma,
2021 complex_test_vector[i].result_seg,
2022 "Complex", i);
2023 if (ret < 0)
2024 return ret;
2025 }
2026 xhci_dbg(xhci, "TRB math tests passed.\n");
2027 return 0;
2028}
2029
2030static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
2031{
2032 u64 temp;
2033 dma_addr_t deq;
2034
2035 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2036 xhci->event_ring->dequeue);
2037 if (deq == 0 && !in_interrupt())
2038 xhci_warn(xhci, "WARN something wrong with SW event ring "
2039 "dequeue ptr.\n");
2040 /* Update HC event ring dequeue pointer */
2041 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2042 temp &= ERST_PTR_MASK;
2043 /* Don't clear the EHB bit (which is RW1C) because
2044 * there might be more events to service.
2045 */
2046 temp &= ~ERST_EHB;
2047 xhci_dbg(xhci, "// Write event ring dequeue pointer, "
2048 "preserving EHB bit\n");
2049 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2050 &xhci->ir_set->erst_dequeue);
2051}
2052
2053static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2054 __le32 __iomem *addr, u8 major_revision)
2055{
2056 u32 temp, port_offset, port_count;
2057 int i;
2058
2059 if (major_revision > 0x03) {
2060 xhci_warn(xhci, "Ignoring unknown port speed, "
2061 "Ext Cap %p, revision = 0x%x\n",
2062 addr, major_revision);
2063 /* Ignoring port protocol we can't understand. FIXME */
2064 return;
2065 }
2066
2067 /* Port offset and count in the third dword, see section 7.2 */
2068 temp = xhci_readl(xhci, addr + 2);
2069 port_offset = XHCI_EXT_PORT_OFF(temp);
2070 port_count = XHCI_EXT_PORT_COUNT(temp);
2071 xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
2072 "count = %u, revision = 0x%x\n",
2073 addr, port_offset, port_count, major_revision);
2074 /* Port count includes the current port offset */
2075 if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2076 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2077 return;
2078
2079 /* Check the host's USB2 LPM capability */
2080 if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
2081 (temp & XHCI_L1C)) {
2082 xhci_dbg(xhci, "xHCI 0.96: support USB2 software lpm\n");
2083 xhci->sw_lpm_support = 1;
2084 }
2085
2086 if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2087 xhci_dbg(xhci, "xHCI 1.0: support USB2 software lpm\n");
2088 xhci->sw_lpm_support = 1;
2089 if (temp & XHCI_HLC) {
2090 xhci_dbg(xhci, "xHCI 1.0: support USB2 hardware lpm\n");
2091 xhci->hw_lpm_support = 1;
2092 }
2093 }
2094
2095 port_offset--;
2096 for (i = port_offset; i < (port_offset + port_count); i++) {
2097 /* Duplicate entry. Ignore the port if the revisions differ. */
2098 if (xhci->port_array[i] != 0) {
2099 xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2100 " port %u\n", addr, i);
2101 xhci_warn(xhci, "Port was marked as USB %u, "
2102 "duplicated as USB %u\n",
2103 xhci->port_array[i], major_revision);
2104 /* Only adjust the roothub port counts if we haven't
2105 * found a similar duplicate.
2106 */
2107 if (xhci->port_array[i] != major_revision &&
2108 xhci->port_array[i] != DUPLICATE_ENTRY) {
2109 if (xhci->port_array[i] == 0x03)
2110 xhci->num_usb3_ports--;
2111 else
2112 xhci->num_usb2_ports--;
2113 xhci->port_array[i] = DUPLICATE_ENTRY;
2114 }
2115 /* FIXME: Should we disable the port? */
2116 continue;
2117 }
2118 xhci->port_array[i] = major_revision;
2119 if (major_revision == 0x03)
2120 xhci->num_usb3_ports++;
2121 else
2122 xhci->num_usb2_ports++;
2123 }
2124 /* FIXME: Should we disable ports not in the Extended Capabilities? */
2125}
2126
2127/*
2128 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2129 * specify what speeds each port is supposed to be. We can't count on the port
2130 * speed bits in the PORTSC register being correct until a device is connected,
2131 * but we need to set up the two fake roothubs with the correct number of USB
2132 * 3.0 and USB 2.0 ports at host controller initialization time.
2133 */
2134static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2135{
2136 __le32 __iomem *addr;
2137 u32 offset;
2138 unsigned int num_ports;
2139 int i, j, port_index;
2140
2141 addr = &xhci->cap_regs->hcc_params;
2142 offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
2143 if (offset == 0) {
2144 xhci_err(xhci, "No Extended Capability registers, "
2145 "unable to set up roothub.\n");
2146 return -ENODEV;
2147 }
2148
2149 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2150 xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2151 if (!xhci->port_array)
2152 return -ENOMEM;
2153
2154 xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2155 if (!xhci->rh_bw)
2156 return -ENOMEM;
2157 for (i = 0; i < num_ports; i++) {
2158 struct xhci_interval_bw_table *bw_table;
2159
2160 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2161 bw_table = &xhci->rh_bw[i].bw_table;
2162 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2163 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2164 }
2165
2166 /*
2167 * For whatever reason, the first capability offset is from the
2168 * capability register base, not from the HCCPARAMS register.
2169 * See section 5.3.6 for offset calculation.
2170 */
2171 addr = &xhci->cap_regs->hc_capbase + offset;
2172 while (1) {
2173 u32 cap_id;
2174
2175 cap_id = xhci_readl(xhci, addr);
2176 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2177 xhci_add_in_port(xhci, num_ports, addr,
2178 (u8) XHCI_EXT_PORT_MAJOR(cap_id));
2179 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2180 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2181 == num_ports)
2182 break;
2183 /*
2184 * Once you're into the Extended Capabilities, the offset is
2185 * always relative to the register holding the offset.
2186 */
2187 addr += offset;
2188 }
2189
2190 if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2191 xhci_warn(xhci, "No ports on the roothubs?\n");
2192 return -ENODEV;
2193 }
2194 xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2195 xhci->num_usb2_ports, xhci->num_usb3_ports);
2196
2197 /* Place limits on the number of roothub ports so that the hub
2198 * descriptors aren't longer than the USB core will allocate.
2199 */
2200 if (xhci->num_usb3_ports > 15) {
2201 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
2202 xhci->num_usb3_ports = 15;
2203 }
2204 if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2205 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
2206 USB_MAXCHILDREN);
2207 xhci->num_usb2_ports = USB_MAXCHILDREN;
2208 }
2209
2210 /*
2211 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2212 * Not sure how the USB core will handle a hub with no ports...
2213 */
2214 if (xhci->num_usb2_ports) {
2215 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2216 xhci->num_usb2_ports, flags);
2217 if (!xhci->usb2_ports)
2218 return -ENOMEM;
2219
2220 port_index = 0;
2221 for (i = 0; i < num_ports; i++) {
2222 if (xhci->port_array[i] == 0x03 ||
2223 xhci->port_array[i] == 0 ||
2224 xhci->port_array[i] == DUPLICATE_ENTRY)
2225 continue;
2226
2227 xhci->usb2_ports[port_index] =
2228 &xhci->op_regs->port_status_base +
2229 NUM_PORT_REGS*i;
2230 xhci_dbg(xhci, "USB 2.0 port at index %u, "
2231 "addr = %p\n", i,
2232 xhci->usb2_ports[port_index]);
2233 port_index++;
2234 if (port_index == xhci->num_usb2_ports)
2235 break;
2236 }
2237 }
2238 if (xhci->num_usb3_ports) {
2239 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2240 xhci->num_usb3_ports, flags);
2241 if (!xhci->usb3_ports)
2242 return -ENOMEM;
2243
2244 port_index = 0;
2245 for (i = 0; i < num_ports; i++)
2246 if (xhci->port_array[i] == 0x03) {
2247 xhci->usb3_ports[port_index] =
2248 &xhci->op_regs->port_status_base +
2249 NUM_PORT_REGS*i;
2250 xhci_dbg(xhci, "USB 3.0 port at index %u, "
2251 "addr = %p\n", i,
2252 xhci->usb3_ports[port_index]);
2253 port_index++;
2254 if (port_index == xhci->num_usb3_ports)
2255 break;
2256 }
2257 }
2258 return 0;
2259}
2260
2261int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2262{
2263 dma_addr_t dma;
2264 struct device *dev = xhci_to_hcd(xhci)->self.controller;
2265 unsigned int val, val2;
2266 u64 val_64;
2267 struct xhci_segment *seg;
2268 u32 page_size, temp;
2269 int i;
2270
2271 page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
2272 xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
2273 for (i = 0; i < 16; i++) {
2274 if ((0x1 & page_size) != 0)
2275 break;
2276 page_size = page_size >> 1;
2277 }
2278 if (i < 16)
2279 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
2280 else
2281 xhci_warn(xhci, "WARN: no supported page size\n");
2282 /* Use 4K pages, since that's common and the minimum the HC supports */
2283 xhci->page_shift = 12;
2284 xhci->page_size = 1 << xhci->page_shift;
2285 xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
2286
2287 /*
2288 * Program the Number of Device Slots Enabled field in the CONFIG
2289 * register with the max value of slots the HC can handle.
2290 */
2291 val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
2292 xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
2293 (unsigned int) val);
2294 val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
2295 val |= (val2 & ~HCS_SLOTS_MASK);
2296 xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
2297 (unsigned int) val);
2298 xhci_writel(xhci, val, &xhci->op_regs->config_reg);
2299
2300 /*
2301 * Section 5.4.8 - doorbell array must be
2302 * "physically contiguous and 64-byte (cache line) aligned".
2303 */
2304 xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2305 GFP_KERNEL);
2306 if (!xhci->dcbaa)
2307 goto fail;
2308 memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2309 xhci->dcbaa->dma = dma;
2310 xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2311 (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2312 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2313
2314 /*
2315 * Initialize the ring segment pool. The ring must be a contiguous
2316 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
2317 * however, the command ring segment needs 64-byte aligned segments,
2318 * so we pick the greater alignment need.
2319 */
2320 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2321 SEGMENT_SIZE, 64, xhci->page_size);
2322
2323 /* See Table 46 and Note on Figure 55 */
2324 xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2325 2112, 64, xhci->page_size);
2326 if (!xhci->segment_pool || !xhci->device_pool)
2327 goto fail;
2328
2329 /* Linear stream context arrays don't have any boundary restrictions,
2330 * and only need to be 16-byte aligned.
2331 */
2332 xhci->small_streams_pool =
2333 dma_pool_create("xHCI 256 byte stream ctx arrays",
2334 dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2335 xhci->medium_streams_pool =
2336 dma_pool_create("xHCI 1KB stream ctx arrays",
2337 dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2338 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2339 * will be allocated with dma_alloc_coherent()
2340 */
2341
2342 if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2343 goto fail;
2344
2345 /* Set up the command ring to have one segments for now. */
2346 xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags);
2347 if (!xhci->cmd_ring)
2348 goto fail;
2349 INIT_LIST_HEAD(&xhci->cancel_cmd_list);
2350 xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
2351 xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
2352 (unsigned long long)xhci->cmd_ring->first_seg->dma);
2353
2354 /* Set the address in the Command Ring Control register */
2355 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2356 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2357 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2358 xhci->cmd_ring->cycle_state;
2359 xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2360 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2361 xhci_dbg_cmd_ptrs(xhci);
2362
2363 xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
2364 if (!xhci->lpm_command)
2365 goto fail;
2366
2367 /* Reserve one command ring TRB for disabling LPM.
2368 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2369 * disabling LPM, we only need to reserve one TRB for all devices.
2370 */
2371 xhci->cmd_ring_reserved_trbs++;
2372
2373 val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2374 val &= DBOFF_MASK;
2375 xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2376 " from cap regs base addr\n", val);
2377 xhci->dba = (void __iomem *) xhci->cap_regs + val;
2378 xhci_dbg_regs(xhci);
2379 xhci_print_run_regs(xhci);
2380 /* Set ir_set to interrupt register set 0 */
2381 xhci->ir_set = &xhci->run_regs->ir_set[0];
2382
2383 /*
2384 * Event ring setup: Allocate a normal ring, but also setup
2385 * the event ring segment table (ERST). Section 4.9.3.
2386 */
2387 xhci_dbg(xhci, "// Allocating event ring\n");
2388 xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2389 flags);
2390 if (!xhci->event_ring)
2391 goto fail;
2392 if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2393 goto fail;
2394
2395 xhci->erst.entries = dma_alloc_coherent(dev,
2396 sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2397 GFP_KERNEL);
2398 if (!xhci->erst.entries)
2399 goto fail;
2400 xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2401 (unsigned long long)dma);
2402
2403 memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2404 xhci->erst.num_entries = ERST_NUM_SEGS;
2405 xhci->erst.erst_dma_addr = dma;
2406 xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2407 xhci->erst.num_entries,
2408 xhci->erst.entries,
2409 (unsigned long long)xhci->erst.erst_dma_addr);
2410
2411 /* set ring base address and size for each segment table entry */
2412 for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2413 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2414 entry->seg_addr = cpu_to_le64(seg->dma);
2415 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2416 entry->rsvd = 0;
2417 seg = seg->next;
2418 }
2419
2420 /* set ERST count with the number of entries in the segment table */
2421 val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2422 val &= ERST_SIZE_MASK;
2423 val |= ERST_NUM_SEGS;
2424 xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2425 val);
2426 xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2427
2428 xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2429 /* set the segment table base address */
2430 xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2431 (unsigned long long)xhci->erst.erst_dma_addr);
2432 val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2433 val_64 &= ERST_PTR_MASK;
2434 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2435 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2436
2437 /* Set the event ring dequeue address */
2438 xhci_set_hc_event_deq(xhci);
2439 xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2440 xhci_print_ir_set(xhci, 0);
2441
2442 /*
2443 * XXX: Might need to set the Interrupter Moderation Register to
2444 * something other than the default (~1ms minimum between interrupts).
2445 * See section 5.5.1.2.
2446 */
2447 init_completion(&xhci->addr_dev);
2448 for (i = 0; i < MAX_HC_SLOTS; ++i)
2449 xhci->devs[i] = NULL;
2450 for (i = 0; i < USB_MAXCHILDREN; ++i) {
2451 xhci->bus_state[0].resume_done[i] = 0;
2452 xhci->bus_state[1].resume_done[i] = 0;
2453 }
2454
2455 if (scratchpad_alloc(xhci, flags))
2456 goto fail;
2457 if (xhci_setup_port_arrays(xhci, flags))
2458 goto fail;
2459
2460 INIT_LIST_HEAD(&xhci->lpm_failed_devs);
2461
2462 /* Enable USB 3.0 device notifications for function remote wake, which
2463 * is necessary for allowing USB 3.0 devices to do remote wakeup from
2464 * U3 (device suspend).
2465 */
2466 temp = xhci_readl(xhci, &xhci->op_regs->dev_notification);
2467 temp &= ~DEV_NOTE_MASK;
2468 temp |= DEV_NOTE_FWAKE;
2469 xhci_writel(xhci, temp, &xhci->op_regs->dev_notification);
2470
2471 return 0;
2472
2473fail:
2474 xhci_warn(xhci, "Couldn't initialize memory\n");
2475 xhci_halt(xhci);
2476 xhci_reset(xhci);
2477 xhci_mem_cleanup(xhci);
2478 return -ENOMEM;
2479}