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1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/gfp.h>
24#include <asm/unaligned.h>
25
26#include "xhci.h"
27#include "xhci-trace.h"
28
29#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
30#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
31 PORT_RC | PORT_PLC | PORT_PE)
32
33/* USB 3.0 BOS descriptor and a capability descriptor, combined */
34static u8 usb_bos_descriptor [] = {
35 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
36 USB_DT_BOS, /* __u8 bDescriptorType */
37 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
38 0x1, /* __u8 bNumDeviceCaps */
39 /* First device capability */
40 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
41 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
42 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
43 0x00, /* bmAttributes, LTM off by default */
44 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
45 0x03, /* bFunctionalitySupport,
46 USB 3.0 speed only */
47 0x00, /* bU1DevExitLat, set later. */
48 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
49};
50
51
52static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
53 struct usb_hub_descriptor *desc, int ports)
54{
55 u16 temp;
56
57 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
58 desc->bHubContrCurrent = 0;
59
60 desc->bNbrPorts = ports;
61 temp = 0;
62 /* Bits 1:0 - support per-port power switching, or power always on */
63 if (HCC_PPC(xhci->hcc_params))
64 temp |= HUB_CHAR_INDV_PORT_LPSM;
65 else
66 temp |= HUB_CHAR_NO_LPSM;
67 /* Bit 2 - root hubs are not part of a compound device */
68 /* Bits 4:3 - individual port over current protection */
69 temp |= HUB_CHAR_INDV_PORT_OCPM;
70 /* Bits 6:5 - no TTs in root ports */
71 /* Bit 7 - no port indicators */
72 desc->wHubCharacteristics = cpu_to_le16(temp);
73}
74
75/* Fill in the USB 2.0 roothub descriptor */
76static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
77 struct usb_hub_descriptor *desc)
78{
79 int ports;
80 u16 temp;
81 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
82 u32 portsc;
83 unsigned int i;
84
85 ports = xhci->num_usb2_ports;
86
87 xhci_common_hub_descriptor(xhci, desc, ports);
88 desc->bDescriptorType = USB_DT_HUB;
89 temp = 1 + (ports / 8);
90 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
91
92 /* The Device Removable bits are reported on a byte granularity.
93 * If the port doesn't exist within that byte, the bit is set to 0.
94 */
95 memset(port_removable, 0, sizeof(port_removable));
96 for (i = 0; i < ports; i++) {
97 portsc = readl(xhci->usb2_ports[i]);
98 /* If a device is removable, PORTSC reports a 0, same as in the
99 * hub descriptor DeviceRemovable bits.
100 */
101 if (portsc & PORT_DEV_REMOVE)
102 /* This math is hairy because bit 0 of DeviceRemovable
103 * is reserved, and bit 1 is for port 1, etc.
104 */
105 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
106 }
107
108 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
109 * ports on it. The USB 2.0 specification says that there are two
110 * variable length fields at the end of the hub descriptor:
111 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
112 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
113 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
114 * 0xFF, so we initialize the both arrays (DeviceRemovable and
115 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
116 * set of ports that actually exist.
117 */
118 memset(desc->u.hs.DeviceRemovable, 0xff,
119 sizeof(desc->u.hs.DeviceRemovable));
120 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
121 sizeof(desc->u.hs.PortPwrCtrlMask));
122
123 for (i = 0; i < (ports + 1 + 7) / 8; i++)
124 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
125 sizeof(__u8));
126}
127
128/* Fill in the USB 3.0 roothub descriptor */
129static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
130 struct usb_hub_descriptor *desc)
131{
132 int ports;
133 u16 port_removable;
134 u32 portsc;
135 unsigned int i;
136
137 ports = xhci->num_usb3_ports;
138 xhci_common_hub_descriptor(xhci, desc, ports);
139 desc->bDescriptorType = USB_DT_SS_HUB;
140 desc->bDescLength = USB_DT_SS_HUB_SIZE;
141
142 /* header decode latency should be zero for roothubs,
143 * see section 4.23.5.2.
144 */
145 desc->u.ss.bHubHdrDecLat = 0;
146 desc->u.ss.wHubDelay = 0;
147
148 port_removable = 0;
149 /* bit 0 is reserved, bit 1 is for port 1, etc. */
150 for (i = 0; i < ports; i++) {
151 portsc = readl(xhci->usb3_ports[i]);
152 if (portsc & PORT_DEV_REMOVE)
153 port_removable |= 1 << (i + 1);
154 }
155
156 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
157}
158
159static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
160 struct usb_hub_descriptor *desc)
161{
162
163 if (hcd->speed == HCD_USB3)
164 xhci_usb3_hub_descriptor(hcd, xhci, desc);
165 else
166 xhci_usb2_hub_descriptor(hcd, xhci, desc);
167
168}
169
170static unsigned int xhci_port_speed(unsigned int port_status)
171{
172 if (DEV_LOWSPEED(port_status))
173 return USB_PORT_STAT_LOW_SPEED;
174 if (DEV_HIGHSPEED(port_status))
175 return USB_PORT_STAT_HIGH_SPEED;
176 /*
177 * FIXME: Yes, we should check for full speed, but the core uses that as
178 * a default in portspeed() in usb/core/hub.c (which is the only place
179 * USB_PORT_STAT_*_SPEED is used).
180 */
181 return 0;
182}
183
184/*
185 * These bits are Read Only (RO) and should be saved and written to the
186 * registers: 0, 3, 10:13, 30
187 * connect status, over-current status, port speed, and device removable.
188 * connect status and port speed are also sticky - meaning they're in
189 * the AUX well and they aren't changed by a hot, warm, or cold reset.
190 */
191#define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
192/*
193 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
194 * bits 5:8, 9, 14:15, 25:27
195 * link state, port power, port indicator state, "wake on" enable state
196 */
197#define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
198/*
199 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
200 * bit 4 (port reset)
201 */
202#define XHCI_PORT_RW1S ((1<<4))
203/*
204 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
205 * bits 1, 17, 18, 19, 20, 21, 22, 23
206 * port enable/disable, and
207 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
208 * over-current, reset, link state, and L1 change
209 */
210#define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
211/*
212 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
213 * latched in
214 */
215#define XHCI_PORT_RW ((1<<16))
216/*
217 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
218 * bits 2, 24, 28:31
219 */
220#define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
221
222/*
223 * Given a port state, this function returns a value that would result in the
224 * port being in the same state, if the value was written to the port status
225 * control register.
226 * Save Read Only (RO) bits and save read/write bits where
227 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
228 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
229 */
230u32 xhci_port_state_to_neutral(u32 state)
231{
232 /* Save read-only status and port state */
233 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
234}
235
236/*
237 * find slot id based on port number.
238 * @port: The one-based port number from one of the two split roothubs.
239 */
240int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
241 u16 port)
242{
243 int slot_id;
244 int i;
245 enum usb_device_speed speed;
246
247 slot_id = 0;
248 for (i = 0; i < MAX_HC_SLOTS; i++) {
249 if (!xhci->devs[i])
250 continue;
251 speed = xhci->devs[i]->udev->speed;
252 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
253 && xhci->devs[i]->fake_port == port) {
254 slot_id = i;
255 break;
256 }
257 }
258
259 return slot_id;
260}
261
262/*
263 * Stop device
264 * It issues stop endpoint command for EP 0 to 30. And wait the last command
265 * to complete.
266 * suspend will set to 1, if suspend bit need to set in command.
267 */
268static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
269{
270 struct xhci_virt_device *virt_dev;
271 struct xhci_command *cmd;
272 unsigned long flags;
273 int timeleft;
274 int ret;
275 int i;
276
277 ret = 0;
278 virt_dev = xhci->devs[slot_id];
279 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
280 if (!cmd) {
281 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
282 return -ENOMEM;
283 }
284
285 spin_lock_irqsave(&xhci->lock, flags);
286 for (i = LAST_EP_INDEX; i > 0; i--) {
287 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
288 xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
289 }
290 cmd->command_trb = xhci_find_next_enqueue(xhci->cmd_ring);
291 list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
292 xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
293 xhci_ring_cmd_db(xhci);
294 spin_unlock_irqrestore(&xhci->lock, flags);
295
296 /* Wait for last stop endpoint command to finish */
297 timeleft = wait_for_completion_interruptible_timeout(
298 cmd->completion,
299 XHCI_CMD_DEFAULT_TIMEOUT);
300 if (timeleft <= 0) {
301 xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
302 timeleft == 0 ? "Timeout" : "Signal");
303 spin_lock_irqsave(&xhci->lock, flags);
304 /* The timeout might have raced with the event ring handler, so
305 * only delete from the list if the item isn't poisoned.
306 */
307 if (cmd->cmd_list.next != LIST_POISON1)
308 list_del(&cmd->cmd_list);
309 spin_unlock_irqrestore(&xhci->lock, flags);
310 ret = -ETIME;
311 goto command_cleanup;
312 }
313
314command_cleanup:
315 xhci_free_command(xhci, cmd);
316 return ret;
317}
318
319/*
320 * Ring device, it rings the all doorbells unconditionally.
321 */
322void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
323{
324 int i;
325
326 for (i = 0; i < LAST_EP_INDEX + 1; i++)
327 if (xhci->devs[slot_id]->eps[i].ring &&
328 xhci->devs[slot_id]->eps[i].ring->dequeue)
329 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
330
331 return;
332}
333
334static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
335 u16 wIndex, __le32 __iomem *addr, u32 port_status)
336{
337 /* Don't allow the USB core to disable SuperSpeed ports. */
338 if (hcd->speed == HCD_USB3) {
339 xhci_dbg(xhci, "Ignoring request to disable "
340 "SuperSpeed port.\n");
341 return;
342 }
343
344 /* Write 1 to disable the port */
345 writel(port_status | PORT_PE, addr);
346 port_status = readl(addr);
347 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
348 wIndex, port_status);
349}
350
351static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
352 u16 wIndex, __le32 __iomem *addr, u32 port_status)
353{
354 char *port_change_bit;
355 u32 status;
356
357 switch (wValue) {
358 case USB_PORT_FEAT_C_RESET:
359 status = PORT_RC;
360 port_change_bit = "reset";
361 break;
362 case USB_PORT_FEAT_C_BH_PORT_RESET:
363 status = PORT_WRC;
364 port_change_bit = "warm(BH) reset";
365 break;
366 case USB_PORT_FEAT_C_CONNECTION:
367 status = PORT_CSC;
368 port_change_bit = "connect";
369 break;
370 case USB_PORT_FEAT_C_OVER_CURRENT:
371 status = PORT_OCC;
372 port_change_bit = "over-current";
373 break;
374 case USB_PORT_FEAT_C_ENABLE:
375 status = PORT_PEC;
376 port_change_bit = "enable/disable";
377 break;
378 case USB_PORT_FEAT_C_SUSPEND:
379 status = PORT_PLC;
380 port_change_bit = "suspend/resume";
381 break;
382 case USB_PORT_FEAT_C_PORT_LINK_STATE:
383 status = PORT_PLC;
384 port_change_bit = "link state";
385 break;
386 default:
387 /* Should never happen */
388 return;
389 }
390 /* Change bits are all write 1 to clear */
391 writel(port_status | status, addr);
392 port_status = readl(addr);
393 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
394 port_change_bit, wIndex, port_status);
395}
396
397static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
398{
399 int max_ports;
400 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
401
402 if (hcd->speed == HCD_USB3) {
403 max_ports = xhci->num_usb3_ports;
404 *port_array = xhci->usb3_ports;
405 } else {
406 max_ports = xhci->num_usb2_ports;
407 *port_array = xhci->usb2_ports;
408 }
409
410 return max_ports;
411}
412
413void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
414 int port_id, u32 link_state)
415{
416 u32 temp;
417
418 temp = readl(port_array[port_id]);
419 temp = xhci_port_state_to_neutral(temp);
420 temp &= ~PORT_PLS_MASK;
421 temp |= PORT_LINK_STROBE | link_state;
422 writel(temp, port_array[port_id]);
423}
424
425static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
426 __le32 __iomem **port_array, int port_id, u16 wake_mask)
427{
428 u32 temp;
429
430 temp = readl(port_array[port_id]);
431 temp = xhci_port_state_to_neutral(temp);
432
433 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
434 temp |= PORT_WKCONN_E;
435 else
436 temp &= ~PORT_WKCONN_E;
437
438 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
439 temp |= PORT_WKDISC_E;
440 else
441 temp &= ~PORT_WKDISC_E;
442
443 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
444 temp |= PORT_WKOC_E;
445 else
446 temp &= ~PORT_WKOC_E;
447
448 writel(temp, port_array[port_id]);
449}
450
451/* Test and clear port RWC bit */
452void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
453 int port_id, u32 port_bit)
454{
455 u32 temp;
456
457 temp = readl(port_array[port_id]);
458 if (temp & port_bit) {
459 temp = xhci_port_state_to_neutral(temp);
460 temp |= port_bit;
461 writel(temp, port_array[port_id]);
462 }
463}
464
465/* Updates Link Status for USB 2.1 port */
466static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
467{
468 if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
469 *status |= USB_PORT_STAT_L1;
470}
471
472/* Updates Link Status for super Speed port */
473static void xhci_hub_report_usb3_link_state(u32 *status, u32 status_reg)
474{
475 u32 pls = status_reg & PORT_PLS_MASK;
476
477 /* resume state is a xHCI internal state.
478 * Do not report it to usb core.
479 */
480 if (pls == XDEV_RESUME)
481 return;
482
483 /* When the CAS bit is set then warm reset
484 * should be performed on port
485 */
486 if (status_reg & PORT_CAS) {
487 /* The CAS bit can be set while the port is
488 * in any link state.
489 * Only roothubs have CAS bit, so we
490 * pretend to be in compliance mode
491 * unless we're already in compliance
492 * or the inactive state.
493 */
494 if (pls != USB_SS_PORT_LS_COMP_MOD &&
495 pls != USB_SS_PORT_LS_SS_INACTIVE) {
496 pls = USB_SS_PORT_LS_COMP_MOD;
497 }
498 /* Return also connection bit -
499 * hub state machine resets port
500 * when this bit is set.
501 */
502 pls |= USB_PORT_STAT_CONNECTION;
503 } else {
504 /*
505 * If CAS bit isn't set but the Port is already at
506 * Compliance Mode, fake a connection so the USB core
507 * notices the Compliance state and resets the port.
508 * This resolves an issue generated by the SN65LVPE502CP
509 * in which sometimes the port enters compliance mode
510 * caused by a delay on the host-device negotiation.
511 */
512 if (pls == USB_SS_PORT_LS_COMP_MOD)
513 pls |= USB_PORT_STAT_CONNECTION;
514 }
515
516 /* update status field */
517 *status |= pls;
518}
519
520/*
521 * Function for Compliance Mode Quirk.
522 *
523 * This Function verifies if all xhc USB3 ports have entered U0, if so,
524 * the compliance mode timer is deleted. A port won't enter
525 * compliance mode if it has previously entered U0.
526 */
527static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
528 u16 wIndex)
529{
530 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
531 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
532
533 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
534 return;
535
536 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
537 xhci->port_status_u0 |= 1 << wIndex;
538 if (xhci->port_status_u0 == all_ports_seen_u0) {
539 del_timer_sync(&xhci->comp_mode_recovery_timer);
540 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
541 "All USB3 ports have entered U0 already!");
542 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
543 "Compliance Mode Recovery Timer Deleted.");
544 }
545 }
546}
547
548/*
549 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
550 * 3.0 hubs use.
551 *
552 * Possible side effects:
553 * - Mark a port as being done with device resume,
554 * and ring the endpoint doorbells.
555 * - Stop the Synopsys redriver Compliance Mode polling.
556 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
557 */
558static u32 xhci_get_port_status(struct usb_hcd *hcd,
559 struct xhci_bus_state *bus_state,
560 __le32 __iomem **port_array,
561 u16 wIndex, u32 raw_port_status,
562 unsigned long flags)
563 __releases(&xhci->lock)
564 __acquires(&xhci->lock)
565{
566 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
567 u32 status = 0;
568 int slot_id;
569
570 /* wPortChange bits */
571 if (raw_port_status & PORT_CSC)
572 status |= USB_PORT_STAT_C_CONNECTION << 16;
573 if (raw_port_status & PORT_PEC)
574 status |= USB_PORT_STAT_C_ENABLE << 16;
575 if ((raw_port_status & PORT_OCC))
576 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
577 if ((raw_port_status & PORT_RC))
578 status |= USB_PORT_STAT_C_RESET << 16;
579 /* USB3.0 only */
580 if (hcd->speed == HCD_USB3) {
581 if ((raw_port_status & PORT_PLC))
582 status |= USB_PORT_STAT_C_LINK_STATE << 16;
583 if ((raw_port_status & PORT_WRC))
584 status |= USB_PORT_STAT_C_BH_RESET << 16;
585 }
586
587 if (hcd->speed != HCD_USB3) {
588 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
589 && (raw_port_status & PORT_POWER))
590 status |= USB_PORT_STAT_SUSPEND;
591 }
592 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
593 !DEV_SUPERSPEED(raw_port_status)) {
594 if ((raw_port_status & PORT_RESET) ||
595 !(raw_port_status & PORT_PE))
596 return 0xffffffff;
597 if (time_after_eq(jiffies,
598 bus_state->resume_done[wIndex])) {
599 int time_left;
600
601 xhci_dbg(xhci, "Resume USB2 port %d\n",
602 wIndex + 1);
603 bus_state->resume_done[wIndex] = 0;
604 clear_bit(wIndex, &bus_state->resuming_ports);
605
606 set_bit(wIndex, &bus_state->rexit_ports);
607 xhci_set_link_state(xhci, port_array, wIndex,
608 XDEV_U0);
609
610 spin_unlock_irqrestore(&xhci->lock, flags);
611 time_left = wait_for_completion_timeout(
612 &bus_state->rexit_done[wIndex],
613 msecs_to_jiffies(
614 XHCI_MAX_REXIT_TIMEOUT));
615 spin_lock_irqsave(&xhci->lock, flags);
616
617 if (time_left) {
618 slot_id = xhci_find_slot_id_by_port(hcd,
619 xhci, wIndex + 1);
620 if (!slot_id) {
621 xhci_dbg(xhci, "slot_id is zero\n");
622 return 0xffffffff;
623 }
624 xhci_ring_device(xhci, slot_id);
625 } else {
626 int port_status = readl(port_array[wIndex]);
627 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
628 XHCI_MAX_REXIT_TIMEOUT,
629 port_status);
630 status |= USB_PORT_STAT_SUSPEND;
631 clear_bit(wIndex, &bus_state->rexit_ports);
632 }
633
634 bus_state->port_c_suspend |= 1 << wIndex;
635 bus_state->suspended_ports &= ~(1 << wIndex);
636 } else {
637 /*
638 * The resume has been signaling for less than
639 * 20ms. Report the port status as SUSPEND,
640 * let the usbcore check port status again
641 * and clear resume signaling later.
642 */
643 status |= USB_PORT_STAT_SUSPEND;
644 }
645 }
646 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0
647 && (raw_port_status & PORT_POWER)
648 && (bus_state->suspended_ports & (1 << wIndex))) {
649 bus_state->suspended_ports &= ~(1 << wIndex);
650 if (hcd->speed != HCD_USB3)
651 bus_state->port_c_suspend |= 1 << wIndex;
652 }
653 if (raw_port_status & PORT_CONNECT) {
654 status |= USB_PORT_STAT_CONNECTION;
655 status |= xhci_port_speed(raw_port_status);
656 }
657 if (raw_port_status & PORT_PE)
658 status |= USB_PORT_STAT_ENABLE;
659 if (raw_port_status & PORT_OC)
660 status |= USB_PORT_STAT_OVERCURRENT;
661 if (raw_port_status & PORT_RESET)
662 status |= USB_PORT_STAT_RESET;
663 if (raw_port_status & PORT_POWER) {
664 if (hcd->speed == HCD_USB3)
665 status |= USB_SS_PORT_STAT_POWER;
666 else
667 status |= USB_PORT_STAT_POWER;
668 }
669 /* Update Port Link State */
670 if (hcd->speed == HCD_USB3) {
671 xhci_hub_report_usb3_link_state(&status, raw_port_status);
672 /*
673 * Verify if all USB3 Ports Have entered U0 already.
674 * Delete Compliance Mode Timer if so.
675 */
676 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
677 } else {
678 xhci_hub_report_usb2_link_state(&status, raw_port_status);
679 }
680 if (bus_state->port_c_suspend & (1 << wIndex))
681 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
682
683 return status;
684}
685
686int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
687 u16 wIndex, char *buf, u16 wLength)
688{
689 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
690 int max_ports;
691 unsigned long flags;
692 u32 temp, status;
693 int retval = 0;
694 __le32 __iomem **port_array;
695 int slot_id;
696 struct xhci_bus_state *bus_state;
697 u16 link_state = 0;
698 u16 wake_mask = 0;
699 u16 timeout = 0;
700
701 max_ports = xhci_get_ports(hcd, &port_array);
702 bus_state = &xhci->bus_state[hcd_index(hcd)];
703
704 spin_lock_irqsave(&xhci->lock, flags);
705 switch (typeReq) {
706 case GetHubStatus:
707 /* No power source, over-current reported per port */
708 memset(buf, 0, 4);
709 break;
710 case GetHubDescriptor:
711 /* Check to make sure userspace is asking for the USB 3.0 hub
712 * descriptor for the USB 3.0 roothub. If not, we stall the
713 * endpoint, like external hubs do.
714 */
715 if (hcd->speed == HCD_USB3 &&
716 (wLength < USB_DT_SS_HUB_SIZE ||
717 wValue != (USB_DT_SS_HUB << 8))) {
718 xhci_dbg(xhci, "Wrong hub descriptor type for "
719 "USB 3.0 roothub.\n");
720 goto error;
721 }
722 xhci_hub_descriptor(hcd, xhci,
723 (struct usb_hub_descriptor *) buf);
724 break;
725 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
726 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
727 goto error;
728
729 if (hcd->speed != HCD_USB3)
730 goto error;
731
732 /* Set the U1 and U2 exit latencies. */
733 memcpy(buf, &usb_bos_descriptor,
734 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
735 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
736 temp = readl(&xhci->cap_regs->hcs_params3);
737 buf[12] = HCS_U1_LATENCY(temp);
738 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
739 }
740
741 /* Indicate whether the host has LTM support. */
742 temp = readl(&xhci->cap_regs->hcc_params);
743 if (HCC_LTC(temp))
744 buf[8] |= USB_LTM_SUPPORT;
745
746 spin_unlock_irqrestore(&xhci->lock, flags);
747 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
748 case GetPortStatus:
749 if (!wIndex || wIndex > max_ports)
750 goto error;
751 wIndex--;
752 temp = readl(port_array[wIndex]);
753 if (temp == 0xffffffff) {
754 retval = -ENODEV;
755 break;
756 }
757 status = xhci_get_port_status(hcd, bus_state, port_array,
758 wIndex, temp, flags);
759 if (status == 0xffffffff)
760 goto error;
761
762 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
763 wIndex, temp);
764 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
765
766 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
767 break;
768 case SetPortFeature:
769 if (wValue == USB_PORT_FEAT_LINK_STATE)
770 link_state = (wIndex & 0xff00) >> 3;
771 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
772 wake_mask = wIndex & 0xff00;
773 /* The MSB of wIndex is the U1/U2 timeout */
774 timeout = (wIndex & 0xff00) >> 8;
775 wIndex &= 0xff;
776 if (!wIndex || wIndex > max_ports)
777 goto error;
778 wIndex--;
779 temp = readl(port_array[wIndex]);
780 if (temp == 0xffffffff) {
781 retval = -ENODEV;
782 break;
783 }
784 temp = xhci_port_state_to_neutral(temp);
785 /* FIXME: What new port features do we need to support? */
786 switch (wValue) {
787 case USB_PORT_FEAT_SUSPEND:
788 temp = readl(port_array[wIndex]);
789 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
790 /* Resume the port to U0 first */
791 xhci_set_link_state(xhci, port_array, wIndex,
792 XDEV_U0);
793 spin_unlock_irqrestore(&xhci->lock, flags);
794 msleep(10);
795 spin_lock_irqsave(&xhci->lock, flags);
796 }
797 /* In spec software should not attempt to suspend
798 * a port unless the port reports that it is in the
799 * enabled (PED = ‘1’,PLS < ‘3’) state.
800 */
801 temp = readl(port_array[wIndex]);
802 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
803 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
804 xhci_warn(xhci, "USB core suspending device "
805 "not in U0/U1/U2.\n");
806 goto error;
807 }
808
809 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
810 wIndex + 1);
811 if (!slot_id) {
812 xhci_warn(xhci, "slot_id is zero\n");
813 goto error;
814 }
815 /* unlock to execute stop endpoint commands */
816 spin_unlock_irqrestore(&xhci->lock, flags);
817 xhci_stop_device(xhci, slot_id, 1);
818 spin_lock_irqsave(&xhci->lock, flags);
819
820 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
821
822 spin_unlock_irqrestore(&xhci->lock, flags);
823 msleep(10); /* wait device to enter */
824 spin_lock_irqsave(&xhci->lock, flags);
825
826 temp = readl(port_array[wIndex]);
827 bus_state->suspended_ports |= 1 << wIndex;
828 break;
829 case USB_PORT_FEAT_LINK_STATE:
830 temp = readl(port_array[wIndex]);
831
832 /* Disable port */
833 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
834 xhci_dbg(xhci, "Disable port %d\n", wIndex);
835 temp = xhci_port_state_to_neutral(temp);
836 /*
837 * Clear all change bits, so that we get a new
838 * connection event.
839 */
840 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
841 PORT_OCC | PORT_RC | PORT_PLC |
842 PORT_CEC;
843 writel(temp | PORT_PE, port_array[wIndex]);
844 temp = readl(port_array[wIndex]);
845 break;
846 }
847
848 /* Put link in RxDetect (enable port) */
849 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
850 xhci_dbg(xhci, "Enable port %d\n", wIndex);
851 xhci_set_link_state(xhci, port_array, wIndex,
852 link_state);
853 temp = readl(port_array[wIndex]);
854 break;
855 }
856
857 /* Software should not attempt to set
858 * port link state above '3' (U3) and the port
859 * must be enabled.
860 */
861 if ((temp & PORT_PE) == 0 ||
862 (link_state > USB_SS_PORT_LS_U3)) {
863 xhci_warn(xhci, "Cannot set link state.\n");
864 goto error;
865 }
866
867 if (link_state == USB_SS_PORT_LS_U3) {
868 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
869 wIndex + 1);
870 if (slot_id) {
871 /* unlock to execute stop endpoint
872 * commands */
873 spin_unlock_irqrestore(&xhci->lock,
874 flags);
875 xhci_stop_device(xhci, slot_id, 1);
876 spin_lock_irqsave(&xhci->lock, flags);
877 }
878 }
879
880 xhci_set_link_state(xhci, port_array, wIndex,
881 link_state);
882
883 spin_unlock_irqrestore(&xhci->lock, flags);
884 msleep(20); /* wait device to enter */
885 spin_lock_irqsave(&xhci->lock, flags);
886
887 temp = readl(port_array[wIndex]);
888 if (link_state == USB_SS_PORT_LS_U3)
889 bus_state->suspended_ports |= 1 << wIndex;
890 break;
891 case USB_PORT_FEAT_POWER:
892 /*
893 * Turn on ports, even if there isn't per-port switching.
894 * HC will report connect events even before this is set.
895 * However, khubd will ignore the roothub events until
896 * the roothub is registered.
897 */
898 writel(temp | PORT_POWER, port_array[wIndex]);
899
900 temp = readl(port_array[wIndex]);
901 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
902
903 spin_unlock_irqrestore(&xhci->lock, flags);
904 temp = usb_acpi_power_manageable(hcd->self.root_hub,
905 wIndex);
906 if (temp)
907 usb_acpi_set_power_state(hcd->self.root_hub,
908 wIndex, true);
909 spin_lock_irqsave(&xhci->lock, flags);
910 break;
911 case USB_PORT_FEAT_RESET:
912 temp = (temp | PORT_RESET);
913 writel(temp, port_array[wIndex]);
914
915 temp = readl(port_array[wIndex]);
916 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
917 break;
918 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
919 xhci_set_remote_wake_mask(xhci, port_array,
920 wIndex, wake_mask);
921 temp = readl(port_array[wIndex]);
922 xhci_dbg(xhci, "set port remote wake mask, "
923 "actual port %d status = 0x%x\n",
924 wIndex, temp);
925 break;
926 case USB_PORT_FEAT_BH_PORT_RESET:
927 temp |= PORT_WR;
928 writel(temp, port_array[wIndex]);
929
930 temp = readl(port_array[wIndex]);
931 break;
932 case USB_PORT_FEAT_U1_TIMEOUT:
933 if (hcd->speed != HCD_USB3)
934 goto error;
935 temp = readl(port_array[wIndex] + PORTPMSC);
936 temp &= ~PORT_U1_TIMEOUT_MASK;
937 temp |= PORT_U1_TIMEOUT(timeout);
938 writel(temp, port_array[wIndex] + PORTPMSC);
939 break;
940 case USB_PORT_FEAT_U2_TIMEOUT:
941 if (hcd->speed != HCD_USB3)
942 goto error;
943 temp = readl(port_array[wIndex] + PORTPMSC);
944 temp &= ~PORT_U2_TIMEOUT_MASK;
945 temp |= PORT_U2_TIMEOUT(timeout);
946 writel(temp, port_array[wIndex] + PORTPMSC);
947 break;
948 default:
949 goto error;
950 }
951 /* unblock any posted writes */
952 temp = readl(port_array[wIndex]);
953 break;
954 case ClearPortFeature:
955 if (!wIndex || wIndex > max_ports)
956 goto error;
957 wIndex--;
958 temp = readl(port_array[wIndex]);
959 if (temp == 0xffffffff) {
960 retval = -ENODEV;
961 break;
962 }
963 /* FIXME: What new port features do we need to support? */
964 temp = xhci_port_state_to_neutral(temp);
965 switch (wValue) {
966 case USB_PORT_FEAT_SUSPEND:
967 temp = readl(port_array[wIndex]);
968 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
969 xhci_dbg(xhci, "PORTSC %04x\n", temp);
970 if (temp & PORT_RESET)
971 goto error;
972 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
973 if ((temp & PORT_PE) == 0)
974 goto error;
975
976 xhci_set_link_state(xhci, port_array, wIndex,
977 XDEV_RESUME);
978 spin_unlock_irqrestore(&xhci->lock, flags);
979 msleep(20);
980 spin_lock_irqsave(&xhci->lock, flags);
981 xhci_set_link_state(xhci, port_array, wIndex,
982 XDEV_U0);
983 }
984 bus_state->port_c_suspend |= 1 << wIndex;
985
986 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
987 wIndex + 1);
988 if (!slot_id) {
989 xhci_dbg(xhci, "slot_id is zero\n");
990 goto error;
991 }
992 xhci_ring_device(xhci, slot_id);
993 break;
994 case USB_PORT_FEAT_C_SUSPEND:
995 bus_state->port_c_suspend &= ~(1 << wIndex);
996 case USB_PORT_FEAT_C_RESET:
997 case USB_PORT_FEAT_C_BH_PORT_RESET:
998 case USB_PORT_FEAT_C_CONNECTION:
999 case USB_PORT_FEAT_C_OVER_CURRENT:
1000 case USB_PORT_FEAT_C_ENABLE:
1001 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1002 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1003 port_array[wIndex], temp);
1004 break;
1005 case USB_PORT_FEAT_ENABLE:
1006 xhci_disable_port(hcd, xhci, wIndex,
1007 port_array[wIndex], temp);
1008 break;
1009 case USB_PORT_FEAT_POWER:
1010 writel(temp & ~PORT_POWER, port_array[wIndex]);
1011
1012 spin_unlock_irqrestore(&xhci->lock, flags);
1013 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1014 wIndex);
1015 if (temp)
1016 usb_acpi_set_power_state(hcd->self.root_hub,
1017 wIndex, false);
1018 spin_lock_irqsave(&xhci->lock, flags);
1019 break;
1020 default:
1021 goto error;
1022 }
1023 break;
1024 default:
1025error:
1026 /* "stall" on error */
1027 retval = -EPIPE;
1028 }
1029 spin_unlock_irqrestore(&xhci->lock, flags);
1030 return retval;
1031}
1032
1033/*
1034 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1035 * Ports are 0-indexed from the HCD point of view,
1036 * and 1-indexed from the USB core pointer of view.
1037 *
1038 * Note that the status change bits will be cleared as soon as a port status
1039 * change event is generated, so we use the saved status from that event.
1040 */
1041int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1042{
1043 unsigned long flags;
1044 u32 temp, status;
1045 u32 mask;
1046 int i, retval;
1047 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1048 int max_ports;
1049 __le32 __iomem **port_array;
1050 struct xhci_bus_state *bus_state;
1051 bool reset_change = false;
1052
1053 max_ports = xhci_get_ports(hcd, &port_array);
1054 bus_state = &xhci->bus_state[hcd_index(hcd)];
1055
1056 /* Initial status is no changes */
1057 retval = (max_ports + 8) / 8;
1058 memset(buf, 0, retval);
1059
1060 /*
1061 * Inform the usbcore about resume-in-progress by returning
1062 * a non-zero value even if there are no status changes.
1063 */
1064 status = bus_state->resuming_ports;
1065
1066 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
1067
1068 spin_lock_irqsave(&xhci->lock, flags);
1069 /* For each port, did anything change? If so, set that bit in buf. */
1070 for (i = 0; i < max_ports; i++) {
1071 temp = readl(port_array[i]);
1072 if (temp == 0xffffffff) {
1073 retval = -ENODEV;
1074 break;
1075 }
1076 if ((temp & mask) != 0 ||
1077 (bus_state->port_c_suspend & 1 << i) ||
1078 (bus_state->resume_done[i] && time_after_eq(
1079 jiffies, bus_state->resume_done[i]))) {
1080 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1081 status = 1;
1082 }
1083 if ((temp & PORT_RC))
1084 reset_change = true;
1085 }
1086 if (!status && !reset_change) {
1087 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1088 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1089 }
1090 spin_unlock_irqrestore(&xhci->lock, flags);
1091 return status ? retval : 0;
1092}
1093
1094#ifdef CONFIG_PM
1095
1096int xhci_bus_suspend(struct usb_hcd *hcd)
1097{
1098 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1099 int max_ports, port_index;
1100 __le32 __iomem **port_array;
1101 struct xhci_bus_state *bus_state;
1102 unsigned long flags;
1103
1104 max_ports = xhci_get_ports(hcd, &port_array);
1105 bus_state = &xhci->bus_state[hcd_index(hcd)];
1106
1107 spin_lock_irqsave(&xhci->lock, flags);
1108
1109 if (hcd->self.root_hub->do_remote_wakeup) {
1110 if (bus_state->resuming_ports) {
1111 spin_unlock_irqrestore(&xhci->lock, flags);
1112 xhci_dbg(xhci, "suspend failed because "
1113 "a port is resuming\n");
1114 return -EBUSY;
1115 }
1116 }
1117
1118 port_index = max_ports;
1119 bus_state->bus_suspended = 0;
1120 while (port_index--) {
1121 /* suspend the port if the port is not suspended */
1122 u32 t1, t2;
1123 int slot_id;
1124
1125 t1 = readl(port_array[port_index]);
1126 t2 = xhci_port_state_to_neutral(t1);
1127
1128 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1129 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1130 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1131 port_index + 1);
1132 if (slot_id) {
1133 spin_unlock_irqrestore(&xhci->lock, flags);
1134 xhci_stop_device(xhci, slot_id, 1);
1135 spin_lock_irqsave(&xhci->lock, flags);
1136 }
1137 t2 &= ~PORT_PLS_MASK;
1138 t2 |= PORT_LINK_STROBE | XDEV_U3;
1139 set_bit(port_index, &bus_state->bus_suspended);
1140 }
1141 /* USB core sets remote wake mask for USB 3.0 hubs,
1142 * including the USB 3.0 roothub, but only if CONFIG_PM_RUNTIME
1143 * is enabled, so also enable remote wake here.
1144 */
1145 if (hcd->self.root_hub->do_remote_wakeup) {
1146 if (t1 & PORT_CONNECT) {
1147 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1148 t2 &= ~PORT_WKCONN_E;
1149 } else {
1150 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1151 t2 &= ~PORT_WKDISC_E;
1152 }
1153 } else
1154 t2 &= ~PORT_WAKE_BITS;
1155
1156 t1 = xhci_port_state_to_neutral(t1);
1157 if (t1 != t2)
1158 writel(t2, port_array[port_index]);
1159 }
1160 hcd->state = HC_STATE_SUSPENDED;
1161 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1162 spin_unlock_irqrestore(&xhci->lock, flags);
1163 return 0;
1164}
1165
1166int xhci_bus_resume(struct usb_hcd *hcd)
1167{
1168 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1169 int max_ports, port_index;
1170 __le32 __iomem **port_array;
1171 struct xhci_bus_state *bus_state;
1172 u32 temp;
1173 unsigned long flags;
1174
1175 max_ports = xhci_get_ports(hcd, &port_array);
1176 bus_state = &xhci->bus_state[hcd_index(hcd)];
1177
1178 if (time_before(jiffies, bus_state->next_statechange))
1179 msleep(5);
1180
1181 spin_lock_irqsave(&xhci->lock, flags);
1182 if (!HCD_HW_ACCESSIBLE(hcd)) {
1183 spin_unlock_irqrestore(&xhci->lock, flags);
1184 return -ESHUTDOWN;
1185 }
1186
1187 /* delay the irqs */
1188 temp = readl(&xhci->op_regs->command);
1189 temp &= ~CMD_EIE;
1190 writel(temp, &xhci->op_regs->command);
1191
1192 port_index = max_ports;
1193 while (port_index--) {
1194 /* Check whether need resume ports. If needed
1195 resume port and disable remote wakeup */
1196 u32 temp;
1197 int slot_id;
1198
1199 temp = readl(port_array[port_index]);
1200 if (DEV_SUPERSPEED(temp))
1201 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1202 else
1203 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1204 if (test_bit(port_index, &bus_state->bus_suspended) &&
1205 (temp & PORT_PLS_MASK)) {
1206 if (DEV_SUPERSPEED(temp)) {
1207 xhci_set_link_state(xhci, port_array,
1208 port_index, XDEV_U0);
1209 } else {
1210 xhci_set_link_state(xhci, port_array,
1211 port_index, XDEV_RESUME);
1212
1213 spin_unlock_irqrestore(&xhci->lock, flags);
1214 msleep(20);
1215 spin_lock_irqsave(&xhci->lock, flags);
1216
1217 xhci_set_link_state(xhci, port_array,
1218 port_index, XDEV_U0);
1219 }
1220 /* wait for the port to enter U0 and report port link
1221 * state change.
1222 */
1223 spin_unlock_irqrestore(&xhci->lock, flags);
1224 msleep(20);
1225 spin_lock_irqsave(&xhci->lock, flags);
1226
1227 /* Clear PLC */
1228 xhci_test_and_clear_bit(xhci, port_array, port_index,
1229 PORT_PLC);
1230
1231 slot_id = xhci_find_slot_id_by_port(hcd,
1232 xhci, port_index + 1);
1233 if (slot_id)
1234 xhci_ring_device(xhci, slot_id);
1235 } else
1236 writel(temp, port_array[port_index]);
1237 }
1238
1239 (void) readl(&xhci->op_regs->command);
1240
1241 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1242 /* re-enable irqs */
1243 temp = readl(&xhci->op_regs->command);
1244 temp |= CMD_EIE;
1245 writel(temp, &xhci->op_regs->command);
1246 temp = readl(&xhci->op_regs->command);
1247
1248 spin_unlock_irqrestore(&xhci->lock, flags);
1249 return 0;
1250}
1251
1252#endif /* CONFIG_PM */
1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/gfp.h>
24#include <asm/unaligned.h>
25
26#include "xhci.h"
27
28#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
29#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
30 PORT_RC | PORT_PLC | PORT_PE)
31
32/* usb 1.1 root hub device descriptor */
33static u8 usb_bos_descriptor [] = {
34 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
35 USB_DT_BOS, /* __u8 bDescriptorType */
36 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
37 0x1, /* __u8 bNumDeviceCaps */
38 /* First device capability */
39 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
40 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
41 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
42 0x00, /* bmAttributes, LTM off by default */
43 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
44 0x03, /* bFunctionalitySupport,
45 USB 3.0 speed only */
46 0x00, /* bU1DevExitLat, set later. */
47 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
48};
49
50
51static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
52 struct usb_hub_descriptor *desc, int ports)
53{
54 u16 temp;
55
56 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
57 desc->bHubContrCurrent = 0;
58
59 desc->bNbrPorts = ports;
60 temp = 0;
61 /* Bits 1:0 - support per-port power switching, or power always on */
62 if (HCC_PPC(xhci->hcc_params))
63 temp |= HUB_CHAR_INDV_PORT_LPSM;
64 else
65 temp |= HUB_CHAR_NO_LPSM;
66 /* Bit 2 - root hubs are not part of a compound device */
67 /* Bits 4:3 - individual port over current protection */
68 temp |= HUB_CHAR_INDV_PORT_OCPM;
69 /* Bits 6:5 - no TTs in root ports */
70 /* Bit 7 - no port indicators */
71 desc->wHubCharacteristics = cpu_to_le16(temp);
72}
73
74/* Fill in the USB 2.0 roothub descriptor */
75static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
76 struct usb_hub_descriptor *desc)
77{
78 int ports;
79 u16 temp;
80 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
81 u32 portsc;
82 unsigned int i;
83
84 ports = xhci->num_usb2_ports;
85
86 xhci_common_hub_descriptor(xhci, desc, ports);
87 desc->bDescriptorType = USB_DT_HUB;
88 temp = 1 + (ports / 8);
89 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
90
91 /* The Device Removable bits are reported on a byte granularity.
92 * If the port doesn't exist within that byte, the bit is set to 0.
93 */
94 memset(port_removable, 0, sizeof(port_removable));
95 for (i = 0; i < ports; i++) {
96 portsc = xhci_readl(xhci, xhci->usb2_ports[i]);
97 /* If a device is removable, PORTSC reports a 0, same as in the
98 * hub descriptor DeviceRemovable bits.
99 */
100 if (portsc & PORT_DEV_REMOVE)
101 /* This math is hairy because bit 0 of DeviceRemovable
102 * is reserved, and bit 1 is for port 1, etc.
103 */
104 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
105 }
106
107 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
108 * ports on it. The USB 2.0 specification says that there are two
109 * variable length fields at the end of the hub descriptor:
110 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
111 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
112 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
113 * 0xFF, so we initialize the both arrays (DeviceRemovable and
114 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
115 * set of ports that actually exist.
116 */
117 memset(desc->u.hs.DeviceRemovable, 0xff,
118 sizeof(desc->u.hs.DeviceRemovable));
119 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
120 sizeof(desc->u.hs.PortPwrCtrlMask));
121
122 for (i = 0; i < (ports + 1 + 7) / 8; i++)
123 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
124 sizeof(__u8));
125}
126
127/* Fill in the USB 3.0 roothub descriptor */
128static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
129 struct usb_hub_descriptor *desc)
130{
131 int ports;
132 u16 port_removable;
133 u32 portsc;
134 unsigned int i;
135
136 ports = xhci->num_usb3_ports;
137 xhci_common_hub_descriptor(xhci, desc, ports);
138 desc->bDescriptorType = USB_DT_SS_HUB;
139 desc->bDescLength = USB_DT_SS_HUB_SIZE;
140
141 /* header decode latency should be zero for roothubs,
142 * see section 4.23.5.2.
143 */
144 desc->u.ss.bHubHdrDecLat = 0;
145 desc->u.ss.wHubDelay = 0;
146
147 port_removable = 0;
148 /* bit 0 is reserved, bit 1 is for port 1, etc. */
149 for (i = 0; i < ports; i++) {
150 portsc = xhci_readl(xhci, xhci->usb3_ports[i]);
151 if (portsc & PORT_DEV_REMOVE)
152 port_removable |= 1 << (i + 1);
153 }
154 memset(&desc->u.ss.DeviceRemovable,
155 (__force __u16) cpu_to_le16(port_removable),
156 sizeof(__u16));
157}
158
159static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
160 struct usb_hub_descriptor *desc)
161{
162
163 if (hcd->speed == HCD_USB3)
164 xhci_usb3_hub_descriptor(hcd, xhci, desc);
165 else
166 xhci_usb2_hub_descriptor(hcd, xhci, desc);
167
168}
169
170static unsigned int xhci_port_speed(unsigned int port_status)
171{
172 if (DEV_LOWSPEED(port_status))
173 return USB_PORT_STAT_LOW_SPEED;
174 if (DEV_HIGHSPEED(port_status))
175 return USB_PORT_STAT_HIGH_SPEED;
176 /*
177 * FIXME: Yes, we should check for full speed, but the core uses that as
178 * a default in portspeed() in usb/core/hub.c (which is the only place
179 * USB_PORT_STAT_*_SPEED is used).
180 */
181 return 0;
182}
183
184/*
185 * These bits are Read Only (RO) and should be saved and written to the
186 * registers: 0, 3, 10:13, 30
187 * connect status, over-current status, port speed, and device removable.
188 * connect status and port speed are also sticky - meaning they're in
189 * the AUX well and they aren't changed by a hot, warm, or cold reset.
190 */
191#define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
192/*
193 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
194 * bits 5:8, 9, 14:15, 25:27
195 * link state, port power, port indicator state, "wake on" enable state
196 */
197#define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
198/*
199 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
200 * bit 4 (port reset)
201 */
202#define XHCI_PORT_RW1S ((1<<4))
203/*
204 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
205 * bits 1, 17, 18, 19, 20, 21, 22, 23
206 * port enable/disable, and
207 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
208 * over-current, reset, link state, and L1 change
209 */
210#define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
211/*
212 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
213 * latched in
214 */
215#define XHCI_PORT_RW ((1<<16))
216/*
217 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
218 * bits 2, 24, 28:31
219 */
220#define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
221
222/*
223 * Given a port state, this function returns a value that would result in the
224 * port being in the same state, if the value was written to the port status
225 * control register.
226 * Save Read Only (RO) bits and save read/write bits where
227 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
228 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
229 */
230u32 xhci_port_state_to_neutral(u32 state)
231{
232 /* Save read-only status and port state */
233 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
234}
235
236/*
237 * find slot id based on port number.
238 * @port: The one-based port number from one of the two split roothubs.
239 */
240int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
241 u16 port)
242{
243 int slot_id;
244 int i;
245 enum usb_device_speed speed;
246
247 slot_id = 0;
248 for (i = 0; i < MAX_HC_SLOTS; i++) {
249 if (!xhci->devs[i])
250 continue;
251 speed = xhci->devs[i]->udev->speed;
252 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
253 && xhci->devs[i]->fake_port == port) {
254 slot_id = i;
255 break;
256 }
257 }
258
259 return slot_id;
260}
261
262/*
263 * Stop device
264 * It issues stop endpoint command for EP 0 to 30. And wait the last command
265 * to complete.
266 * suspend will set to 1, if suspend bit need to set in command.
267 */
268static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
269{
270 struct xhci_virt_device *virt_dev;
271 struct xhci_command *cmd;
272 unsigned long flags;
273 int timeleft;
274 int ret;
275 int i;
276
277 ret = 0;
278 virt_dev = xhci->devs[slot_id];
279 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
280 if (!cmd) {
281 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
282 return -ENOMEM;
283 }
284
285 spin_lock_irqsave(&xhci->lock, flags);
286 for (i = LAST_EP_INDEX; i > 0; i--) {
287 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
288 xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
289 }
290 cmd->command_trb = xhci->cmd_ring->enqueue;
291 list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
292 xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
293 xhci_ring_cmd_db(xhci);
294 spin_unlock_irqrestore(&xhci->lock, flags);
295
296 /* Wait for last stop endpoint command to finish */
297 timeleft = wait_for_completion_interruptible_timeout(
298 cmd->completion,
299 USB_CTRL_SET_TIMEOUT);
300 if (timeleft <= 0) {
301 xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
302 timeleft == 0 ? "Timeout" : "Signal");
303 spin_lock_irqsave(&xhci->lock, flags);
304 /* The timeout might have raced with the event ring handler, so
305 * only delete from the list if the item isn't poisoned.
306 */
307 if (cmd->cmd_list.next != LIST_POISON1)
308 list_del(&cmd->cmd_list);
309 spin_unlock_irqrestore(&xhci->lock, flags);
310 ret = -ETIME;
311 goto command_cleanup;
312 }
313
314command_cleanup:
315 xhci_free_command(xhci, cmd);
316 return ret;
317}
318
319/*
320 * Ring device, it rings the all doorbells unconditionally.
321 */
322void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
323{
324 int i;
325
326 for (i = 0; i < LAST_EP_INDEX + 1; i++)
327 if (xhci->devs[slot_id]->eps[i].ring &&
328 xhci->devs[slot_id]->eps[i].ring->dequeue)
329 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
330
331 return;
332}
333
334static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
335 u16 wIndex, __le32 __iomem *addr, u32 port_status)
336{
337 /* Don't allow the USB core to disable SuperSpeed ports. */
338 if (hcd->speed == HCD_USB3) {
339 xhci_dbg(xhci, "Ignoring request to disable "
340 "SuperSpeed port.\n");
341 return;
342 }
343
344 /* Write 1 to disable the port */
345 xhci_writel(xhci, port_status | PORT_PE, addr);
346 port_status = xhci_readl(xhci, addr);
347 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
348 wIndex, port_status);
349}
350
351static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
352 u16 wIndex, __le32 __iomem *addr, u32 port_status)
353{
354 char *port_change_bit;
355 u32 status;
356
357 switch (wValue) {
358 case USB_PORT_FEAT_C_RESET:
359 status = PORT_RC;
360 port_change_bit = "reset";
361 break;
362 case USB_PORT_FEAT_C_BH_PORT_RESET:
363 status = PORT_WRC;
364 port_change_bit = "warm(BH) reset";
365 break;
366 case USB_PORT_FEAT_C_CONNECTION:
367 status = PORT_CSC;
368 port_change_bit = "connect";
369 break;
370 case USB_PORT_FEAT_C_OVER_CURRENT:
371 status = PORT_OCC;
372 port_change_bit = "over-current";
373 break;
374 case USB_PORT_FEAT_C_ENABLE:
375 status = PORT_PEC;
376 port_change_bit = "enable/disable";
377 break;
378 case USB_PORT_FEAT_C_SUSPEND:
379 status = PORT_PLC;
380 port_change_bit = "suspend/resume";
381 break;
382 case USB_PORT_FEAT_C_PORT_LINK_STATE:
383 status = PORT_PLC;
384 port_change_bit = "link state";
385 break;
386 default:
387 /* Should never happen */
388 return;
389 }
390 /* Change bits are all write 1 to clear */
391 xhci_writel(xhci, port_status | status, addr);
392 port_status = xhci_readl(xhci, addr);
393 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
394 port_change_bit, wIndex, port_status);
395}
396
397static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
398{
399 int max_ports;
400 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
401
402 if (hcd->speed == HCD_USB3) {
403 max_ports = xhci->num_usb3_ports;
404 *port_array = xhci->usb3_ports;
405 } else {
406 max_ports = xhci->num_usb2_ports;
407 *port_array = xhci->usb2_ports;
408 }
409
410 return max_ports;
411}
412
413void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
414 int port_id, u32 link_state)
415{
416 u32 temp;
417
418 temp = xhci_readl(xhci, port_array[port_id]);
419 temp = xhci_port_state_to_neutral(temp);
420 temp &= ~PORT_PLS_MASK;
421 temp |= PORT_LINK_STROBE | link_state;
422 xhci_writel(xhci, temp, port_array[port_id]);
423}
424
425void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
426 __le32 __iomem **port_array, int port_id, u16 wake_mask)
427{
428 u32 temp;
429
430 temp = xhci_readl(xhci, port_array[port_id]);
431 temp = xhci_port_state_to_neutral(temp);
432
433 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
434 temp |= PORT_WKCONN_E;
435 else
436 temp &= ~PORT_WKCONN_E;
437
438 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
439 temp |= PORT_WKDISC_E;
440 else
441 temp &= ~PORT_WKDISC_E;
442
443 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
444 temp |= PORT_WKOC_E;
445 else
446 temp &= ~PORT_WKOC_E;
447
448 xhci_writel(xhci, temp, port_array[port_id]);
449}
450
451/* Test and clear port RWC bit */
452void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
453 int port_id, u32 port_bit)
454{
455 u32 temp;
456
457 temp = xhci_readl(xhci, port_array[port_id]);
458 if (temp & port_bit) {
459 temp = xhci_port_state_to_neutral(temp);
460 temp |= port_bit;
461 xhci_writel(xhci, temp, port_array[port_id]);
462 }
463}
464
465/* Updates Link Status for super Speed port */
466static void xhci_hub_report_link_state(u32 *status, u32 status_reg)
467{
468 u32 pls = status_reg & PORT_PLS_MASK;
469
470 /* resume state is a xHCI internal state.
471 * Do not report it to usb core.
472 */
473 if (pls == XDEV_RESUME)
474 return;
475
476 /* When the CAS bit is set then warm reset
477 * should be performed on port
478 */
479 if (status_reg & PORT_CAS) {
480 /* The CAS bit can be set while the port is
481 * in any link state.
482 * Only roothubs have CAS bit, so we
483 * pretend to be in compliance mode
484 * unless we're already in compliance
485 * or the inactive state.
486 */
487 if (pls != USB_SS_PORT_LS_COMP_MOD &&
488 pls != USB_SS_PORT_LS_SS_INACTIVE) {
489 pls = USB_SS_PORT_LS_COMP_MOD;
490 }
491 /* Return also connection bit -
492 * hub state machine resets port
493 * when this bit is set.
494 */
495 pls |= USB_PORT_STAT_CONNECTION;
496 } else {
497 /*
498 * If CAS bit isn't set but the Port is already at
499 * Compliance Mode, fake a connection so the USB core
500 * notices the Compliance state and resets the port.
501 * This resolves an issue generated by the SN65LVPE502CP
502 * in which sometimes the port enters compliance mode
503 * caused by a delay on the host-device negotiation.
504 */
505 if (pls == USB_SS_PORT_LS_COMP_MOD)
506 pls |= USB_PORT_STAT_CONNECTION;
507 }
508
509 /* update status field */
510 *status |= pls;
511}
512
513/*
514 * Function for Compliance Mode Quirk.
515 *
516 * This Function verifies if all xhc USB3 ports have entered U0, if so,
517 * the compliance mode timer is deleted. A port won't enter
518 * compliance mode if it has previously entered U0.
519 */
520void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, u16 wIndex)
521{
522 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
523 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
524
525 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
526 return;
527
528 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
529 xhci->port_status_u0 |= 1 << wIndex;
530 if (xhci->port_status_u0 == all_ports_seen_u0) {
531 del_timer_sync(&xhci->comp_mode_recovery_timer);
532 xhci_dbg(xhci, "All USB3 ports have entered U0 already!\n");
533 xhci_dbg(xhci, "Compliance Mode Recovery Timer Deleted.\n");
534 }
535 }
536}
537
538int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
539 u16 wIndex, char *buf, u16 wLength)
540{
541 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
542 int max_ports;
543 unsigned long flags;
544 u32 temp, status;
545 int retval = 0;
546 __le32 __iomem **port_array;
547 int slot_id;
548 struct xhci_bus_state *bus_state;
549 u16 link_state = 0;
550 u16 wake_mask = 0;
551 u16 timeout = 0;
552
553 max_ports = xhci_get_ports(hcd, &port_array);
554 bus_state = &xhci->bus_state[hcd_index(hcd)];
555
556 spin_lock_irqsave(&xhci->lock, flags);
557 switch (typeReq) {
558 case GetHubStatus:
559 /* No power source, over-current reported per port */
560 memset(buf, 0, 4);
561 break;
562 case GetHubDescriptor:
563 /* Check to make sure userspace is asking for the USB 3.0 hub
564 * descriptor for the USB 3.0 roothub. If not, we stall the
565 * endpoint, like external hubs do.
566 */
567 if (hcd->speed == HCD_USB3 &&
568 (wLength < USB_DT_SS_HUB_SIZE ||
569 wValue != (USB_DT_SS_HUB << 8))) {
570 xhci_dbg(xhci, "Wrong hub descriptor type for "
571 "USB 3.0 roothub.\n");
572 goto error;
573 }
574 xhci_hub_descriptor(hcd, xhci,
575 (struct usb_hub_descriptor *) buf);
576 break;
577 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
578 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
579 goto error;
580
581 if (hcd->speed != HCD_USB3)
582 goto error;
583
584 memcpy(buf, &usb_bos_descriptor,
585 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
586 temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
587 buf[12] = HCS_U1_LATENCY(temp);
588 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
589
590 spin_unlock_irqrestore(&xhci->lock, flags);
591 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
592 case GetPortStatus:
593 if (!wIndex || wIndex > max_ports)
594 goto error;
595 wIndex--;
596 status = 0;
597 temp = xhci_readl(xhci, port_array[wIndex]);
598 if (temp == 0xffffffff) {
599 retval = -ENODEV;
600 break;
601 }
602 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
603
604 /* wPortChange bits */
605 if (temp & PORT_CSC)
606 status |= USB_PORT_STAT_C_CONNECTION << 16;
607 if (temp & PORT_PEC)
608 status |= USB_PORT_STAT_C_ENABLE << 16;
609 if ((temp & PORT_OCC))
610 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
611 if ((temp & PORT_RC))
612 status |= USB_PORT_STAT_C_RESET << 16;
613 /* USB3.0 only */
614 if (hcd->speed == HCD_USB3) {
615 if ((temp & PORT_PLC))
616 status |= USB_PORT_STAT_C_LINK_STATE << 16;
617 if ((temp & PORT_WRC))
618 status |= USB_PORT_STAT_C_BH_RESET << 16;
619 }
620
621 if (hcd->speed != HCD_USB3) {
622 if ((temp & PORT_PLS_MASK) == XDEV_U3
623 && (temp & PORT_POWER))
624 status |= USB_PORT_STAT_SUSPEND;
625 }
626 if ((temp & PORT_PLS_MASK) == XDEV_RESUME &&
627 !DEV_SUPERSPEED(temp)) {
628 if ((temp & PORT_RESET) || !(temp & PORT_PE))
629 goto error;
630 if (time_after_eq(jiffies,
631 bus_state->resume_done[wIndex])) {
632 xhci_dbg(xhci, "Resume USB2 port %d\n",
633 wIndex + 1);
634 bus_state->resume_done[wIndex] = 0;
635 clear_bit(wIndex, &bus_state->resuming_ports);
636 xhci_set_link_state(xhci, port_array, wIndex,
637 XDEV_U0);
638 xhci_dbg(xhci, "set port %d resume\n",
639 wIndex + 1);
640 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
641 wIndex + 1);
642 if (!slot_id) {
643 xhci_dbg(xhci, "slot_id is zero\n");
644 goto error;
645 }
646 xhci_ring_device(xhci, slot_id);
647 bus_state->port_c_suspend |= 1 << wIndex;
648 bus_state->suspended_ports &= ~(1 << wIndex);
649 } else {
650 /*
651 * The resume has been signaling for less than
652 * 20ms. Report the port status as SUSPEND,
653 * let the usbcore check port status again
654 * and clear resume signaling later.
655 */
656 status |= USB_PORT_STAT_SUSPEND;
657 }
658 }
659 if ((temp & PORT_PLS_MASK) == XDEV_U0
660 && (temp & PORT_POWER)
661 && (bus_state->suspended_ports & (1 << wIndex))) {
662 bus_state->suspended_ports &= ~(1 << wIndex);
663 if (hcd->speed != HCD_USB3)
664 bus_state->port_c_suspend |= 1 << wIndex;
665 }
666 if (temp & PORT_CONNECT) {
667 status |= USB_PORT_STAT_CONNECTION;
668 status |= xhci_port_speed(temp);
669 }
670 if (temp & PORT_PE)
671 status |= USB_PORT_STAT_ENABLE;
672 if (temp & PORT_OC)
673 status |= USB_PORT_STAT_OVERCURRENT;
674 if (temp & PORT_RESET)
675 status |= USB_PORT_STAT_RESET;
676 if (temp & PORT_POWER) {
677 if (hcd->speed == HCD_USB3)
678 status |= USB_SS_PORT_STAT_POWER;
679 else
680 status |= USB_PORT_STAT_POWER;
681 }
682 /* Update Port Link State for super speed ports*/
683 if (hcd->speed == HCD_USB3) {
684 xhci_hub_report_link_state(&status, temp);
685 /*
686 * Verify if all USB3 Ports Have entered U0 already.
687 * Delete Compliance Mode Timer if so.
688 */
689 xhci_del_comp_mod_timer(xhci, temp, wIndex);
690 }
691 if (bus_state->port_c_suspend & (1 << wIndex))
692 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
693 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
694 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
695 break;
696 case SetPortFeature:
697 if (wValue == USB_PORT_FEAT_LINK_STATE)
698 link_state = (wIndex & 0xff00) >> 3;
699 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
700 wake_mask = wIndex & 0xff00;
701 /* The MSB of wIndex is the U1/U2 timeout */
702 timeout = (wIndex & 0xff00) >> 8;
703 wIndex &= 0xff;
704 if (!wIndex || wIndex > max_ports)
705 goto error;
706 wIndex--;
707 temp = xhci_readl(xhci, port_array[wIndex]);
708 if (temp == 0xffffffff) {
709 retval = -ENODEV;
710 break;
711 }
712 temp = xhci_port_state_to_neutral(temp);
713 /* FIXME: What new port features do we need to support? */
714 switch (wValue) {
715 case USB_PORT_FEAT_SUSPEND:
716 temp = xhci_readl(xhci, port_array[wIndex]);
717 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
718 /* Resume the port to U0 first */
719 xhci_set_link_state(xhci, port_array, wIndex,
720 XDEV_U0);
721 spin_unlock_irqrestore(&xhci->lock, flags);
722 msleep(10);
723 spin_lock_irqsave(&xhci->lock, flags);
724 }
725 /* In spec software should not attempt to suspend
726 * a port unless the port reports that it is in the
727 * enabled (PED = ‘1’,PLS < ‘3’) state.
728 */
729 temp = xhci_readl(xhci, port_array[wIndex]);
730 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
731 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
732 xhci_warn(xhci, "USB core suspending device "
733 "not in U0/U1/U2.\n");
734 goto error;
735 }
736
737 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
738 wIndex + 1);
739 if (!slot_id) {
740 xhci_warn(xhci, "slot_id is zero\n");
741 goto error;
742 }
743 /* unlock to execute stop endpoint commands */
744 spin_unlock_irqrestore(&xhci->lock, flags);
745 xhci_stop_device(xhci, slot_id, 1);
746 spin_lock_irqsave(&xhci->lock, flags);
747
748 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
749
750 spin_unlock_irqrestore(&xhci->lock, flags);
751 msleep(10); /* wait device to enter */
752 spin_lock_irqsave(&xhci->lock, flags);
753
754 temp = xhci_readl(xhci, port_array[wIndex]);
755 bus_state->suspended_ports |= 1 << wIndex;
756 break;
757 case USB_PORT_FEAT_LINK_STATE:
758 temp = xhci_readl(xhci, port_array[wIndex]);
759 /* Software should not attempt to set
760 * port link state above '5' (Rx.Detect) and the port
761 * must be enabled.
762 */
763 if ((temp & PORT_PE) == 0 ||
764 (link_state > USB_SS_PORT_LS_RX_DETECT)) {
765 xhci_warn(xhci, "Cannot set link state.\n");
766 goto error;
767 }
768
769 if (link_state == USB_SS_PORT_LS_U3) {
770 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
771 wIndex + 1);
772 if (slot_id) {
773 /* unlock to execute stop endpoint
774 * commands */
775 spin_unlock_irqrestore(&xhci->lock,
776 flags);
777 xhci_stop_device(xhci, slot_id, 1);
778 spin_lock_irqsave(&xhci->lock, flags);
779 }
780 }
781
782 xhci_set_link_state(xhci, port_array, wIndex,
783 link_state);
784
785 spin_unlock_irqrestore(&xhci->lock, flags);
786 msleep(20); /* wait device to enter */
787 spin_lock_irqsave(&xhci->lock, flags);
788
789 temp = xhci_readl(xhci, port_array[wIndex]);
790 if (link_state == USB_SS_PORT_LS_U3)
791 bus_state->suspended_ports |= 1 << wIndex;
792 break;
793 case USB_PORT_FEAT_POWER:
794 /*
795 * Turn on ports, even if there isn't per-port switching.
796 * HC will report connect events even before this is set.
797 * However, khubd will ignore the roothub events until
798 * the roothub is registered.
799 */
800 xhci_writel(xhci, temp | PORT_POWER,
801 port_array[wIndex]);
802
803 temp = xhci_readl(xhci, port_array[wIndex]);
804 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
805 break;
806 case USB_PORT_FEAT_RESET:
807 temp = (temp | PORT_RESET);
808 xhci_writel(xhci, temp, port_array[wIndex]);
809
810 temp = xhci_readl(xhci, port_array[wIndex]);
811 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
812 break;
813 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
814 xhci_set_remote_wake_mask(xhci, port_array,
815 wIndex, wake_mask);
816 temp = xhci_readl(xhci, port_array[wIndex]);
817 xhci_dbg(xhci, "set port remote wake mask, "
818 "actual port %d status = 0x%x\n",
819 wIndex, temp);
820 break;
821 case USB_PORT_FEAT_BH_PORT_RESET:
822 temp |= PORT_WR;
823 xhci_writel(xhci, temp, port_array[wIndex]);
824
825 temp = xhci_readl(xhci, port_array[wIndex]);
826 break;
827 case USB_PORT_FEAT_U1_TIMEOUT:
828 if (hcd->speed != HCD_USB3)
829 goto error;
830 temp = xhci_readl(xhci, port_array[wIndex] + 1);
831 temp &= ~PORT_U1_TIMEOUT_MASK;
832 temp |= PORT_U1_TIMEOUT(timeout);
833 xhci_writel(xhci, temp, port_array[wIndex] + 1);
834 break;
835 case USB_PORT_FEAT_U2_TIMEOUT:
836 if (hcd->speed != HCD_USB3)
837 goto error;
838 temp = xhci_readl(xhci, port_array[wIndex] + 1);
839 temp &= ~PORT_U2_TIMEOUT_MASK;
840 temp |= PORT_U2_TIMEOUT(timeout);
841 xhci_writel(xhci, temp, port_array[wIndex] + 1);
842 break;
843 default:
844 goto error;
845 }
846 /* unblock any posted writes */
847 temp = xhci_readl(xhci, port_array[wIndex]);
848 break;
849 case ClearPortFeature:
850 if (!wIndex || wIndex > max_ports)
851 goto error;
852 wIndex--;
853 temp = xhci_readl(xhci, port_array[wIndex]);
854 if (temp == 0xffffffff) {
855 retval = -ENODEV;
856 break;
857 }
858 /* FIXME: What new port features do we need to support? */
859 temp = xhci_port_state_to_neutral(temp);
860 switch (wValue) {
861 case USB_PORT_FEAT_SUSPEND:
862 temp = xhci_readl(xhci, port_array[wIndex]);
863 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
864 xhci_dbg(xhci, "PORTSC %04x\n", temp);
865 if (temp & PORT_RESET)
866 goto error;
867 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
868 if ((temp & PORT_PE) == 0)
869 goto error;
870
871 xhci_set_link_state(xhci, port_array, wIndex,
872 XDEV_RESUME);
873 spin_unlock_irqrestore(&xhci->lock, flags);
874 msleep(20);
875 spin_lock_irqsave(&xhci->lock, flags);
876 xhci_set_link_state(xhci, port_array, wIndex,
877 XDEV_U0);
878 }
879 bus_state->port_c_suspend |= 1 << wIndex;
880
881 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
882 wIndex + 1);
883 if (!slot_id) {
884 xhci_dbg(xhci, "slot_id is zero\n");
885 goto error;
886 }
887 xhci_ring_device(xhci, slot_id);
888 break;
889 case USB_PORT_FEAT_C_SUSPEND:
890 bus_state->port_c_suspend &= ~(1 << wIndex);
891 case USB_PORT_FEAT_C_RESET:
892 case USB_PORT_FEAT_C_BH_PORT_RESET:
893 case USB_PORT_FEAT_C_CONNECTION:
894 case USB_PORT_FEAT_C_OVER_CURRENT:
895 case USB_PORT_FEAT_C_ENABLE:
896 case USB_PORT_FEAT_C_PORT_LINK_STATE:
897 xhci_clear_port_change_bit(xhci, wValue, wIndex,
898 port_array[wIndex], temp);
899 break;
900 case USB_PORT_FEAT_ENABLE:
901 xhci_disable_port(hcd, xhci, wIndex,
902 port_array[wIndex], temp);
903 break;
904 default:
905 goto error;
906 }
907 break;
908 default:
909error:
910 /* "stall" on error */
911 retval = -EPIPE;
912 }
913 spin_unlock_irqrestore(&xhci->lock, flags);
914 return retval;
915}
916
917/*
918 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
919 * Ports are 0-indexed from the HCD point of view,
920 * and 1-indexed from the USB core pointer of view.
921 *
922 * Note that the status change bits will be cleared as soon as a port status
923 * change event is generated, so we use the saved status from that event.
924 */
925int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
926{
927 unsigned long flags;
928 u32 temp, status;
929 u32 mask;
930 int i, retval;
931 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
932 int max_ports;
933 __le32 __iomem **port_array;
934 struct xhci_bus_state *bus_state;
935
936 max_ports = xhci_get_ports(hcd, &port_array);
937 bus_state = &xhci->bus_state[hcd_index(hcd)];
938
939 /* Initial status is no changes */
940 retval = (max_ports + 8) / 8;
941 memset(buf, 0, retval);
942
943 /*
944 * Inform the usbcore about resume-in-progress by returning
945 * a non-zero value even if there are no status changes.
946 */
947 status = bus_state->resuming_ports;
948
949 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
950
951 spin_lock_irqsave(&xhci->lock, flags);
952 /* For each port, did anything change? If so, set that bit in buf. */
953 for (i = 0; i < max_ports; i++) {
954 temp = xhci_readl(xhci, port_array[i]);
955 if (temp == 0xffffffff) {
956 retval = -ENODEV;
957 break;
958 }
959 if ((temp & mask) != 0 ||
960 (bus_state->port_c_suspend & 1 << i) ||
961 (bus_state->resume_done[i] && time_after_eq(
962 jiffies, bus_state->resume_done[i]))) {
963 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
964 status = 1;
965 }
966 }
967 spin_unlock_irqrestore(&xhci->lock, flags);
968 return status ? retval : 0;
969}
970
971#ifdef CONFIG_PM
972
973int xhci_bus_suspend(struct usb_hcd *hcd)
974{
975 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
976 int max_ports, port_index;
977 __le32 __iomem **port_array;
978 struct xhci_bus_state *bus_state;
979 unsigned long flags;
980
981 max_ports = xhci_get_ports(hcd, &port_array);
982 bus_state = &xhci->bus_state[hcd_index(hcd)];
983
984 spin_lock_irqsave(&xhci->lock, flags);
985
986 if (hcd->self.root_hub->do_remote_wakeup) {
987 if (bus_state->resuming_ports) {
988 spin_unlock_irqrestore(&xhci->lock, flags);
989 xhci_dbg(xhci, "suspend failed because "
990 "a port is resuming\n");
991 return -EBUSY;
992 }
993 }
994
995 port_index = max_ports;
996 bus_state->bus_suspended = 0;
997 while (port_index--) {
998 /* suspend the port if the port is not suspended */
999 u32 t1, t2;
1000 int slot_id;
1001
1002 t1 = xhci_readl(xhci, port_array[port_index]);
1003 t2 = xhci_port_state_to_neutral(t1);
1004
1005 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1006 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1007 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1008 port_index + 1);
1009 if (slot_id) {
1010 spin_unlock_irqrestore(&xhci->lock, flags);
1011 xhci_stop_device(xhci, slot_id, 1);
1012 spin_lock_irqsave(&xhci->lock, flags);
1013 }
1014 t2 &= ~PORT_PLS_MASK;
1015 t2 |= PORT_LINK_STROBE | XDEV_U3;
1016 set_bit(port_index, &bus_state->bus_suspended);
1017 }
1018 /* USB core sets remote wake mask for USB 3.0 hubs,
1019 * including the USB 3.0 roothub, but only if CONFIG_USB_SUSPEND
1020 * is enabled, so also enable remote wake here.
1021 */
1022 if (hcd->self.root_hub->do_remote_wakeup) {
1023 if (t1 & PORT_CONNECT) {
1024 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1025 t2 &= ~PORT_WKCONN_E;
1026 } else {
1027 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1028 t2 &= ~PORT_WKDISC_E;
1029 }
1030 } else
1031 t2 &= ~PORT_WAKE_BITS;
1032
1033 t1 = xhci_port_state_to_neutral(t1);
1034 if (t1 != t2)
1035 xhci_writel(xhci, t2, port_array[port_index]);
1036
1037 if (hcd->speed != HCD_USB3) {
1038 /* enable remote wake up for USB 2.0 */
1039 __le32 __iomem *addr;
1040 u32 tmp;
1041
1042 /* Add one to the port status register address to get
1043 * the port power control register address.
1044 */
1045 addr = port_array[port_index] + 1;
1046 tmp = xhci_readl(xhci, addr);
1047 tmp |= PORT_RWE;
1048 xhci_writel(xhci, tmp, addr);
1049 }
1050 }
1051 hcd->state = HC_STATE_SUSPENDED;
1052 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1053 spin_unlock_irqrestore(&xhci->lock, flags);
1054 return 0;
1055}
1056
1057int xhci_bus_resume(struct usb_hcd *hcd)
1058{
1059 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1060 int max_ports, port_index;
1061 __le32 __iomem **port_array;
1062 struct xhci_bus_state *bus_state;
1063 u32 temp;
1064 unsigned long flags;
1065
1066 max_ports = xhci_get_ports(hcd, &port_array);
1067 bus_state = &xhci->bus_state[hcd_index(hcd)];
1068
1069 if (time_before(jiffies, bus_state->next_statechange))
1070 msleep(5);
1071
1072 spin_lock_irqsave(&xhci->lock, flags);
1073 if (!HCD_HW_ACCESSIBLE(hcd)) {
1074 spin_unlock_irqrestore(&xhci->lock, flags);
1075 return -ESHUTDOWN;
1076 }
1077
1078 /* delay the irqs */
1079 temp = xhci_readl(xhci, &xhci->op_regs->command);
1080 temp &= ~CMD_EIE;
1081 xhci_writel(xhci, temp, &xhci->op_regs->command);
1082
1083 port_index = max_ports;
1084 while (port_index--) {
1085 /* Check whether need resume ports. If needed
1086 resume port and disable remote wakeup */
1087 u32 temp;
1088 int slot_id;
1089
1090 temp = xhci_readl(xhci, port_array[port_index]);
1091 if (DEV_SUPERSPEED(temp))
1092 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1093 else
1094 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1095 if (test_bit(port_index, &bus_state->bus_suspended) &&
1096 (temp & PORT_PLS_MASK)) {
1097 if (DEV_SUPERSPEED(temp)) {
1098 xhci_set_link_state(xhci, port_array,
1099 port_index, XDEV_U0);
1100 } else {
1101 xhci_set_link_state(xhci, port_array,
1102 port_index, XDEV_RESUME);
1103
1104 spin_unlock_irqrestore(&xhci->lock, flags);
1105 msleep(20);
1106 spin_lock_irqsave(&xhci->lock, flags);
1107
1108 xhci_set_link_state(xhci, port_array,
1109 port_index, XDEV_U0);
1110 }
1111 /* wait for the port to enter U0 and report port link
1112 * state change.
1113 */
1114 spin_unlock_irqrestore(&xhci->lock, flags);
1115 msleep(20);
1116 spin_lock_irqsave(&xhci->lock, flags);
1117
1118 /* Clear PLC */
1119 xhci_test_and_clear_bit(xhci, port_array, port_index,
1120 PORT_PLC);
1121
1122 slot_id = xhci_find_slot_id_by_port(hcd,
1123 xhci, port_index + 1);
1124 if (slot_id)
1125 xhci_ring_device(xhci, slot_id);
1126 } else
1127 xhci_writel(xhci, temp, port_array[port_index]);
1128
1129 if (hcd->speed != HCD_USB3) {
1130 /* disable remote wake up for USB 2.0 */
1131 __le32 __iomem *addr;
1132 u32 tmp;
1133
1134 /* Add one to the port status register address to get
1135 * the port power control register address.
1136 */
1137 addr = port_array[port_index] + 1;
1138 tmp = xhci_readl(xhci, addr);
1139 tmp &= ~PORT_RWE;
1140 xhci_writel(xhci, tmp, addr);
1141 }
1142 }
1143
1144 (void) xhci_readl(xhci, &xhci->op_regs->command);
1145
1146 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1147 /* re-enable irqs */
1148 temp = xhci_readl(xhci, &xhci->op_regs->command);
1149 temp |= CMD_EIE;
1150 xhci_writel(xhci, temp, &xhci->op_regs->command);
1151 temp = xhci_readl(xhci, &xhci->op_regs->command);
1152
1153 spin_unlock_irqrestore(&xhci->lock, flags);
1154 return 0;
1155}
1156
1157#endif /* CONFIG_PM */