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1/*
2 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
3 * Copyright (c) 2008-2009 Marvell Semiconductor
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11#include <linux/delay.h>
12#include <linux/jiffies.h>
13#include <linux/list.h>
14#include <linux/module.h>
15#include <linux/netdevice.h>
16#include <linux/phy.h>
17#include <net/dsa.h>
18
19#define REG_PORT(p) (8 + (p))
20#define REG_GLOBAL 0x0f
21
22static int reg_read(struct dsa_switch *ds, int addr, int reg)
23{
24 return mdiobus_read(ds->master_mii_bus, ds->pd->sw_addr + addr, reg);
25}
26
27#define REG_READ(addr, reg) \
28 ({ \
29 int __ret; \
30 \
31 __ret = reg_read(ds, addr, reg); \
32 if (__ret < 0) \
33 return __ret; \
34 __ret; \
35 })
36
37
38static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
39{
40 return mdiobus_write(ds->master_mii_bus, ds->pd->sw_addr + addr,
41 reg, val);
42}
43
44#define REG_WRITE(addr, reg, val) \
45 ({ \
46 int __ret; \
47 \
48 __ret = reg_write(ds, addr, reg, val); \
49 if (__ret < 0) \
50 return __ret; \
51 })
52
53static char *mv88e6060_probe(struct mii_bus *bus, int sw_addr)
54{
55 int ret;
56
57 ret = mdiobus_read(bus, sw_addr + REG_PORT(0), 0x03);
58 if (ret >= 0) {
59 ret &= 0xfff0;
60 if (ret == 0x0600)
61 return "Marvell 88E6060";
62 }
63
64 return NULL;
65}
66
67static int mv88e6060_switch_reset(struct dsa_switch *ds)
68{
69 int i;
70 int ret;
71 unsigned long timeout;
72
73 /* Set all ports to the disabled state. */
74 for (i = 0; i < 6; i++) {
75 ret = REG_READ(REG_PORT(i), 0x04);
76 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
77 }
78
79 /* Wait for transmit queues to drain. */
80 usleep_range(2000, 4000);
81
82 /* Reset the switch. */
83 REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
84
85 /* Wait up to one second for reset to complete. */
86 timeout = jiffies + 1 * HZ;
87 while (time_before(jiffies, timeout)) {
88 ret = REG_READ(REG_GLOBAL, 0x00);
89 if ((ret & 0x8000) == 0x0000)
90 break;
91
92 usleep_range(1000, 2000);
93 }
94 if (time_after(jiffies, timeout))
95 return -ETIMEDOUT;
96
97 return 0;
98}
99
100static int mv88e6060_setup_global(struct dsa_switch *ds)
101{
102 /* Disable discarding of frames with excessive collisions,
103 * set the maximum frame size to 1536 bytes, and mask all
104 * interrupt sources.
105 */
106 REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
107
108 /* Enable automatic address learning, set the address
109 * database size to 1024 entries, and set the default aging
110 * time to 5 minutes.
111 */
112 REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
113
114 return 0;
115}
116
117static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
118{
119 int addr = REG_PORT(p);
120
121 /* Do not force flow control, disable Ingress and Egress
122 * Header tagging, disable VLAN tunneling, and set the port
123 * state to Forwarding. Additionally, if this is the CPU
124 * port, enable Ingress and Egress Trailer tagging mode.
125 */
126 REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
127
128 /* Port based VLAN map: give each port its own address
129 * database, allow the CPU port to talk to each of the 'real'
130 * ports, and allow each of the 'real' ports to only talk to
131 * the CPU port.
132 */
133 REG_WRITE(addr, 0x06,
134 ((p & 0xf) << 12) |
135 (dsa_is_cpu_port(ds, p) ?
136 ds->phys_port_mask :
137 (1 << ds->dst->cpu_port)));
138
139 /* Port Association Vector: when learning source addresses
140 * of packets, add the address to the address database using
141 * a port bitmap that has only the bit for this port set and
142 * the other bits clear.
143 */
144 REG_WRITE(addr, 0x0b, 1 << p);
145
146 return 0;
147}
148
149static int mv88e6060_setup(struct dsa_switch *ds)
150{
151 int i;
152 int ret;
153
154 ret = mv88e6060_switch_reset(ds);
155 if (ret < 0)
156 return ret;
157
158 /* @@@ initialise atu */
159
160 ret = mv88e6060_setup_global(ds);
161 if (ret < 0)
162 return ret;
163
164 for (i = 0; i < 6; i++) {
165 ret = mv88e6060_setup_port(ds, i);
166 if (ret < 0)
167 return ret;
168 }
169
170 return 0;
171}
172
173static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
174{
175 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
176 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
177 REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
178
179 return 0;
180}
181
182static int mv88e6060_port_to_phy_addr(int port)
183{
184 if (port >= 0 && port <= 5)
185 return port;
186 return -1;
187}
188
189static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
190{
191 int addr;
192
193 addr = mv88e6060_port_to_phy_addr(port);
194 if (addr == -1)
195 return 0xffff;
196
197 return reg_read(ds, addr, regnum);
198}
199
200static int
201mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
202{
203 int addr;
204
205 addr = mv88e6060_port_to_phy_addr(port);
206 if (addr == -1)
207 return 0xffff;
208
209 return reg_write(ds, addr, regnum, val);
210}
211
212static void mv88e6060_poll_link(struct dsa_switch *ds)
213{
214 int i;
215
216 for (i = 0; i < DSA_MAX_PORTS; i++) {
217 struct net_device *dev;
218 int uninitialized_var(port_status);
219 int link;
220 int speed;
221 int duplex;
222 int fc;
223
224 dev = ds->ports[i];
225 if (dev == NULL)
226 continue;
227
228 link = 0;
229 if (dev->flags & IFF_UP) {
230 port_status = reg_read(ds, REG_PORT(i), 0x00);
231 if (port_status < 0)
232 continue;
233
234 link = !!(port_status & 0x1000);
235 }
236
237 if (!link) {
238 if (netif_carrier_ok(dev)) {
239 netdev_info(dev, "link down\n");
240 netif_carrier_off(dev);
241 }
242 continue;
243 }
244
245 speed = (port_status & 0x0100) ? 100 : 10;
246 duplex = (port_status & 0x0200) ? 1 : 0;
247 fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
248
249 if (!netif_carrier_ok(dev)) {
250 netdev_info(dev,
251 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
252 speed,
253 duplex ? "full" : "half",
254 fc ? "en" : "dis");
255 netif_carrier_on(dev);
256 }
257 }
258}
259
260static struct dsa_switch_driver mv88e6060_switch_driver = {
261 .tag_protocol = htons(ETH_P_TRAILER),
262 .probe = mv88e6060_probe,
263 .setup = mv88e6060_setup,
264 .set_addr = mv88e6060_set_addr,
265 .phy_read = mv88e6060_phy_read,
266 .phy_write = mv88e6060_phy_write,
267 .poll_link = mv88e6060_poll_link,
268};
269
270static int __init mv88e6060_init(void)
271{
272 register_switch_driver(&mv88e6060_switch_driver);
273 return 0;
274}
275module_init(mv88e6060_init);
276
277static void __exit mv88e6060_cleanup(void)
278{
279 unregister_switch_driver(&mv88e6060_switch_driver);
280}
281module_exit(mv88e6060_cleanup);
282
283MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
284MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
285MODULE_LICENSE("GPL");
286MODULE_ALIAS("platform:mv88e6060");
1/*
2 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
3 * Copyright (c) 2008-2009 Marvell Semiconductor
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11#include <linux/list.h>
12#include <linux/module.h>
13#include <linux/netdevice.h>
14#include <linux/phy.h>
15#include <net/dsa.h>
16
17#define REG_PORT(p) (8 + (p))
18#define REG_GLOBAL 0x0f
19
20static int reg_read(struct dsa_switch *ds, int addr, int reg)
21{
22 return mdiobus_read(ds->master_mii_bus, ds->pd->sw_addr + addr, reg);
23}
24
25#define REG_READ(addr, reg) \
26 ({ \
27 int __ret; \
28 \
29 __ret = reg_read(ds, addr, reg); \
30 if (__ret < 0) \
31 return __ret; \
32 __ret; \
33 })
34
35
36static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
37{
38 return mdiobus_write(ds->master_mii_bus, ds->pd->sw_addr + addr,
39 reg, val);
40}
41
42#define REG_WRITE(addr, reg, val) \
43 ({ \
44 int __ret; \
45 \
46 __ret = reg_write(ds, addr, reg, val); \
47 if (__ret < 0) \
48 return __ret; \
49 })
50
51static char *mv88e6060_probe(struct mii_bus *bus, int sw_addr)
52{
53 int ret;
54
55 ret = mdiobus_read(bus, sw_addr + REG_PORT(0), 0x03);
56 if (ret >= 0) {
57 ret &= 0xfff0;
58 if (ret == 0x0600)
59 return "Marvell 88E6060";
60 }
61
62 return NULL;
63}
64
65static int mv88e6060_switch_reset(struct dsa_switch *ds)
66{
67 int i;
68 int ret;
69
70 /*
71 * Set all ports to the disabled state.
72 */
73 for (i = 0; i < 6; i++) {
74 ret = REG_READ(REG_PORT(i), 0x04);
75 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
76 }
77
78 /*
79 * Wait for transmit queues to drain.
80 */
81 msleep(2);
82
83 /*
84 * Reset the switch.
85 */
86 REG_WRITE(REG_GLOBAL, 0x0a, 0xa130);
87
88 /*
89 * Wait up to one second for reset to complete.
90 */
91 for (i = 0; i < 1000; i++) {
92 ret = REG_READ(REG_GLOBAL, 0x00);
93 if ((ret & 0x8000) == 0x0000)
94 break;
95
96 msleep(1);
97 }
98 if (i == 1000)
99 return -ETIMEDOUT;
100
101 return 0;
102}
103
104static int mv88e6060_setup_global(struct dsa_switch *ds)
105{
106 /*
107 * Disable discarding of frames with excessive collisions,
108 * set the maximum frame size to 1536 bytes, and mask all
109 * interrupt sources.
110 */
111 REG_WRITE(REG_GLOBAL, 0x04, 0x0800);
112
113 /*
114 * Enable automatic address learning, set the address
115 * database size to 1024 entries, and set the default aging
116 * time to 5 minutes.
117 */
118 REG_WRITE(REG_GLOBAL, 0x0a, 0x2130);
119
120 return 0;
121}
122
123static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
124{
125 int addr = REG_PORT(p);
126
127 /*
128 * Do not force flow control, disable Ingress and Egress
129 * Header tagging, disable VLAN tunneling, and set the port
130 * state to Forwarding. Additionally, if this is the CPU
131 * port, enable Ingress and Egress Trailer tagging mode.
132 */
133 REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003);
134
135 /*
136 * Port based VLAN map: give each port its own address
137 * database, allow the CPU port to talk to each of the 'real'
138 * ports, and allow each of the 'real' ports to only talk to
139 * the CPU port.
140 */
141 REG_WRITE(addr, 0x06,
142 ((p & 0xf) << 12) |
143 (dsa_is_cpu_port(ds, p) ?
144 ds->phys_port_mask :
145 (1 << ds->dst->cpu_port)));
146
147 /*
148 * Port Association Vector: when learning source addresses
149 * of packets, add the address to the address database using
150 * a port bitmap that has only the bit for this port set and
151 * the other bits clear.
152 */
153 REG_WRITE(addr, 0x0b, 1 << p);
154
155 return 0;
156}
157
158static int mv88e6060_setup(struct dsa_switch *ds)
159{
160 int i;
161 int ret;
162
163 ret = mv88e6060_switch_reset(ds);
164 if (ret < 0)
165 return ret;
166
167 /* @@@ initialise atu */
168
169 ret = mv88e6060_setup_global(ds);
170 if (ret < 0)
171 return ret;
172
173 for (i = 0; i < 6; i++) {
174 ret = mv88e6060_setup_port(ds, i);
175 if (ret < 0)
176 return ret;
177 }
178
179 return 0;
180}
181
182static int mv88e6060_set_addr(struct dsa_switch *ds, u8 *addr)
183{
184 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
185 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
186 REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
187
188 return 0;
189}
190
191static int mv88e6060_port_to_phy_addr(int port)
192{
193 if (port >= 0 && port <= 5)
194 return port;
195 return -1;
196}
197
198static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
199{
200 int addr;
201
202 addr = mv88e6060_port_to_phy_addr(port);
203 if (addr == -1)
204 return 0xffff;
205
206 return reg_read(ds, addr, regnum);
207}
208
209static int
210mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
211{
212 int addr;
213
214 addr = mv88e6060_port_to_phy_addr(port);
215 if (addr == -1)
216 return 0xffff;
217
218 return reg_write(ds, addr, regnum, val);
219}
220
221static void mv88e6060_poll_link(struct dsa_switch *ds)
222{
223 int i;
224
225 for (i = 0; i < DSA_MAX_PORTS; i++) {
226 struct net_device *dev;
227 int uninitialized_var(port_status);
228 int link;
229 int speed;
230 int duplex;
231 int fc;
232
233 dev = ds->ports[i];
234 if (dev == NULL)
235 continue;
236
237 link = 0;
238 if (dev->flags & IFF_UP) {
239 port_status = reg_read(ds, REG_PORT(i), 0x00);
240 if (port_status < 0)
241 continue;
242
243 link = !!(port_status & 0x1000);
244 }
245
246 if (!link) {
247 if (netif_carrier_ok(dev)) {
248 printk(KERN_INFO "%s: link down\n", dev->name);
249 netif_carrier_off(dev);
250 }
251 continue;
252 }
253
254 speed = (port_status & 0x0100) ? 100 : 10;
255 duplex = (port_status & 0x0200) ? 1 : 0;
256 fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0;
257
258 if (!netif_carrier_ok(dev)) {
259 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
260 "flow control %sabled\n", dev->name,
261 speed, duplex ? "full" : "half",
262 fc ? "en" : "dis");
263 netif_carrier_on(dev);
264 }
265 }
266}
267
268static struct dsa_switch_driver mv88e6060_switch_driver = {
269 .tag_protocol = htons(ETH_P_TRAILER),
270 .probe = mv88e6060_probe,
271 .setup = mv88e6060_setup,
272 .set_addr = mv88e6060_set_addr,
273 .phy_read = mv88e6060_phy_read,
274 .phy_write = mv88e6060_phy_write,
275 .poll_link = mv88e6060_poll_link,
276};
277
278static int __init mv88e6060_init(void)
279{
280 register_switch_driver(&mv88e6060_switch_driver);
281 return 0;
282}
283module_init(mv88e6060_init);
284
285static void __exit mv88e6060_cleanup(void)
286{
287 unregister_switch_driver(&mv88e6060_switch_driver);
288}
289module_exit(mv88e6060_cleanup);
290
291MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
292MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
293MODULE_LICENSE("GPL");
294MODULE_ALIAS("platform:mv88e6060");