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v3.15
  1/*
  2 * Copyright (C) ST-Ericsson SA 2010
  3 *
  4 * License Terms: GNU General Public License, version 2
  5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  6 */
  7
  8#include <linux/module.h>
  9#include <linux/init.h>
 10#include <linux/platform_device.h>
 11#include <linux/slab.h>
 12#include <linux/gpio.h>
 13#include <linux/irq.h>
 14#include <linux/irqdomain.h>
 15#include <linux/interrupt.h>
 16#include <linux/of.h>
 17#include <linux/mfd/stmpe.h>
 18
 19/*
 20 * These registers are modified under the irq bus lock and cached to avoid
 21 * unnecessary writes in bus_sync_unlock.
 22 */
 23enum { REG_RE, REG_FE, REG_IE };
 24
 25#define CACHE_NR_REGS	3
 26#define CACHE_NR_BANKS	(STMPE_NR_GPIOS / 8)
 27
 28struct stmpe_gpio {
 29	struct gpio_chip chip;
 30	struct stmpe *stmpe;
 31	struct device *dev;
 32	struct mutex irq_lock;
 33	struct irq_domain *domain;
 34
 35	int irq_base;
 36	unsigned norequest_mask;
 37
 38	/* Caches of interrupt control registers for bus_lock */
 39	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
 40	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
 41};
 42
 43static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
 44{
 45	return container_of(chip, struct stmpe_gpio, chip);
 46}
 47
 48static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
 49{
 50	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
 51	struct stmpe *stmpe = stmpe_gpio->stmpe;
 52	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
 53	u8 mask = 1 << (offset % 8);
 54	int ret;
 55
 56	ret = stmpe_reg_read(stmpe, reg);
 57	if (ret < 0)
 58		return ret;
 59
 60	return !!(ret & mask);
 61}
 62
 63static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
 64{
 65	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
 66	struct stmpe *stmpe = stmpe_gpio->stmpe;
 67	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
 68	u8 reg = stmpe->regs[which] - (offset / 8);
 69	u8 mask = 1 << (offset % 8);
 70
 71	/*
 72	 * Some variants have single register for gpio set/clear functionality.
 73	 * For them we need to write 0 to clear and 1 to set.
 74	 */
 75	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
 76		stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
 77	else
 78		stmpe_reg_write(stmpe, reg, mask);
 79}
 80
 81static int stmpe_gpio_direction_output(struct gpio_chip *chip,
 82					 unsigned offset, int val)
 83{
 84	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
 85	struct stmpe *stmpe = stmpe_gpio->stmpe;
 86	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
 87	u8 mask = 1 << (offset % 8);
 88
 89	stmpe_gpio_set(chip, offset, val);
 90
 91	return stmpe_set_bits(stmpe, reg, mask, mask);
 92}
 93
 94static int stmpe_gpio_direction_input(struct gpio_chip *chip,
 95					unsigned offset)
 96{
 97	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
 98	struct stmpe *stmpe = stmpe_gpio->stmpe;
 99	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
100	u8 mask = 1 << (offset % 8);
101
102	return stmpe_set_bits(stmpe, reg, mask, 0);
103}
104
105static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
106{
107	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
108
109	return irq_create_mapping(stmpe_gpio->domain, offset);
110}
111
112static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
113{
114	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
115	struct stmpe *stmpe = stmpe_gpio->stmpe;
116
117	if (stmpe_gpio->norequest_mask & (1 << offset))
118		return -EINVAL;
119
120	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
121}
122
123static struct gpio_chip template_chip = {
124	.label			= "stmpe",
125	.owner			= THIS_MODULE,
126	.direction_input	= stmpe_gpio_direction_input,
127	.get			= stmpe_gpio_get,
128	.direction_output	= stmpe_gpio_direction_output,
129	.set			= stmpe_gpio_set,
130	.to_irq			= stmpe_gpio_to_irq,
131	.request		= stmpe_gpio_request,
132	.can_sleep		= true,
133};
134
135static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
136{
137	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
138	int offset = d->hwirq;
139	int regoffset = offset / 8;
140	int mask = 1 << (offset % 8);
141
142	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
143		return -EINVAL;
144
145	/* STMPE801 doesn't have RE and FE registers */
146	if (stmpe_gpio->stmpe->partnum == STMPE801)
147		return 0;
148
149	if (type == IRQ_TYPE_EDGE_RISING)
150		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
151	else
152		stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
153
154	if (type == IRQ_TYPE_EDGE_FALLING)
155		stmpe_gpio->regs[REG_FE][regoffset] |= mask;
156	else
157		stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
158
159	return 0;
160}
161
162static void stmpe_gpio_irq_lock(struct irq_data *d)
163{
164	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
165
166	mutex_lock(&stmpe_gpio->irq_lock);
167}
168
169static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
170{
171	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
172	struct stmpe *stmpe = stmpe_gpio->stmpe;
173	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
174	static const u8 regmap[] = {
175		[REG_RE]	= STMPE_IDX_GPRER_LSB,
176		[REG_FE]	= STMPE_IDX_GPFER_LSB,
177		[REG_IE]	= STMPE_IDX_IEGPIOR_LSB,
178	};
179	int i, j;
180
181	for (i = 0; i < CACHE_NR_REGS; i++) {
182		/* STMPE801 doesn't have RE and FE registers */
183		if ((stmpe->partnum == STMPE801) &&
184				(i != REG_IE))
185			continue;
186
187		for (j = 0; j < num_banks; j++) {
188			u8 old = stmpe_gpio->oldregs[i][j];
189			u8 new = stmpe_gpio->regs[i][j];
190
191			if (new == old)
192				continue;
193
194			stmpe_gpio->oldregs[i][j] = new;
195			stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
196		}
197	}
198
199	mutex_unlock(&stmpe_gpio->irq_lock);
200}
201
202static void stmpe_gpio_irq_mask(struct irq_data *d)
203{
204	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
205	int offset = d->hwirq;
206	int regoffset = offset / 8;
207	int mask = 1 << (offset % 8);
208
209	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
210}
211
212static void stmpe_gpio_irq_unmask(struct irq_data *d)
213{
214	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
215	int offset = d->hwirq;
216	int regoffset = offset / 8;
217	int mask = 1 << (offset % 8);
218
219	stmpe_gpio->regs[REG_IE][regoffset] |= mask;
220}
221
222static struct irq_chip stmpe_gpio_irq_chip = {
223	.name			= "stmpe-gpio",
224	.irq_bus_lock		= stmpe_gpio_irq_lock,
225	.irq_bus_sync_unlock	= stmpe_gpio_irq_sync_unlock,
226	.irq_mask		= stmpe_gpio_irq_mask,
227	.irq_unmask		= stmpe_gpio_irq_unmask,
228	.irq_set_type		= stmpe_gpio_irq_set_type,
229};
230
231static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
232{
233	struct stmpe_gpio *stmpe_gpio = dev;
234	struct stmpe *stmpe = stmpe_gpio->stmpe;
235	u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
236	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
237	u8 status[num_banks];
238	int ret;
239	int i;
240
241	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
242	if (ret < 0)
243		return IRQ_NONE;
244
245	for (i = 0; i < num_banks; i++) {
246		int bank = num_banks - i - 1;
247		unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
248		unsigned int stat = status[i];
249
250		stat &= enabled;
251		if (!stat)
252			continue;
253
254		while (stat) {
255			int bit = __ffs(stat);
256			int line = bank * 8 + bit;
257			int child_irq = irq_find_mapping(stmpe_gpio->domain,
258							 line);
259
260			handle_nested_irq(child_irq);
261			stat &= ~(1 << bit);
262		}
263
264		stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
265
266		/* Edge detect register is not present on 801 */
267		if (stmpe->partnum != STMPE801)
268			stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
269					+ i, status[i]);
270	}
271
272	return IRQ_HANDLED;
273}
274
275static int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int irq,
276			      irq_hw_number_t hwirq)
277{
278	struct stmpe_gpio *stmpe_gpio = d->host_data;
 
279
280	if (!stmpe_gpio)
281		return -EINVAL;
282
283	irq_set_chip_data(irq, stmpe_gpio);
284	irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
285				 handle_simple_irq);
286	irq_set_nested_thread(irq, 1);
287#ifdef CONFIG_ARM
288	set_irq_flags(irq, IRQF_VALID);
289#else
290	irq_set_noprobe(irq);
291#endif
 
292
293	return 0;
294}
295
296static void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
297{
 
 
 
 
298#ifdef CONFIG_ARM
299	set_irq_flags(irq, 0);
300#endif
301	irq_set_chip_and_handler(irq, NULL, NULL);
302	irq_set_chip_data(irq, NULL);
303}
304
305static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
306	.unmap = stmpe_gpio_irq_unmap,
307	.map = stmpe_gpio_irq_map,
308	.xlate = irq_domain_xlate_twocell,
309};
310
311static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio,
312		struct device_node *np)
313{
314	int base = 0;
315
316	if (!np)
317		base = stmpe_gpio->irq_base;
318
319	stmpe_gpio->domain = irq_domain_add_simple(np,
320				stmpe_gpio->chip.ngpio, base,
321				&stmpe_gpio_irq_simple_ops, stmpe_gpio);
322	if (!stmpe_gpio->domain) {
323		dev_err(stmpe_gpio->dev, "failed to create irqdomain\n");
324		return -ENOSYS;
325	}
326
327	return 0;
328}
329
330static int stmpe_gpio_probe(struct platform_device *pdev)
331{
332	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
333	struct device_node *np = pdev->dev.of_node;
334	struct stmpe_gpio_platform_data *pdata;
335	struct stmpe_gpio *stmpe_gpio;
336	int ret;
337	int irq = 0;
338
339	pdata = stmpe->pdata->gpio;
340
341	irq = platform_get_irq(pdev, 0);
342
343	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
344	if (!stmpe_gpio)
345		return -ENOMEM;
346
347	mutex_init(&stmpe_gpio->irq_lock);
348
349	stmpe_gpio->dev = &pdev->dev;
350	stmpe_gpio->stmpe = stmpe;
 
 
351	stmpe_gpio->chip = template_chip;
352	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
353	stmpe_gpio->chip.dev = &pdev->dev;
354#ifdef CONFIG_OF
355	stmpe_gpio->chip.of_node = np;
356#endif
357	stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
358
359	if (pdata)
360		stmpe_gpio->norequest_mask = pdata->norequest_mask;
361	else if (np)
362		of_property_read_u32(np, "st,norequest-mask",
363				&stmpe_gpio->norequest_mask);
364
365	if (irq >= 0)
366		stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
367	else
368		dev_info(&pdev->dev,
369			"device configured in no-irq mode; "
370			"irqs are not available\n");
371
372	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
373	if (ret)
374		goto out_free;
375
376	if (irq >= 0) {
377		ret = stmpe_gpio_irq_init(stmpe_gpio, np);
378		if (ret)
379			goto out_disable;
380
381		ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
382				IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
383		if (ret) {
384			dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
385			goto out_disable;
386		}
387	}
388
389	ret = gpiochip_add(&stmpe_gpio->chip);
390	if (ret) {
391		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
392		goto out_freeirq;
393	}
394
395	if (pdata && pdata->setup)
396		pdata->setup(stmpe, stmpe_gpio->chip.base);
397
398	platform_set_drvdata(pdev, stmpe_gpio);
399
400	return 0;
401
402out_freeirq:
403	if (irq >= 0)
404		free_irq(irq, stmpe_gpio);
 
 
 
405out_disable:
406	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
407out_free:
408	kfree(stmpe_gpio);
409	return ret;
410}
411
412static int stmpe_gpio_remove(struct platform_device *pdev)
413{
414	struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
415	struct stmpe *stmpe = stmpe_gpio->stmpe;
416	struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
417	int irq = platform_get_irq(pdev, 0);
418	int ret;
419
420	if (pdata && pdata->remove)
421		pdata->remove(stmpe, stmpe_gpio->chip.base);
422
423	ret = gpiochip_remove(&stmpe_gpio->chip);
424	if (ret < 0) {
425		dev_err(stmpe_gpio->dev,
426			"unable to remove gpiochip: %d\n", ret);
427		return ret;
428	}
429
430	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
431
432	if (irq >= 0)
433		free_irq(irq, stmpe_gpio);
434
 
 
435	kfree(stmpe_gpio);
436
437	return 0;
438}
439
440static struct platform_driver stmpe_gpio_driver = {
441	.driver.name	= "stmpe-gpio",
442	.driver.owner	= THIS_MODULE,
443	.probe		= stmpe_gpio_probe,
444	.remove		= stmpe_gpio_remove,
445};
446
447static int __init stmpe_gpio_init(void)
448{
449	return platform_driver_register(&stmpe_gpio_driver);
450}
451subsys_initcall(stmpe_gpio_init);
452
453static void __exit stmpe_gpio_exit(void)
454{
455	platform_driver_unregister(&stmpe_gpio_driver);
456}
457module_exit(stmpe_gpio_exit);
458
459MODULE_LICENSE("GPL v2");
460MODULE_DESCRIPTION("STMPExxxx GPIO driver");
461MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");
v3.5.6
  1/*
  2 * Copyright (C) ST-Ericsson SA 2010
  3 *
  4 * License Terms: GNU General Public License, version 2
  5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  6 */
  7
  8#include <linux/module.h>
  9#include <linux/init.h>
 10#include <linux/platform_device.h>
 11#include <linux/slab.h>
 12#include <linux/gpio.h>
 13#include <linux/irq.h>
 
 14#include <linux/interrupt.h>
 
 15#include <linux/mfd/stmpe.h>
 16
 17/*
 18 * These registers are modified under the irq bus lock and cached to avoid
 19 * unnecessary writes in bus_sync_unlock.
 20 */
 21enum { REG_RE, REG_FE, REG_IE };
 22
 23#define CACHE_NR_REGS	3
 24#define CACHE_NR_BANKS	(STMPE_NR_GPIOS / 8)
 25
 26struct stmpe_gpio {
 27	struct gpio_chip chip;
 28	struct stmpe *stmpe;
 29	struct device *dev;
 30	struct mutex irq_lock;
 
 31
 32	int irq_base;
 33	unsigned norequest_mask;
 34
 35	/* Caches of interrupt control registers for bus_lock */
 36	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
 37	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
 38};
 39
 40static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
 41{
 42	return container_of(chip, struct stmpe_gpio, chip);
 43}
 44
 45static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
 46{
 47	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
 48	struct stmpe *stmpe = stmpe_gpio->stmpe;
 49	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
 50	u8 mask = 1 << (offset % 8);
 51	int ret;
 52
 53	ret = stmpe_reg_read(stmpe, reg);
 54	if (ret < 0)
 55		return ret;
 56
 57	return !!(ret & mask);
 58}
 59
 60static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
 61{
 62	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
 63	struct stmpe *stmpe = stmpe_gpio->stmpe;
 64	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
 65	u8 reg = stmpe->regs[which] - (offset / 8);
 66	u8 mask = 1 << (offset % 8);
 67
 68	/*
 69	 * Some variants have single register for gpio set/clear functionality.
 70	 * For them we need to write 0 to clear and 1 to set.
 71	 */
 72	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
 73		stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
 74	else
 75		stmpe_reg_write(stmpe, reg, mask);
 76}
 77
 78static int stmpe_gpio_direction_output(struct gpio_chip *chip,
 79					 unsigned offset, int val)
 80{
 81	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
 82	struct stmpe *stmpe = stmpe_gpio->stmpe;
 83	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
 84	u8 mask = 1 << (offset % 8);
 85
 86	stmpe_gpio_set(chip, offset, val);
 87
 88	return stmpe_set_bits(stmpe, reg, mask, mask);
 89}
 90
 91static int stmpe_gpio_direction_input(struct gpio_chip *chip,
 92					unsigned offset)
 93{
 94	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
 95	struct stmpe *stmpe = stmpe_gpio->stmpe;
 96	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
 97	u8 mask = 1 << (offset % 8);
 98
 99	return stmpe_set_bits(stmpe, reg, mask, 0);
100}
101
102static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
103{
104	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
105
106	return stmpe_gpio->irq_base + offset;
107}
108
109static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
110{
111	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
112	struct stmpe *stmpe = stmpe_gpio->stmpe;
113
114	if (stmpe_gpio->norequest_mask & (1 << offset))
115		return -EINVAL;
116
117	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
118}
119
120static struct gpio_chip template_chip = {
121	.label			= "stmpe",
122	.owner			= THIS_MODULE,
123	.direction_input	= stmpe_gpio_direction_input,
124	.get			= stmpe_gpio_get,
125	.direction_output	= stmpe_gpio_direction_output,
126	.set			= stmpe_gpio_set,
127	.to_irq			= stmpe_gpio_to_irq,
128	.request		= stmpe_gpio_request,
129	.can_sleep		= 1,
130};
131
132static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
133{
134	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
135	int offset = d->irq - stmpe_gpio->irq_base;
136	int regoffset = offset / 8;
137	int mask = 1 << (offset % 8);
138
139	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
140		return -EINVAL;
141
142	/* STMPE801 doesn't have RE and FE registers */
143	if (stmpe_gpio->stmpe->partnum == STMPE801)
144		return 0;
145
146	if (type == IRQ_TYPE_EDGE_RISING)
147		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
148	else
149		stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
150
151	if (type == IRQ_TYPE_EDGE_FALLING)
152		stmpe_gpio->regs[REG_FE][regoffset] |= mask;
153	else
154		stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
155
156	return 0;
157}
158
159static void stmpe_gpio_irq_lock(struct irq_data *d)
160{
161	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
162
163	mutex_lock(&stmpe_gpio->irq_lock);
164}
165
166static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
167{
168	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
169	struct stmpe *stmpe = stmpe_gpio->stmpe;
170	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
171	static const u8 regmap[] = {
172		[REG_RE]	= STMPE_IDX_GPRER_LSB,
173		[REG_FE]	= STMPE_IDX_GPFER_LSB,
174		[REG_IE]	= STMPE_IDX_IEGPIOR_LSB,
175	};
176	int i, j;
177
178	for (i = 0; i < CACHE_NR_REGS; i++) {
179		/* STMPE801 doesn't have RE and FE registers */
180		if ((stmpe->partnum == STMPE801) &&
181				(i != REG_IE))
182			continue;
183
184		for (j = 0; j < num_banks; j++) {
185			u8 old = stmpe_gpio->oldregs[i][j];
186			u8 new = stmpe_gpio->regs[i][j];
187
188			if (new == old)
189				continue;
190
191			stmpe_gpio->oldregs[i][j] = new;
192			stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
193		}
194	}
195
196	mutex_unlock(&stmpe_gpio->irq_lock);
197}
198
199static void stmpe_gpio_irq_mask(struct irq_data *d)
200{
201	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
202	int offset = d->irq - stmpe_gpio->irq_base;
203	int regoffset = offset / 8;
204	int mask = 1 << (offset % 8);
205
206	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
207}
208
209static void stmpe_gpio_irq_unmask(struct irq_data *d)
210{
211	struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
212	int offset = d->irq - stmpe_gpio->irq_base;
213	int regoffset = offset / 8;
214	int mask = 1 << (offset % 8);
215
216	stmpe_gpio->regs[REG_IE][regoffset] |= mask;
217}
218
219static struct irq_chip stmpe_gpio_irq_chip = {
220	.name			= "stmpe-gpio",
221	.irq_bus_lock		= stmpe_gpio_irq_lock,
222	.irq_bus_sync_unlock	= stmpe_gpio_irq_sync_unlock,
223	.irq_mask		= stmpe_gpio_irq_mask,
224	.irq_unmask		= stmpe_gpio_irq_unmask,
225	.irq_set_type		= stmpe_gpio_irq_set_type,
226};
227
228static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
229{
230	struct stmpe_gpio *stmpe_gpio = dev;
231	struct stmpe *stmpe = stmpe_gpio->stmpe;
232	u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
233	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
234	u8 status[num_banks];
235	int ret;
236	int i;
237
238	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
239	if (ret < 0)
240		return IRQ_NONE;
241
242	for (i = 0; i < num_banks; i++) {
243		int bank = num_banks - i - 1;
244		unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
245		unsigned int stat = status[i];
246
247		stat &= enabled;
248		if (!stat)
249			continue;
250
251		while (stat) {
252			int bit = __ffs(stat);
253			int line = bank * 8 + bit;
 
 
254
255			handle_nested_irq(stmpe_gpio->irq_base + line);
256			stat &= ~(1 << bit);
257		}
258
259		stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
260
261		/* Edge detect register is not present on 801 */
262		if (stmpe->partnum != STMPE801)
263			stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
264					+ i, status[i]);
265	}
266
267	return IRQ_HANDLED;
268}
269
270static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
 
271{
272	int base = stmpe_gpio->irq_base;
273	int irq;
274
275	for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
276		irq_set_chip_data(irq, stmpe_gpio);
277		irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
278					 handle_simple_irq);
279		irq_set_nested_thread(irq, 1);
 
 
280#ifdef CONFIG_ARM
281		set_irq_flags(irq, IRQF_VALID);
282#else
283		irq_set_noprobe(irq);
284#endif
285	}
286
287	return 0;
288}
289
290static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
291{
292	int base = stmpe_gpio->irq_base;
293	int irq;
294
295	for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
296#ifdef CONFIG_ARM
297		set_irq_flags(irq, 0);
298#endif
299		irq_set_chip_and_handler(irq, NULL, NULL);
300		irq_set_chip_data(irq, NULL);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
301	}
 
 
302}
303
304static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
305{
306	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
 
307	struct stmpe_gpio_platform_data *pdata;
308	struct stmpe_gpio *stmpe_gpio;
309	int ret;
310	int irq = 0;
311
312	pdata = stmpe->pdata->gpio;
313
314	irq = platform_get_irq(pdev, 0);
315
316	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
317	if (!stmpe_gpio)
318		return -ENOMEM;
319
320	mutex_init(&stmpe_gpio->irq_lock);
321
322	stmpe_gpio->dev = &pdev->dev;
323	stmpe_gpio->stmpe = stmpe;
324	stmpe_gpio->norequest_mask = pdata ? pdata->norequest_mask : 0;
325
326	stmpe_gpio->chip = template_chip;
327	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
328	stmpe_gpio->chip.dev = &pdev->dev;
 
 
 
329	stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
330
 
 
 
 
 
 
331	if (irq >= 0)
332		stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
333	else
334		dev_info(&pdev->dev,
335			"device configured in no-irq mode; "
336			"irqs are not available\n");
337
338	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
339	if (ret)
340		goto out_free;
341
342	if (irq >= 0) {
343		ret = stmpe_gpio_irq_init(stmpe_gpio);
344		if (ret)
345			goto out_disable;
346
347		ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
348				IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
349		if (ret) {
350			dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
351			goto out_removeirq;
352		}
353	}
354
355	ret = gpiochip_add(&stmpe_gpio->chip);
356	if (ret) {
357		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
358		goto out_freeirq;
359	}
360
361	if (pdata && pdata->setup)
362		pdata->setup(stmpe, stmpe_gpio->chip.base);
363
364	platform_set_drvdata(pdev, stmpe_gpio);
365
366	return 0;
367
368out_freeirq:
369	if (irq >= 0)
370		free_irq(irq, stmpe_gpio);
371out_removeirq:
372	if (irq >= 0)
373		stmpe_gpio_irq_remove(stmpe_gpio);
374out_disable:
375	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
376out_free:
377	kfree(stmpe_gpio);
378	return ret;
379}
380
381static int __devexit stmpe_gpio_remove(struct platform_device *pdev)
382{
383	struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
384	struct stmpe *stmpe = stmpe_gpio->stmpe;
385	struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
386	int irq = platform_get_irq(pdev, 0);
387	int ret;
388
389	if (pdata && pdata->remove)
390		pdata->remove(stmpe, stmpe_gpio->chip.base);
391
392	ret = gpiochip_remove(&stmpe_gpio->chip);
393	if (ret < 0) {
394		dev_err(stmpe_gpio->dev,
395			"unable to remove gpiochip: %d\n", ret);
396		return ret;
397	}
398
399	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
400
401	if (irq >= 0) {
402		free_irq(irq, stmpe_gpio);
403		stmpe_gpio_irq_remove(stmpe_gpio);
404	}
405	platform_set_drvdata(pdev, NULL);
406	kfree(stmpe_gpio);
407
408	return 0;
409}
410
411static struct platform_driver stmpe_gpio_driver = {
412	.driver.name	= "stmpe-gpio",
413	.driver.owner	= THIS_MODULE,
414	.probe		= stmpe_gpio_probe,
415	.remove		= __devexit_p(stmpe_gpio_remove),
416};
417
418static int __init stmpe_gpio_init(void)
419{
420	return platform_driver_register(&stmpe_gpio_driver);
421}
422subsys_initcall(stmpe_gpio_init);
423
424static void __exit stmpe_gpio_exit(void)
425{
426	platform_driver_unregister(&stmpe_gpio_driver);
427}
428module_exit(stmpe_gpio_exit);
429
430MODULE_LICENSE("GPL v2");
431MODULE_DESCRIPTION("STMPExxxx GPIO driver");
432MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");