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1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Refer to drivers/dma/imx-sdma.c
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/mm.h>
14#include <linux/interrupt.h>
15#include <linux/clk.h>
16#include <linux/wait.h>
17#include <linux/sched.h>
18#include <linux/semaphore.h>
19#include <linux/device.h>
20#include <linux/dma-mapping.h>
21#include <linux/slab.h>
22#include <linux/platform_device.h>
23#include <linux/dmaengine.h>
24#include <linux/delay.h>
25#include <linux/module.h>
26#include <linux/stmp_device.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/of_dma.h>
30#include <linux/list.h>
31
32#include <asm/irq.h>
33
34#include "dmaengine.h"
35
36/*
37 * NOTE: The term "PIO" throughout the mxs-dma implementation means
38 * PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
39 * dma can program the controller registers of peripheral devices.
40 */
41
42#define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH)
43#define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA)
44
45#define HW_APBHX_CTRL0 0x000
46#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
47#define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
48#define BP_APBH_CTRL0_RESET_CHANNEL 16
49#define HW_APBHX_CTRL1 0x010
50#define HW_APBHX_CTRL2 0x020
51#define HW_APBHX_CHANNEL_CTRL 0x030
52#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
53/*
54 * The offset of NXTCMDAR register is different per both dma type and version,
55 * while stride for each channel is all the same 0x70.
56 */
57#define HW_APBHX_CHn_NXTCMDAR(d, n) \
58 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70)
59#define HW_APBHX_CHn_SEMA(d, n) \
60 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70)
61#define HW_APBHX_CHn_BAR(d, n) \
62 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x070 : 0x130) + (n) * 0x70)
63#define HW_APBX_CHn_DEBUG1(d, n) (0x150 + (n) * 0x70)
64
65/*
66 * ccw bits definitions
67 *
68 * COMMAND: 0..1 (2)
69 * CHAIN: 2 (1)
70 * IRQ: 3 (1)
71 * NAND_LOCK: 4 (1) - not implemented
72 * NAND_WAIT4READY: 5 (1) - not implemented
73 * DEC_SEM: 6 (1)
74 * WAIT4END: 7 (1)
75 * HALT_ON_TERMINATE: 8 (1)
76 * TERMINATE_FLUSH: 9 (1)
77 * RESERVED: 10..11 (2)
78 * PIO_NUM: 12..15 (4)
79 */
80#define BP_CCW_COMMAND 0
81#define BM_CCW_COMMAND (3 << 0)
82#define CCW_CHAIN (1 << 2)
83#define CCW_IRQ (1 << 3)
84#define CCW_DEC_SEM (1 << 6)
85#define CCW_WAIT4END (1 << 7)
86#define CCW_HALT_ON_TERM (1 << 8)
87#define CCW_TERM_FLUSH (1 << 9)
88#define BP_CCW_PIO_NUM 12
89#define BM_CCW_PIO_NUM (0xf << 12)
90
91#define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
92
93#define MXS_DMA_CMD_NO_XFER 0
94#define MXS_DMA_CMD_WRITE 1
95#define MXS_DMA_CMD_READ 2
96#define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
97
98struct mxs_dma_ccw {
99 u32 next;
100 u16 bits;
101 u16 xfer_bytes;
102#define MAX_XFER_BYTES 0xff00
103 u32 bufaddr;
104#define MXS_PIO_WORDS 16
105 u32 pio_words[MXS_PIO_WORDS];
106};
107
108#define CCW_BLOCK_SIZE (4 * PAGE_SIZE)
109#define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw))
110
111struct mxs_dma_chan {
112 struct mxs_dma_engine *mxs_dma;
113 struct dma_chan chan;
114 struct dma_async_tx_descriptor desc;
115 struct tasklet_struct tasklet;
116 unsigned int chan_irq;
117 struct mxs_dma_ccw *ccw;
118 dma_addr_t ccw_phys;
119 int desc_count;
120 enum dma_status status;
121 unsigned int flags;
122 bool reset;
123#define MXS_DMA_SG_LOOP (1 << 0)
124#define MXS_DMA_USE_SEMAPHORE (1 << 1)
125};
126
127#define MXS_DMA_CHANNELS 16
128#define MXS_DMA_CHANNELS_MASK 0xffff
129
130enum mxs_dma_devtype {
131 MXS_DMA_APBH,
132 MXS_DMA_APBX,
133};
134
135enum mxs_dma_id {
136 IMX23_DMA,
137 IMX28_DMA,
138};
139
140struct mxs_dma_engine {
141 enum mxs_dma_id dev_id;
142 enum mxs_dma_devtype type;
143 void __iomem *base;
144 struct clk *clk;
145 struct dma_device dma_device;
146 struct device_dma_parameters dma_parms;
147 struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
148 struct platform_device *pdev;
149 unsigned int nr_channels;
150};
151
152struct mxs_dma_type {
153 enum mxs_dma_id id;
154 enum mxs_dma_devtype type;
155};
156
157static struct mxs_dma_type mxs_dma_types[] = {
158 {
159 .id = IMX23_DMA,
160 .type = MXS_DMA_APBH,
161 }, {
162 .id = IMX23_DMA,
163 .type = MXS_DMA_APBX,
164 }, {
165 .id = IMX28_DMA,
166 .type = MXS_DMA_APBH,
167 }, {
168 .id = IMX28_DMA,
169 .type = MXS_DMA_APBX,
170 }
171};
172
173static struct platform_device_id mxs_dma_ids[] = {
174 {
175 .name = "imx23-dma-apbh",
176 .driver_data = (kernel_ulong_t) &mxs_dma_types[0],
177 }, {
178 .name = "imx23-dma-apbx",
179 .driver_data = (kernel_ulong_t) &mxs_dma_types[1],
180 }, {
181 .name = "imx28-dma-apbh",
182 .driver_data = (kernel_ulong_t) &mxs_dma_types[2],
183 }, {
184 .name = "imx28-dma-apbx",
185 .driver_data = (kernel_ulong_t) &mxs_dma_types[3],
186 }, {
187 /* end of list */
188 }
189};
190
191static const struct of_device_id mxs_dma_dt_ids[] = {
192 { .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_ids[0], },
193 { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_ids[1], },
194 { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_ids[2], },
195 { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_ids[3], },
196 { /* sentinel */ }
197};
198MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids);
199
200static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
201{
202 return container_of(chan, struct mxs_dma_chan, chan);
203}
204
205static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
206{
207 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
208 int chan_id = mxs_chan->chan.chan_id;
209
210 /*
211 * mxs dma channel resets can cause a channel stall. To recover from a
212 * channel stall, we have to reset the whole DMA engine. To avoid this,
213 * we use cyclic DMA with semaphores, that are enhanced in
214 * mxs_dma_int_handler. To reset the channel, we can simply stop writing
215 * into the semaphore counter.
216 */
217 if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE &&
218 mxs_chan->flags & MXS_DMA_SG_LOOP) {
219 mxs_chan->reset = true;
220 } else if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma)) {
221 writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
222 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
223 } else {
224 unsigned long elapsed = 0;
225 const unsigned long max_wait = 50000; /* 50ms */
226 void __iomem *reg_dbg1 = mxs_dma->base +
227 HW_APBX_CHn_DEBUG1(mxs_dma, chan_id);
228
229 /*
230 * On i.MX28 APBX, the DMA channel can stop working if we reset
231 * the channel while it is in READ_FLUSH (0x08) state.
232 * We wait here until we leave the state. Then we trigger the
233 * reset. Waiting a maximum of 50ms, the kernel shouldn't crash
234 * because of this.
235 */
236 while ((readl(reg_dbg1) & 0xf) == 0x8 && elapsed < max_wait) {
237 udelay(100);
238 elapsed += 100;
239 }
240
241 if (elapsed >= max_wait)
242 dev_err(&mxs_chan->mxs_dma->pdev->dev,
243 "Failed waiting for the DMA channel %d to leave state READ_FLUSH, trying to reset channel in READ_FLUSH state now\n",
244 chan_id);
245
246 writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
247 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
248 }
249
250 mxs_chan->status = DMA_COMPLETE;
251}
252
253static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
254{
255 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
256 int chan_id = mxs_chan->chan.chan_id;
257
258 /* set cmd_addr up */
259 writel(mxs_chan->ccw_phys,
260 mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id));
261
262 /* write 1 to SEMA to kick off the channel */
263 if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE &&
264 mxs_chan->flags & MXS_DMA_SG_LOOP) {
265 /* A cyclic DMA consists of at least 2 segments, so initialize
266 * the semaphore with 2 so we have enough time to add 1 to the
267 * semaphore if we need to */
268 writel(2, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
269 } else {
270 writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
271 }
272 mxs_chan->reset = false;
273}
274
275static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
276{
277 mxs_chan->status = DMA_COMPLETE;
278}
279
280static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
281{
282 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
283 int chan_id = mxs_chan->chan.chan_id;
284
285 /* freeze the channel */
286 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
287 writel(1 << chan_id,
288 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
289 else
290 writel(1 << chan_id,
291 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
292
293 mxs_chan->status = DMA_PAUSED;
294}
295
296static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
297{
298 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
299 int chan_id = mxs_chan->chan.chan_id;
300
301 /* unfreeze the channel */
302 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
303 writel(1 << chan_id,
304 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
305 else
306 writel(1 << chan_id,
307 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR);
308
309 mxs_chan->status = DMA_IN_PROGRESS;
310}
311
312static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
313{
314 return dma_cookie_assign(tx);
315}
316
317static void mxs_dma_tasklet(unsigned long data)
318{
319 struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data;
320
321 if (mxs_chan->desc.callback)
322 mxs_chan->desc.callback(mxs_chan->desc.callback_param);
323}
324
325static int mxs_dma_irq_to_chan(struct mxs_dma_engine *mxs_dma, int irq)
326{
327 int i;
328
329 for (i = 0; i != mxs_dma->nr_channels; ++i)
330 if (mxs_dma->mxs_chans[i].chan_irq == irq)
331 return i;
332
333 return -EINVAL;
334}
335
336static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
337{
338 struct mxs_dma_engine *mxs_dma = dev_id;
339 struct mxs_dma_chan *mxs_chan;
340 u32 completed;
341 u32 err;
342 int chan = mxs_dma_irq_to_chan(mxs_dma, irq);
343
344 if (chan < 0)
345 return IRQ_NONE;
346
347 /* completion status */
348 completed = readl(mxs_dma->base + HW_APBHX_CTRL1);
349 completed = (completed >> chan) & 0x1;
350
351 /* Clear interrupt */
352 writel((1 << chan),
353 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
354
355 /* error status */
356 err = readl(mxs_dma->base + HW_APBHX_CTRL2);
357 err &= (1 << (MXS_DMA_CHANNELS + chan)) | (1 << chan);
358
359 /*
360 * error status bit is in the upper 16 bits, error irq bit in the lower
361 * 16 bits. We transform it into a simpler error code:
362 * err: 0x00 = no error, 0x01 = TERMINATION, 0x02 = BUS_ERROR
363 */
364 err = (err >> (MXS_DMA_CHANNELS + chan)) + (err >> chan);
365
366 /* Clear error irq */
367 writel((1 << chan),
368 mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
369
370 /*
371 * When both completion and error of termination bits set at the
372 * same time, we do not take it as an error. IOW, it only becomes
373 * an error we need to handle here in case of either it's a bus
374 * error or a termination error with no completion. 0x01 is termination
375 * error, so we can subtract err & completed to get the real error case.
376 */
377 err -= err & completed;
378
379 mxs_chan = &mxs_dma->mxs_chans[chan];
380
381 if (err) {
382 dev_dbg(mxs_dma->dma_device.dev,
383 "%s: error in channel %d\n", __func__,
384 chan);
385 mxs_chan->status = DMA_ERROR;
386 mxs_dma_reset_chan(mxs_chan);
387 } else if (mxs_chan->status != DMA_COMPLETE) {
388 if (mxs_chan->flags & MXS_DMA_SG_LOOP) {
389 mxs_chan->status = DMA_IN_PROGRESS;
390 if (mxs_chan->flags & MXS_DMA_USE_SEMAPHORE)
391 writel(1, mxs_dma->base +
392 HW_APBHX_CHn_SEMA(mxs_dma, chan));
393 } else {
394 mxs_chan->status = DMA_COMPLETE;
395 }
396 }
397
398 if (mxs_chan->status == DMA_COMPLETE) {
399 if (mxs_chan->reset)
400 return IRQ_HANDLED;
401 dma_cookie_complete(&mxs_chan->desc);
402 }
403
404 /* schedule tasklet on this channel */
405 tasklet_schedule(&mxs_chan->tasklet);
406
407 return IRQ_HANDLED;
408}
409
410static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
411{
412 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
413 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
414 int ret;
415
416 mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev,
417 CCW_BLOCK_SIZE, &mxs_chan->ccw_phys,
418 GFP_KERNEL);
419 if (!mxs_chan->ccw) {
420 ret = -ENOMEM;
421 goto err_alloc;
422 }
423
424 memset(mxs_chan->ccw, 0, CCW_BLOCK_SIZE);
425
426 if (mxs_chan->chan_irq != NO_IRQ) {
427 ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
428 0, "mxs-dma", mxs_dma);
429 if (ret)
430 goto err_irq;
431 }
432
433 ret = clk_prepare_enable(mxs_dma->clk);
434 if (ret)
435 goto err_clk;
436
437 mxs_dma_reset_chan(mxs_chan);
438
439 dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
440 mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
441
442 /* the descriptor is ready */
443 async_tx_ack(&mxs_chan->desc);
444
445 return 0;
446
447err_clk:
448 free_irq(mxs_chan->chan_irq, mxs_dma);
449err_irq:
450 dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
451 mxs_chan->ccw, mxs_chan->ccw_phys);
452err_alloc:
453 return ret;
454}
455
456static void mxs_dma_free_chan_resources(struct dma_chan *chan)
457{
458 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
459 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
460
461 mxs_dma_disable_chan(mxs_chan);
462
463 free_irq(mxs_chan->chan_irq, mxs_dma);
464
465 dma_free_coherent(mxs_dma->dma_device.dev, CCW_BLOCK_SIZE,
466 mxs_chan->ccw, mxs_chan->ccw_phys);
467
468 clk_disable_unprepare(mxs_dma->clk);
469}
470
471/*
472 * How to use the flags for ->device_prep_slave_sg() :
473 * [1] If there is only one DMA command in the DMA chain, the code should be:
474 * ......
475 * ->device_prep_slave_sg(DMA_CTRL_ACK);
476 * ......
477 * [2] If there are two DMA commands in the DMA chain, the code should be
478 * ......
479 * ->device_prep_slave_sg(0);
480 * ......
481 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
482 * ......
483 * [3] If there are more than two DMA commands in the DMA chain, the code
484 * should be:
485 * ......
486 * ->device_prep_slave_sg(0); // First
487 * ......
488 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]);
489 * ......
490 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last
491 * ......
492 */
493static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
494 struct dma_chan *chan, struct scatterlist *sgl,
495 unsigned int sg_len, enum dma_transfer_direction direction,
496 unsigned long flags, void *context)
497{
498 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
499 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
500 struct mxs_dma_ccw *ccw;
501 struct scatterlist *sg;
502 u32 i, j;
503 u32 *pio;
504 bool append = flags & DMA_PREP_INTERRUPT;
505 int idx = append ? mxs_chan->desc_count : 0;
506
507 if (mxs_chan->status == DMA_IN_PROGRESS && !append)
508 return NULL;
509
510 if (sg_len + (append ? idx : 0) > NUM_CCW) {
511 dev_err(mxs_dma->dma_device.dev,
512 "maximum number of sg exceeded: %d > %d\n",
513 sg_len, NUM_CCW);
514 goto err_out;
515 }
516
517 mxs_chan->status = DMA_IN_PROGRESS;
518 mxs_chan->flags = 0;
519
520 /*
521 * If the sg is prepared with append flag set, the sg
522 * will be appended to the last prepared sg.
523 */
524 if (append) {
525 BUG_ON(idx < 1);
526 ccw = &mxs_chan->ccw[idx - 1];
527 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
528 ccw->bits |= CCW_CHAIN;
529 ccw->bits &= ~CCW_IRQ;
530 ccw->bits &= ~CCW_DEC_SEM;
531 } else {
532 idx = 0;
533 }
534
535 if (direction == DMA_TRANS_NONE) {
536 ccw = &mxs_chan->ccw[idx++];
537 pio = (u32 *) sgl;
538
539 for (j = 0; j < sg_len;)
540 ccw->pio_words[j++] = *pio++;
541
542 ccw->bits = 0;
543 ccw->bits |= CCW_IRQ;
544 ccw->bits |= CCW_DEC_SEM;
545 if (flags & DMA_CTRL_ACK)
546 ccw->bits |= CCW_WAIT4END;
547 ccw->bits |= CCW_HALT_ON_TERM;
548 ccw->bits |= CCW_TERM_FLUSH;
549 ccw->bits |= BF_CCW(sg_len, PIO_NUM);
550 ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
551 } else {
552 for_each_sg(sgl, sg, sg_len, i) {
553 if (sg_dma_len(sg) > MAX_XFER_BYTES) {
554 dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
555 sg_dma_len(sg), MAX_XFER_BYTES);
556 goto err_out;
557 }
558
559 ccw = &mxs_chan->ccw[idx++];
560
561 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
562 ccw->bufaddr = sg->dma_address;
563 ccw->xfer_bytes = sg_dma_len(sg);
564
565 ccw->bits = 0;
566 ccw->bits |= CCW_CHAIN;
567 ccw->bits |= CCW_HALT_ON_TERM;
568 ccw->bits |= CCW_TERM_FLUSH;
569 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
570 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
571 COMMAND);
572
573 if (i + 1 == sg_len) {
574 ccw->bits &= ~CCW_CHAIN;
575 ccw->bits |= CCW_IRQ;
576 ccw->bits |= CCW_DEC_SEM;
577 if (flags & DMA_CTRL_ACK)
578 ccw->bits |= CCW_WAIT4END;
579 }
580 }
581 }
582 mxs_chan->desc_count = idx;
583
584 return &mxs_chan->desc;
585
586err_out:
587 mxs_chan->status = DMA_ERROR;
588 return NULL;
589}
590
591static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
592 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
593 size_t period_len, enum dma_transfer_direction direction,
594 unsigned long flags, void *context)
595{
596 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
597 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
598 u32 num_periods = buf_len / period_len;
599 u32 i = 0, buf = 0;
600
601 if (mxs_chan->status == DMA_IN_PROGRESS)
602 return NULL;
603
604 mxs_chan->status = DMA_IN_PROGRESS;
605 mxs_chan->flags |= MXS_DMA_SG_LOOP;
606 mxs_chan->flags |= MXS_DMA_USE_SEMAPHORE;
607
608 if (num_periods > NUM_CCW) {
609 dev_err(mxs_dma->dma_device.dev,
610 "maximum number of sg exceeded: %d > %d\n",
611 num_periods, NUM_CCW);
612 goto err_out;
613 }
614
615 if (period_len > MAX_XFER_BYTES) {
616 dev_err(mxs_dma->dma_device.dev,
617 "maximum period size exceeded: %d > %d\n",
618 period_len, MAX_XFER_BYTES);
619 goto err_out;
620 }
621
622 while (buf < buf_len) {
623 struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
624
625 if (i + 1 == num_periods)
626 ccw->next = mxs_chan->ccw_phys;
627 else
628 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);
629
630 ccw->bufaddr = dma_addr;
631 ccw->xfer_bytes = period_len;
632
633 ccw->bits = 0;
634 ccw->bits |= CCW_CHAIN;
635 ccw->bits |= CCW_IRQ;
636 ccw->bits |= CCW_HALT_ON_TERM;
637 ccw->bits |= CCW_TERM_FLUSH;
638 ccw->bits |= CCW_DEC_SEM;
639 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
640 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
641
642 dma_addr += period_len;
643 buf += period_len;
644
645 i++;
646 }
647 mxs_chan->desc_count = i;
648
649 return &mxs_chan->desc;
650
651err_out:
652 mxs_chan->status = DMA_ERROR;
653 return NULL;
654}
655
656static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
657 unsigned long arg)
658{
659 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
660 int ret = 0;
661
662 switch (cmd) {
663 case DMA_TERMINATE_ALL:
664 mxs_dma_reset_chan(mxs_chan);
665 mxs_dma_disable_chan(mxs_chan);
666 break;
667 case DMA_PAUSE:
668 mxs_dma_pause_chan(mxs_chan);
669 break;
670 case DMA_RESUME:
671 mxs_dma_resume_chan(mxs_chan);
672 break;
673 default:
674 ret = -ENOSYS;
675 }
676
677 return ret;
678}
679
680static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
681 dma_cookie_t cookie, struct dma_tx_state *txstate)
682{
683 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
684 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
685 u32 residue = 0;
686
687 if (mxs_chan->status == DMA_IN_PROGRESS &&
688 mxs_chan->flags & MXS_DMA_SG_LOOP) {
689 struct mxs_dma_ccw *last_ccw;
690 u32 bar;
691
692 last_ccw = &mxs_chan->ccw[mxs_chan->desc_count - 1];
693 residue = last_ccw->xfer_bytes + last_ccw->bufaddr;
694
695 bar = readl(mxs_dma->base +
696 HW_APBHX_CHn_BAR(mxs_dma, chan->chan_id));
697 residue -= bar;
698 }
699
700 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
701 residue);
702
703 return mxs_chan->status;
704}
705
706static void mxs_dma_issue_pending(struct dma_chan *chan)
707{
708 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
709
710 mxs_dma_enable_chan(mxs_chan);
711}
712
713static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
714{
715 int ret;
716
717 ret = clk_prepare_enable(mxs_dma->clk);
718 if (ret)
719 return ret;
720
721 ret = stmp_reset_block(mxs_dma->base);
722 if (ret)
723 goto err_out;
724
725 /* enable apbh burst */
726 if (dma_is_apbh(mxs_dma)) {
727 writel(BM_APBH_CTRL0_APB_BURST_EN,
728 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
729 writel(BM_APBH_CTRL0_APB_BURST8_EN,
730 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
731 }
732
733 /* enable irq for all the channels */
734 writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
735 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
736
737err_out:
738 clk_disable_unprepare(mxs_dma->clk);
739 return ret;
740}
741
742struct mxs_dma_filter_param {
743 struct device_node *of_node;
744 unsigned int chan_id;
745};
746
747static bool mxs_dma_filter_fn(struct dma_chan *chan, void *fn_param)
748{
749 struct mxs_dma_filter_param *param = fn_param;
750 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
751 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
752 int chan_irq;
753
754 if (mxs_dma->dma_device.dev->of_node != param->of_node)
755 return false;
756
757 if (chan->chan_id != param->chan_id)
758 return false;
759
760 chan_irq = platform_get_irq(mxs_dma->pdev, param->chan_id);
761 if (chan_irq < 0)
762 return false;
763
764 mxs_chan->chan_irq = chan_irq;
765
766 return true;
767}
768
769static struct dma_chan *mxs_dma_xlate(struct of_phandle_args *dma_spec,
770 struct of_dma *ofdma)
771{
772 struct mxs_dma_engine *mxs_dma = ofdma->of_dma_data;
773 dma_cap_mask_t mask = mxs_dma->dma_device.cap_mask;
774 struct mxs_dma_filter_param param;
775
776 if (dma_spec->args_count != 1)
777 return NULL;
778
779 param.of_node = ofdma->of_node;
780 param.chan_id = dma_spec->args[0];
781
782 if (param.chan_id >= mxs_dma->nr_channels)
783 return NULL;
784
785 return dma_request_channel(mask, mxs_dma_filter_fn, ¶m);
786}
787
788static int __init mxs_dma_probe(struct platform_device *pdev)
789{
790 struct device_node *np = pdev->dev.of_node;
791 const struct platform_device_id *id_entry;
792 const struct of_device_id *of_id;
793 const struct mxs_dma_type *dma_type;
794 struct mxs_dma_engine *mxs_dma;
795 struct resource *iores;
796 int ret, i;
797
798 mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL);
799 if (!mxs_dma)
800 return -ENOMEM;
801
802 ret = of_property_read_u32(np, "dma-channels", &mxs_dma->nr_channels);
803 if (ret) {
804 dev_err(&pdev->dev, "failed to read dma-channels\n");
805 return ret;
806 }
807
808 of_id = of_match_device(mxs_dma_dt_ids, &pdev->dev);
809 if (of_id)
810 id_entry = of_id->data;
811 else
812 id_entry = platform_get_device_id(pdev);
813
814 dma_type = (struct mxs_dma_type *)id_entry->driver_data;
815 mxs_dma->type = dma_type->type;
816 mxs_dma->dev_id = dma_type->id;
817
818 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
819 mxs_dma->base = devm_ioremap_resource(&pdev->dev, iores);
820 if (IS_ERR(mxs_dma->base))
821 return PTR_ERR(mxs_dma->base);
822
823 mxs_dma->clk = devm_clk_get(&pdev->dev, NULL);
824 if (IS_ERR(mxs_dma->clk))
825 return PTR_ERR(mxs_dma->clk);
826
827 dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
828 dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
829
830 INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
831
832 /* Initialize channel parameters */
833 for (i = 0; i < MXS_DMA_CHANNELS; i++) {
834 struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
835
836 mxs_chan->mxs_dma = mxs_dma;
837 mxs_chan->chan.device = &mxs_dma->dma_device;
838 dma_cookie_init(&mxs_chan->chan);
839
840 tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
841 (unsigned long) mxs_chan);
842
843
844 /* Add the channel to mxs_chan list */
845 list_add_tail(&mxs_chan->chan.device_node,
846 &mxs_dma->dma_device.channels);
847 }
848
849 ret = mxs_dma_init(mxs_dma);
850 if (ret)
851 return ret;
852
853 mxs_dma->pdev = pdev;
854 mxs_dma->dma_device.dev = &pdev->dev;
855
856 /* mxs_dma gets 65535 bytes maximum sg size */
857 mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
858 dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
859
860 mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
861 mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
862 mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
863 mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
864 mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
865 mxs_dma->dma_device.device_control = mxs_dma_control;
866 mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending;
867
868 ret = dma_async_device_register(&mxs_dma->dma_device);
869 if (ret) {
870 dev_err(mxs_dma->dma_device.dev, "unable to register\n");
871 return ret;
872 }
873
874 ret = of_dma_controller_register(np, mxs_dma_xlate, mxs_dma);
875 if (ret) {
876 dev_err(mxs_dma->dma_device.dev,
877 "failed to register controller\n");
878 dma_async_device_unregister(&mxs_dma->dma_device);
879 }
880
881 dev_info(mxs_dma->dma_device.dev, "initialized\n");
882
883 return 0;
884}
885
886static struct platform_driver mxs_dma_driver = {
887 .driver = {
888 .name = "mxs-dma",
889 .of_match_table = mxs_dma_dt_ids,
890 },
891 .id_table = mxs_dma_ids,
892};
893
894static int __init mxs_dma_module_init(void)
895{
896 return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
897}
898subsys_initcall(mxs_dma_module_init);
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Refer to drivers/dma/imx-sdma.c
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/mm.h>
14#include <linux/interrupt.h>
15#include <linux/clk.h>
16#include <linux/wait.h>
17#include <linux/sched.h>
18#include <linux/semaphore.h>
19#include <linux/device.h>
20#include <linux/dma-mapping.h>
21#include <linux/slab.h>
22#include <linux/platform_device.h>
23#include <linux/dmaengine.h>
24#include <linux/delay.h>
25#include <linux/module.h>
26#include <linux/fsl/mxs-dma.h>
27#include <linux/stmp_device.h>
28#include <linux/of.h>
29#include <linux/of_device.h>
30
31#include <asm/irq.h>
32#include <mach/mxs.h>
33
34#include "dmaengine.h"
35
36/*
37 * NOTE: The term "PIO" throughout the mxs-dma implementation means
38 * PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
39 * dma can program the controller registers of peripheral devices.
40 */
41
42#define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH)
43#define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA)
44
45#define HW_APBHX_CTRL0 0x000
46#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
47#define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
48#define BP_APBH_CTRL0_RESET_CHANNEL 16
49#define HW_APBHX_CTRL1 0x010
50#define HW_APBHX_CTRL2 0x020
51#define HW_APBHX_CHANNEL_CTRL 0x030
52#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
53/*
54 * The offset of NXTCMDAR register is different per both dma type and version,
55 * while stride for each channel is all the same 0x70.
56 */
57#define HW_APBHX_CHn_NXTCMDAR(d, n) \
58 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70)
59#define HW_APBHX_CHn_SEMA(d, n) \
60 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70)
61
62/*
63 * ccw bits definitions
64 *
65 * COMMAND: 0..1 (2)
66 * CHAIN: 2 (1)
67 * IRQ: 3 (1)
68 * NAND_LOCK: 4 (1) - not implemented
69 * NAND_WAIT4READY: 5 (1) - not implemented
70 * DEC_SEM: 6 (1)
71 * WAIT4END: 7 (1)
72 * HALT_ON_TERMINATE: 8 (1)
73 * TERMINATE_FLUSH: 9 (1)
74 * RESERVED: 10..11 (2)
75 * PIO_NUM: 12..15 (4)
76 */
77#define BP_CCW_COMMAND 0
78#define BM_CCW_COMMAND (3 << 0)
79#define CCW_CHAIN (1 << 2)
80#define CCW_IRQ (1 << 3)
81#define CCW_DEC_SEM (1 << 6)
82#define CCW_WAIT4END (1 << 7)
83#define CCW_HALT_ON_TERM (1 << 8)
84#define CCW_TERM_FLUSH (1 << 9)
85#define BP_CCW_PIO_NUM 12
86#define BM_CCW_PIO_NUM (0xf << 12)
87
88#define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
89
90#define MXS_DMA_CMD_NO_XFER 0
91#define MXS_DMA_CMD_WRITE 1
92#define MXS_DMA_CMD_READ 2
93#define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
94
95struct mxs_dma_ccw {
96 u32 next;
97 u16 bits;
98 u16 xfer_bytes;
99#define MAX_XFER_BYTES 0xff00
100 u32 bufaddr;
101#define MXS_PIO_WORDS 16
102 u32 pio_words[MXS_PIO_WORDS];
103};
104
105#define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw))
106
107struct mxs_dma_chan {
108 struct mxs_dma_engine *mxs_dma;
109 struct dma_chan chan;
110 struct dma_async_tx_descriptor desc;
111 struct tasklet_struct tasklet;
112 int chan_irq;
113 struct mxs_dma_ccw *ccw;
114 dma_addr_t ccw_phys;
115 int desc_count;
116 enum dma_status status;
117 unsigned int flags;
118#define MXS_DMA_SG_LOOP (1 << 0)
119};
120
121#define MXS_DMA_CHANNELS 16
122#define MXS_DMA_CHANNELS_MASK 0xffff
123
124enum mxs_dma_devtype {
125 MXS_DMA_APBH,
126 MXS_DMA_APBX,
127};
128
129enum mxs_dma_id {
130 IMX23_DMA,
131 IMX28_DMA,
132};
133
134struct mxs_dma_engine {
135 enum mxs_dma_id dev_id;
136 enum mxs_dma_devtype type;
137 void __iomem *base;
138 struct clk *clk;
139 struct dma_device dma_device;
140 struct device_dma_parameters dma_parms;
141 struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
142};
143
144struct mxs_dma_type {
145 enum mxs_dma_id id;
146 enum mxs_dma_devtype type;
147};
148
149static struct mxs_dma_type mxs_dma_types[] = {
150 {
151 .id = IMX23_DMA,
152 .type = MXS_DMA_APBH,
153 }, {
154 .id = IMX23_DMA,
155 .type = MXS_DMA_APBX,
156 }, {
157 .id = IMX28_DMA,
158 .type = MXS_DMA_APBH,
159 }, {
160 .id = IMX28_DMA,
161 .type = MXS_DMA_APBX,
162 }
163};
164
165static struct platform_device_id mxs_dma_ids[] = {
166 {
167 .name = "imx23-dma-apbh",
168 .driver_data = (kernel_ulong_t) &mxs_dma_types[0],
169 }, {
170 .name = "imx23-dma-apbx",
171 .driver_data = (kernel_ulong_t) &mxs_dma_types[1],
172 }, {
173 .name = "imx28-dma-apbh",
174 .driver_data = (kernel_ulong_t) &mxs_dma_types[2],
175 }, {
176 .name = "imx28-dma-apbx",
177 .driver_data = (kernel_ulong_t) &mxs_dma_types[3],
178 }, {
179 /* end of list */
180 }
181};
182
183static const struct of_device_id mxs_dma_dt_ids[] = {
184 { .compatible = "fsl,imx23-dma-apbh", .data = &mxs_dma_ids[0], },
185 { .compatible = "fsl,imx23-dma-apbx", .data = &mxs_dma_ids[1], },
186 { .compatible = "fsl,imx28-dma-apbh", .data = &mxs_dma_ids[2], },
187 { .compatible = "fsl,imx28-dma-apbx", .data = &mxs_dma_ids[3], },
188 { /* sentinel */ }
189};
190MODULE_DEVICE_TABLE(of, mxs_dma_dt_ids);
191
192static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
193{
194 return container_of(chan, struct mxs_dma_chan, chan);
195}
196
197int mxs_dma_is_apbh(struct dma_chan *chan)
198{
199 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
200 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
201
202 return dma_is_apbh(mxs_dma);
203}
204
205int mxs_dma_is_apbx(struct dma_chan *chan)
206{
207 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
208 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
209
210 return !dma_is_apbh(mxs_dma);
211}
212
213static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
214{
215 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
216 int chan_id = mxs_chan->chan.chan_id;
217
218 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
219 writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
220 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
221 else
222 writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
223 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
224}
225
226static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
227{
228 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
229 int chan_id = mxs_chan->chan.chan_id;
230
231 /* set cmd_addr up */
232 writel(mxs_chan->ccw_phys,
233 mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(mxs_dma, chan_id));
234
235 /* write 1 to SEMA to kick off the channel */
236 writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(mxs_dma, chan_id));
237}
238
239static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
240{
241 mxs_chan->status = DMA_SUCCESS;
242}
243
244static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
245{
246 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
247 int chan_id = mxs_chan->chan.chan_id;
248
249 /* freeze the channel */
250 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
251 writel(1 << chan_id,
252 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
253 else
254 writel(1 << chan_id,
255 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
256
257 mxs_chan->status = DMA_PAUSED;
258}
259
260static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
261{
262 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
263 int chan_id = mxs_chan->chan.chan_id;
264
265 /* unfreeze the channel */
266 if (dma_is_apbh(mxs_dma) && apbh_is_old(mxs_dma))
267 writel(1 << chan_id,
268 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
269 else
270 writel(1 << chan_id,
271 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_CLR);
272
273 mxs_chan->status = DMA_IN_PROGRESS;
274}
275
276static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
277{
278 return dma_cookie_assign(tx);
279}
280
281static void mxs_dma_tasklet(unsigned long data)
282{
283 struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data;
284
285 if (mxs_chan->desc.callback)
286 mxs_chan->desc.callback(mxs_chan->desc.callback_param);
287}
288
289static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
290{
291 struct mxs_dma_engine *mxs_dma = dev_id;
292 u32 stat1, stat2;
293
294 /* completion status */
295 stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1);
296 stat1 &= MXS_DMA_CHANNELS_MASK;
297 writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
298
299 /* error status */
300 stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2);
301 writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
302
303 /*
304 * When both completion and error of termination bits set at the
305 * same time, we do not take it as an error. IOW, it only becomes
306 * an error we need to handle here in case of either it's (1) a bus
307 * error or (2) a termination error with no completion.
308 */
309 stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */
310 (~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */
311
312 /* combine error and completion status for checking */
313 stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1;
314 while (stat1) {
315 int channel = fls(stat1) - 1;
316 struct mxs_dma_chan *mxs_chan =
317 &mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS];
318
319 if (channel >= MXS_DMA_CHANNELS) {
320 dev_dbg(mxs_dma->dma_device.dev,
321 "%s: error in channel %d\n", __func__,
322 channel - MXS_DMA_CHANNELS);
323 mxs_chan->status = DMA_ERROR;
324 mxs_dma_reset_chan(mxs_chan);
325 } else {
326 if (mxs_chan->flags & MXS_DMA_SG_LOOP)
327 mxs_chan->status = DMA_IN_PROGRESS;
328 else
329 mxs_chan->status = DMA_SUCCESS;
330 }
331
332 stat1 &= ~(1 << channel);
333
334 if (mxs_chan->status == DMA_SUCCESS)
335 dma_cookie_complete(&mxs_chan->desc);
336
337 /* schedule tasklet on this channel */
338 tasklet_schedule(&mxs_chan->tasklet);
339 }
340
341 return IRQ_HANDLED;
342}
343
344static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
345{
346 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
347 struct mxs_dma_data *data = chan->private;
348 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
349 int ret;
350
351 if (!data)
352 return -EINVAL;
353
354 mxs_chan->chan_irq = data->chan_irq;
355
356 mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
357 &mxs_chan->ccw_phys, GFP_KERNEL);
358 if (!mxs_chan->ccw) {
359 ret = -ENOMEM;
360 goto err_alloc;
361 }
362
363 memset(mxs_chan->ccw, 0, PAGE_SIZE);
364
365 if (mxs_chan->chan_irq != NO_IRQ) {
366 ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
367 0, "mxs-dma", mxs_dma);
368 if (ret)
369 goto err_irq;
370 }
371
372 ret = clk_prepare_enable(mxs_dma->clk);
373 if (ret)
374 goto err_clk;
375
376 mxs_dma_reset_chan(mxs_chan);
377
378 dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
379 mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
380
381 /* the descriptor is ready */
382 async_tx_ack(&mxs_chan->desc);
383
384 return 0;
385
386err_clk:
387 free_irq(mxs_chan->chan_irq, mxs_dma);
388err_irq:
389 dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
390 mxs_chan->ccw, mxs_chan->ccw_phys);
391err_alloc:
392 return ret;
393}
394
395static void mxs_dma_free_chan_resources(struct dma_chan *chan)
396{
397 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
398 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
399
400 mxs_dma_disable_chan(mxs_chan);
401
402 free_irq(mxs_chan->chan_irq, mxs_dma);
403
404 dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
405 mxs_chan->ccw, mxs_chan->ccw_phys);
406
407 clk_disable_unprepare(mxs_dma->clk);
408}
409
410/*
411 * How to use the flags for ->device_prep_slave_sg() :
412 * [1] If there is only one DMA command in the DMA chain, the code should be:
413 * ......
414 * ->device_prep_slave_sg(DMA_CTRL_ACK);
415 * ......
416 * [2] If there are two DMA commands in the DMA chain, the code should be
417 * ......
418 * ->device_prep_slave_sg(0);
419 * ......
420 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
421 * ......
422 * [3] If there are more than two DMA commands in the DMA chain, the code
423 * should be:
424 * ......
425 * ->device_prep_slave_sg(0); // First
426 * ......
427 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]);
428 * ......
429 * ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last
430 * ......
431 */
432static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
433 struct dma_chan *chan, struct scatterlist *sgl,
434 unsigned int sg_len, enum dma_transfer_direction direction,
435 unsigned long flags, void *context)
436{
437 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
438 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
439 struct mxs_dma_ccw *ccw;
440 struct scatterlist *sg;
441 int i, j;
442 u32 *pio;
443 bool append = flags & DMA_PREP_INTERRUPT;
444 int idx = append ? mxs_chan->desc_count : 0;
445
446 if (mxs_chan->status == DMA_IN_PROGRESS && !append)
447 return NULL;
448
449 if (sg_len + (append ? idx : 0) > NUM_CCW) {
450 dev_err(mxs_dma->dma_device.dev,
451 "maximum number of sg exceeded: %d > %d\n",
452 sg_len, NUM_CCW);
453 goto err_out;
454 }
455
456 mxs_chan->status = DMA_IN_PROGRESS;
457 mxs_chan->flags = 0;
458
459 /*
460 * If the sg is prepared with append flag set, the sg
461 * will be appended to the last prepared sg.
462 */
463 if (append) {
464 BUG_ON(idx < 1);
465 ccw = &mxs_chan->ccw[idx - 1];
466 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
467 ccw->bits |= CCW_CHAIN;
468 ccw->bits &= ~CCW_IRQ;
469 ccw->bits &= ~CCW_DEC_SEM;
470 } else {
471 idx = 0;
472 }
473
474 if (direction == DMA_TRANS_NONE) {
475 ccw = &mxs_chan->ccw[idx++];
476 pio = (u32 *) sgl;
477
478 for (j = 0; j < sg_len;)
479 ccw->pio_words[j++] = *pio++;
480
481 ccw->bits = 0;
482 ccw->bits |= CCW_IRQ;
483 ccw->bits |= CCW_DEC_SEM;
484 if (flags & DMA_CTRL_ACK)
485 ccw->bits |= CCW_WAIT4END;
486 ccw->bits |= CCW_HALT_ON_TERM;
487 ccw->bits |= CCW_TERM_FLUSH;
488 ccw->bits |= BF_CCW(sg_len, PIO_NUM);
489 ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
490 } else {
491 for_each_sg(sgl, sg, sg_len, i) {
492 if (sg_dma_len(sg) > MAX_XFER_BYTES) {
493 dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
494 sg_dma_len(sg), MAX_XFER_BYTES);
495 goto err_out;
496 }
497
498 ccw = &mxs_chan->ccw[idx++];
499
500 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
501 ccw->bufaddr = sg->dma_address;
502 ccw->xfer_bytes = sg_dma_len(sg);
503
504 ccw->bits = 0;
505 ccw->bits |= CCW_CHAIN;
506 ccw->bits |= CCW_HALT_ON_TERM;
507 ccw->bits |= CCW_TERM_FLUSH;
508 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
509 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
510 COMMAND);
511
512 if (i + 1 == sg_len) {
513 ccw->bits &= ~CCW_CHAIN;
514 ccw->bits |= CCW_IRQ;
515 ccw->bits |= CCW_DEC_SEM;
516 if (flags & DMA_CTRL_ACK)
517 ccw->bits |= CCW_WAIT4END;
518 }
519 }
520 }
521 mxs_chan->desc_count = idx;
522
523 return &mxs_chan->desc;
524
525err_out:
526 mxs_chan->status = DMA_ERROR;
527 return NULL;
528}
529
530static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
531 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
532 size_t period_len, enum dma_transfer_direction direction,
533 void *context)
534{
535 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
536 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
537 int num_periods = buf_len / period_len;
538 int i = 0, buf = 0;
539
540 if (mxs_chan->status == DMA_IN_PROGRESS)
541 return NULL;
542
543 mxs_chan->status = DMA_IN_PROGRESS;
544 mxs_chan->flags |= MXS_DMA_SG_LOOP;
545
546 if (num_periods > NUM_CCW) {
547 dev_err(mxs_dma->dma_device.dev,
548 "maximum number of sg exceeded: %d > %d\n",
549 num_periods, NUM_CCW);
550 goto err_out;
551 }
552
553 if (period_len > MAX_XFER_BYTES) {
554 dev_err(mxs_dma->dma_device.dev,
555 "maximum period size exceeded: %d > %d\n",
556 period_len, MAX_XFER_BYTES);
557 goto err_out;
558 }
559
560 while (buf < buf_len) {
561 struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
562
563 if (i + 1 == num_periods)
564 ccw->next = mxs_chan->ccw_phys;
565 else
566 ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);
567
568 ccw->bufaddr = dma_addr;
569 ccw->xfer_bytes = period_len;
570
571 ccw->bits = 0;
572 ccw->bits |= CCW_CHAIN;
573 ccw->bits |= CCW_IRQ;
574 ccw->bits |= CCW_HALT_ON_TERM;
575 ccw->bits |= CCW_TERM_FLUSH;
576 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
577 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
578
579 dma_addr += period_len;
580 buf += period_len;
581
582 i++;
583 }
584 mxs_chan->desc_count = i;
585
586 return &mxs_chan->desc;
587
588err_out:
589 mxs_chan->status = DMA_ERROR;
590 return NULL;
591}
592
593static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
594 unsigned long arg)
595{
596 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
597 int ret = 0;
598
599 switch (cmd) {
600 case DMA_TERMINATE_ALL:
601 mxs_dma_reset_chan(mxs_chan);
602 mxs_dma_disable_chan(mxs_chan);
603 break;
604 case DMA_PAUSE:
605 mxs_dma_pause_chan(mxs_chan);
606 break;
607 case DMA_RESUME:
608 mxs_dma_resume_chan(mxs_chan);
609 break;
610 default:
611 ret = -ENOSYS;
612 }
613
614 return ret;
615}
616
617static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
618 dma_cookie_t cookie, struct dma_tx_state *txstate)
619{
620 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
621 dma_cookie_t last_used;
622
623 last_used = chan->cookie;
624 dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);
625
626 return mxs_chan->status;
627}
628
629static void mxs_dma_issue_pending(struct dma_chan *chan)
630{
631 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
632
633 mxs_dma_enable_chan(mxs_chan);
634}
635
636static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
637{
638 int ret;
639
640 ret = clk_prepare_enable(mxs_dma->clk);
641 if (ret)
642 return ret;
643
644 ret = stmp_reset_block(mxs_dma->base);
645 if (ret)
646 goto err_out;
647
648 /* enable apbh burst */
649 if (dma_is_apbh(mxs_dma)) {
650 writel(BM_APBH_CTRL0_APB_BURST_EN,
651 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
652 writel(BM_APBH_CTRL0_APB_BURST8_EN,
653 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
654 }
655
656 /* enable irq for all the channels */
657 writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
658 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
659
660err_out:
661 clk_disable_unprepare(mxs_dma->clk);
662 return ret;
663}
664
665static int __init mxs_dma_probe(struct platform_device *pdev)
666{
667 const struct platform_device_id *id_entry;
668 const struct of_device_id *of_id;
669 const struct mxs_dma_type *dma_type;
670 struct mxs_dma_engine *mxs_dma;
671 struct resource *iores;
672 int ret, i;
673
674 mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL);
675 if (!mxs_dma)
676 return -ENOMEM;
677
678 of_id = of_match_device(mxs_dma_dt_ids, &pdev->dev);
679 if (of_id)
680 id_entry = of_id->data;
681 else
682 id_entry = platform_get_device_id(pdev);
683
684 dma_type = (struct mxs_dma_type *)id_entry->driver_data;
685 mxs_dma->type = dma_type->type;
686 mxs_dma->dev_id = dma_type->id;
687
688 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
689
690 if (!request_mem_region(iores->start, resource_size(iores),
691 pdev->name)) {
692 ret = -EBUSY;
693 goto err_request_region;
694 }
695
696 mxs_dma->base = ioremap(iores->start, resource_size(iores));
697 if (!mxs_dma->base) {
698 ret = -ENOMEM;
699 goto err_ioremap;
700 }
701
702 mxs_dma->clk = clk_get(&pdev->dev, NULL);
703 if (IS_ERR(mxs_dma->clk)) {
704 ret = PTR_ERR(mxs_dma->clk);
705 goto err_clk;
706 }
707
708 dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
709 dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
710
711 INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
712
713 /* Initialize channel parameters */
714 for (i = 0; i < MXS_DMA_CHANNELS; i++) {
715 struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
716
717 mxs_chan->mxs_dma = mxs_dma;
718 mxs_chan->chan.device = &mxs_dma->dma_device;
719 dma_cookie_init(&mxs_chan->chan);
720
721 tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
722 (unsigned long) mxs_chan);
723
724
725 /* Add the channel to mxs_chan list */
726 list_add_tail(&mxs_chan->chan.device_node,
727 &mxs_dma->dma_device.channels);
728 }
729
730 ret = mxs_dma_init(mxs_dma);
731 if (ret)
732 goto err_init;
733
734 mxs_dma->dma_device.dev = &pdev->dev;
735
736 /* mxs_dma gets 65535 bytes maximum sg size */
737 mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
738 dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
739
740 mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
741 mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
742 mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
743 mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
744 mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
745 mxs_dma->dma_device.device_control = mxs_dma_control;
746 mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending;
747
748 ret = dma_async_device_register(&mxs_dma->dma_device);
749 if (ret) {
750 dev_err(mxs_dma->dma_device.dev, "unable to register\n");
751 goto err_init;
752 }
753
754 dev_info(mxs_dma->dma_device.dev, "initialized\n");
755
756 return 0;
757
758err_init:
759 clk_put(mxs_dma->clk);
760err_clk:
761 iounmap(mxs_dma->base);
762err_ioremap:
763 release_mem_region(iores->start, resource_size(iores));
764err_request_region:
765 kfree(mxs_dma);
766 return ret;
767}
768
769static struct platform_driver mxs_dma_driver = {
770 .driver = {
771 .name = "mxs-dma",
772 .of_match_table = mxs_dma_dt_ids,
773 },
774 .id_table = mxs_dma_ids,
775};
776
777static int __init mxs_dma_module_init(void)
778{
779 return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
780}
781subsys_initcall(mxs_dma_module_init);