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1/*
2 * SH7722 Setup
3 *
4 * Copyright (C) 2006 - 2008 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/mm.h>
12#include <linux/platform_device.h>
13#include <linux/serial.h>
14#include <linux/serial_sci.h>
15#include <linux/sh_dma.h>
16#include <linux/sh_timer.h>
17#include <linux/sh_intc.h>
18#include <linux/uio_driver.h>
19#include <linux/usb/m66592.h>
20
21#include <asm/clock.h>
22#include <asm/mmzone.h>
23#include <asm/siu.h>
24
25#include <cpu/dma-register.h>
26#include <cpu/sh7722.h>
27#include <cpu/serial.h>
28
29static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
30 {
31 .slave_id = SHDMA_SLAVE_SCIF0_TX,
32 .addr = 0xffe0000c,
33 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
34 .mid_rid = 0x21,
35 }, {
36 .slave_id = SHDMA_SLAVE_SCIF0_RX,
37 .addr = 0xffe00014,
38 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
39 .mid_rid = 0x22,
40 }, {
41 .slave_id = SHDMA_SLAVE_SCIF1_TX,
42 .addr = 0xffe1000c,
43 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
44 .mid_rid = 0x25,
45 }, {
46 .slave_id = SHDMA_SLAVE_SCIF1_RX,
47 .addr = 0xffe10014,
48 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
49 .mid_rid = 0x26,
50 }, {
51 .slave_id = SHDMA_SLAVE_SCIF2_TX,
52 .addr = 0xffe2000c,
53 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
54 .mid_rid = 0x29,
55 }, {
56 .slave_id = SHDMA_SLAVE_SCIF2_RX,
57 .addr = 0xffe20014,
58 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
59 .mid_rid = 0x2a,
60 }, {
61 .slave_id = SHDMA_SLAVE_SIUA_TX,
62 .addr = 0xa454c098,
63 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
64 .mid_rid = 0xb1,
65 }, {
66 .slave_id = SHDMA_SLAVE_SIUA_RX,
67 .addr = 0xa454c090,
68 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
69 .mid_rid = 0xb2,
70 }, {
71 .slave_id = SHDMA_SLAVE_SIUB_TX,
72 .addr = 0xa454c09c,
73 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
74 .mid_rid = 0xb5,
75 }, {
76 .slave_id = SHDMA_SLAVE_SIUB_RX,
77 .addr = 0xa454c094,
78 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
79 .mid_rid = 0xb6,
80 }, {
81 .slave_id = SHDMA_SLAVE_SDHI0_TX,
82 .addr = 0x04ce0030,
83 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
84 .mid_rid = 0xc1,
85 }, {
86 .slave_id = SHDMA_SLAVE_SDHI0_RX,
87 .addr = 0x04ce0030,
88 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
89 .mid_rid = 0xc2,
90 },
91};
92
93static const struct sh_dmae_channel sh7722_dmae_channels[] = {
94 {
95 .offset = 0,
96 .dmars = 0,
97 .dmars_bit = 0,
98 }, {
99 .offset = 0x10,
100 .dmars = 0,
101 .dmars_bit = 8,
102 }, {
103 .offset = 0x20,
104 .dmars = 4,
105 .dmars_bit = 0,
106 }, {
107 .offset = 0x30,
108 .dmars = 4,
109 .dmars_bit = 8,
110 }, {
111 .offset = 0x50,
112 .dmars = 8,
113 .dmars_bit = 0,
114 }, {
115 .offset = 0x60,
116 .dmars = 8,
117 .dmars_bit = 8,
118 }
119};
120
121static const unsigned int ts_shift[] = TS_SHIFT;
122
123static struct sh_dmae_pdata dma_platform_data = {
124 .slave = sh7722_dmae_slaves,
125 .slave_num = ARRAY_SIZE(sh7722_dmae_slaves),
126 .channel = sh7722_dmae_channels,
127 .channel_num = ARRAY_SIZE(sh7722_dmae_channels),
128 .ts_low_shift = CHCR_TS_LOW_SHIFT,
129 .ts_low_mask = CHCR_TS_LOW_MASK,
130 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
131 .ts_high_mask = CHCR_TS_HIGH_MASK,
132 .ts_shift = ts_shift,
133 .ts_shift_num = ARRAY_SIZE(ts_shift),
134 .dmaor_init = DMAOR_INIT,
135};
136
137static struct resource sh7722_dmae_resources[] = {
138 [0] = {
139 /* Channel registers and DMAOR */
140 .start = 0xfe008020,
141 .end = 0xfe00808f,
142 .flags = IORESOURCE_MEM,
143 },
144 [1] = {
145 /* DMARSx */
146 .start = 0xfe009000,
147 .end = 0xfe00900b,
148 .flags = IORESOURCE_MEM,
149 },
150 {
151 .name = "error_irq",
152 .start = evt2irq(0xbc0),
153 .end = evt2irq(0xbc0),
154 .flags = IORESOURCE_IRQ,
155 },
156 {
157 /* IRQ for channels 0-3 */
158 .start = evt2irq(0x800),
159 .end = evt2irq(0x860),
160 .flags = IORESOURCE_IRQ,
161 },
162 {
163 /* IRQ for channels 4-5 */
164 .start = evt2irq(0xb80),
165 .end = evt2irq(0xba0),
166 .flags = IORESOURCE_IRQ,
167 },
168};
169
170struct platform_device dma_device = {
171 .name = "sh-dma-engine",
172 .id = -1,
173 .resource = sh7722_dmae_resources,
174 .num_resources = ARRAY_SIZE(sh7722_dmae_resources),
175 .dev = {
176 .platform_data = &dma_platform_data,
177 },
178};
179
180/* Serial */
181static struct plat_sci_port scif0_platform_data = {
182 .flags = UPF_BOOT_AUTOCONF,
183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
184 .type = PORT_SCIF,
185 .ops = &sh7722_sci_port_ops,
186 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
187};
188
189static struct resource scif0_resources[] = {
190 DEFINE_RES_MEM(0xffe00000, 0x100),
191 DEFINE_RES_IRQ(evt2irq(0xc00)),
192};
193
194static struct platform_device scif0_device = {
195 .name = "sh-sci",
196 .id = 0,
197 .resource = scif0_resources,
198 .num_resources = ARRAY_SIZE(scif0_resources),
199 .dev = {
200 .platform_data = &scif0_platform_data,
201 },
202};
203
204static struct plat_sci_port scif1_platform_data = {
205 .flags = UPF_BOOT_AUTOCONF,
206 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
207 .type = PORT_SCIF,
208 .ops = &sh7722_sci_port_ops,
209 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
210};
211
212static struct resource scif1_resources[] = {
213 DEFINE_RES_MEM(0xffe10000, 0x100),
214 DEFINE_RES_IRQ(evt2irq(0xc20)),
215};
216
217static struct platform_device scif1_device = {
218 .name = "sh-sci",
219 .id = 1,
220 .resource = scif1_resources,
221 .num_resources = ARRAY_SIZE(scif1_resources),
222 .dev = {
223 .platform_data = &scif1_platform_data,
224 },
225};
226
227static struct plat_sci_port scif2_platform_data = {
228 .flags = UPF_BOOT_AUTOCONF,
229 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
230 .type = PORT_SCIF,
231 .ops = &sh7722_sci_port_ops,
232 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
233};
234
235static struct resource scif2_resources[] = {
236 DEFINE_RES_MEM(0xffe20000, 0x100),
237 DEFINE_RES_IRQ(evt2irq(0xc40)),
238};
239
240static struct platform_device scif2_device = {
241 .name = "sh-sci",
242 .id = 2,
243 .resource = scif2_resources,
244 .num_resources = ARRAY_SIZE(scif2_resources),
245 .dev = {
246 .platform_data = &scif2_platform_data,
247 },
248};
249
250static struct resource rtc_resources[] = {
251 [0] = {
252 .start = 0xa465fec0,
253 .end = 0xa465fec0 + 0x58 - 1,
254 .flags = IORESOURCE_IO,
255 },
256 [1] = {
257 /* Period IRQ */
258 .start = evt2irq(0x7a0),
259 .flags = IORESOURCE_IRQ,
260 },
261 [2] = {
262 /* Carry IRQ */
263 .start = evt2irq(0x7c0),
264 .flags = IORESOURCE_IRQ,
265 },
266 [3] = {
267 /* Alarm IRQ */
268 .start = evt2irq(0x780),
269 .flags = IORESOURCE_IRQ,
270 },
271};
272
273static struct platform_device rtc_device = {
274 .name = "sh-rtc",
275 .id = -1,
276 .num_resources = ARRAY_SIZE(rtc_resources),
277 .resource = rtc_resources,
278};
279
280static struct m66592_platdata usbf_platdata = {
281 .on_chip = 1,
282};
283
284static struct resource usbf_resources[] = {
285 [0] = {
286 .name = "USBF",
287 .start = 0x04480000,
288 .end = 0x044800FF,
289 .flags = IORESOURCE_MEM,
290 },
291 [1] = {
292 .start = evt2irq(0xa20),
293 .end = evt2irq(0xa20),
294 .flags = IORESOURCE_IRQ,
295 },
296};
297
298static struct platform_device usbf_device = {
299 .name = "m66592_udc",
300 .id = 0, /* "usbf0" clock */
301 .dev = {
302 .dma_mask = NULL,
303 .coherent_dma_mask = 0xffffffff,
304 .platform_data = &usbf_platdata,
305 },
306 .num_resources = ARRAY_SIZE(usbf_resources),
307 .resource = usbf_resources,
308};
309
310static struct resource iic_resources[] = {
311 [0] = {
312 .name = "IIC",
313 .start = 0x04470000,
314 .end = 0x04470017,
315 .flags = IORESOURCE_MEM,
316 },
317 [1] = {
318 .start = evt2irq(0xe00),
319 .end = evt2irq(0xe60),
320 .flags = IORESOURCE_IRQ,
321 },
322};
323
324static struct platform_device iic_device = {
325 .name = "i2c-sh_mobile",
326 .id = 0, /* "i2c0" clock */
327 .num_resources = ARRAY_SIZE(iic_resources),
328 .resource = iic_resources,
329};
330
331static struct uio_info vpu_platform_data = {
332 .name = "VPU4",
333 .version = "0",
334 .irq = evt2irq(0x980),
335};
336
337static struct resource vpu_resources[] = {
338 [0] = {
339 .name = "VPU",
340 .start = 0xfe900000,
341 .end = 0xfe9022eb,
342 .flags = IORESOURCE_MEM,
343 },
344 [1] = {
345 /* place holder for contiguous memory */
346 },
347};
348
349static struct platform_device vpu_device = {
350 .name = "uio_pdrv_genirq",
351 .id = 0,
352 .dev = {
353 .platform_data = &vpu_platform_data,
354 },
355 .resource = vpu_resources,
356 .num_resources = ARRAY_SIZE(vpu_resources),
357};
358
359static struct uio_info veu_platform_data = {
360 .name = "VEU",
361 .version = "0",
362 .irq = evt2irq(0x8c0),
363};
364
365static struct resource veu_resources[] = {
366 [0] = {
367 .name = "VEU",
368 .start = 0xfe920000,
369 .end = 0xfe9200b7,
370 .flags = IORESOURCE_MEM,
371 },
372 [1] = {
373 /* place holder for contiguous memory */
374 },
375};
376
377static struct platform_device veu_device = {
378 .name = "uio_pdrv_genirq",
379 .id = 1,
380 .dev = {
381 .platform_data = &veu_platform_data,
382 },
383 .resource = veu_resources,
384 .num_resources = ARRAY_SIZE(veu_resources),
385};
386
387static struct uio_info jpu_platform_data = {
388 .name = "JPU",
389 .version = "0",
390 .irq = evt2irq(0x560),
391};
392
393static struct resource jpu_resources[] = {
394 [0] = {
395 .name = "JPU",
396 .start = 0xfea00000,
397 .end = 0xfea102d3,
398 .flags = IORESOURCE_MEM,
399 },
400 [1] = {
401 /* place holder for contiguous memory */
402 },
403};
404
405static struct platform_device jpu_device = {
406 .name = "uio_pdrv_genirq",
407 .id = 2,
408 .dev = {
409 .platform_data = &jpu_platform_data,
410 },
411 .resource = jpu_resources,
412 .num_resources = ARRAY_SIZE(jpu_resources),
413};
414
415static struct sh_timer_config cmt_platform_data = {
416 .channel_offset = 0x60,
417 .timer_bit = 5,
418 .clockevent_rating = 125,
419 .clocksource_rating = 125,
420};
421
422static struct resource cmt_resources[] = {
423 [0] = {
424 .start = 0x044a0060,
425 .end = 0x044a006b,
426 .flags = IORESOURCE_MEM,
427 },
428 [1] = {
429 .start = evt2irq(0xf00),
430 .flags = IORESOURCE_IRQ,
431 },
432};
433
434static struct platform_device cmt_device = {
435 .name = "sh_cmt",
436 .id = 0,
437 .dev = {
438 .platform_data = &cmt_platform_data,
439 },
440 .resource = cmt_resources,
441 .num_resources = ARRAY_SIZE(cmt_resources),
442};
443
444static struct sh_timer_config tmu0_platform_data = {
445 .channel_offset = 0x04,
446 .timer_bit = 0,
447 .clockevent_rating = 200,
448};
449
450static struct resource tmu0_resources[] = {
451 [0] = {
452 .start = 0xffd80008,
453 .end = 0xffd80013,
454 .flags = IORESOURCE_MEM,
455 },
456 [1] = {
457 .start = evt2irq(0x400),
458 .flags = IORESOURCE_IRQ,
459 },
460};
461
462static struct platform_device tmu0_device = {
463 .name = "sh_tmu",
464 .id = 0,
465 .dev = {
466 .platform_data = &tmu0_platform_data,
467 },
468 .resource = tmu0_resources,
469 .num_resources = ARRAY_SIZE(tmu0_resources),
470};
471
472static struct sh_timer_config tmu1_platform_data = {
473 .channel_offset = 0x10,
474 .timer_bit = 1,
475 .clocksource_rating = 200,
476};
477
478static struct resource tmu1_resources[] = {
479 [0] = {
480 .start = 0xffd80014,
481 .end = 0xffd8001f,
482 .flags = IORESOURCE_MEM,
483 },
484 [1] = {
485 .start = evt2irq(0x420),
486 .flags = IORESOURCE_IRQ,
487 },
488};
489
490static struct platform_device tmu1_device = {
491 .name = "sh_tmu",
492 .id = 1,
493 .dev = {
494 .platform_data = &tmu1_platform_data,
495 },
496 .resource = tmu1_resources,
497 .num_resources = ARRAY_SIZE(tmu1_resources),
498};
499
500static struct sh_timer_config tmu2_platform_data = {
501 .channel_offset = 0x1c,
502 .timer_bit = 2,
503};
504
505static struct resource tmu2_resources[] = {
506 [0] = {
507 .start = 0xffd80020,
508 .end = 0xffd8002b,
509 .flags = IORESOURCE_MEM,
510 },
511 [1] = {
512 .start = 18,
513 .flags = IORESOURCE_IRQ,
514 },
515};
516
517static struct platform_device tmu2_device = {
518 .name = "sh_tmu",
519 .id = 2,
520 .dev = {
521 .platform_data = &tmu2_platform_data,
522 },
523 .resource = tmu2_resources,
524 .num_resources = ARRAY_SIZE(tmu2_resources),
525};
526
527static struct siu_platform siu_platform_data = {
528 .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
529 .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
530 .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
531 .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
532};
533
534static struct resource siu_resources[] = {
535 [0] = {
536 .start = 0xa4540000,
537 .end = 0xa454c10f,
538 .flags = IORESOURCE_MEM,
539 },
540 [1] = {
541 .start = evt2irq(0xf80),
542 .flags = IORESOURCE_IRQ,
543 },
544};
545
546static struct platform_device siu_device = {
547 .name = "siu-pcm-audio",
548 .id = -1,
549 .dev = {
550 .platform_data = &siu_platform_data,
551 },
552 .resource = siu_resources,
553 .num_resources = ARRAY_SIZE(siu_resources),
554};
555
556static struct platform_device *sh7722_devices[] __initdata = {
557 &scif0_device,
558 &scif1_device,
559 &scif2_device,
560 &cmt_device,
561 &tmu0_device,
562 &tmu1_device,
563 &tmu2_device,
564 &rtc_device,
565 &usbf_device,
566 &iic_device,
567 &vpu_device,
568 &veu_device,
569 &jpu_device,
570 &siu_device,
571 &dma_device,
572};
573
574static int __init sh7722_devices_setup(void)
575{
576 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
577 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
578 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
579
580 return platform_add_devices(sh7722_devices,
581 ARRAY_SIZE(sh7722_devices));
582}
583arch_initcall(sh7722_devices_setup);
584
585static struct platform_device *sh7722_early_devices[] __initdata = {
586 &scif0_device,
587 &scif1_device,
588 &scif2_device,
589 &cmt_device,
590 &tmu0_device,
591 &tmu1_device,
592 &tmu2_device,
593};
594
595void __init plat_early_device_setup(void)
596{
597 early_platform_add_devices(sh7722_early_devices,
598 ARRAY_SIZE(sh7722_early_devices));
599}
600
601enum {
602 UNUSED=0,
603 ENABLED,
604 DISABLED,
605
606 /* interrupt sources */
607 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
608 HUDI,
609 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
610 RTC_ATI, RTC_PRI, RTC_CUI,
611 DMAC0, DMAC1, DMAC2, DMAC3,
612 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
613 VPU, TPU,
614 USB_USBI0, USB_USBI1,
615 DMAC4, DMAC5, DMAC_DADERR,
616 KEYSC,
617 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
618 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
619 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
620 CMT, TSIF, SIU, TWODG,
621 TMU0, TMU1, TMU2,
622 IRDA, JPU, LCDC,
623
624 /* interrupt groups */
625 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
626};
627
628static struct intc_vect vectors[] __initdata = {
629 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
630 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
631 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
632 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
633 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
634 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
635 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
636 INTC_VECT(RTC_CUI, 0x7c0),
637 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
638 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
639 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
640 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
641 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
642 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
643 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
644 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
645 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
646 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
647 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
648 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
649 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
650 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
651 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
652 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
653 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
654 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
655 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
656 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
657 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
658 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
659};
660
661static struct intc_group groups[] __initdata = {
662 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
663 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
664 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
665 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
666 INTC_GROUP(USB, USB_USBI0, USB_USBI1),
667 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
668 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
669 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
670 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
671};
672
673static struct intc_mask_reg mask_registers[] __initdata = {
674 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
675 { } },
676 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
677 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
678 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
679 { 0, 0, 0, VPU, } },
680 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
681 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
682 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
683 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
684 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
685 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
686 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
687 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
688 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
689 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
690 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
691 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
692 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
693 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
694 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
695 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
696 { } },
697 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
698 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
699 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
700 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
701};
702
703static struct intc_prio_reg prio_registers[] __initdata = {
704 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
705 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
706 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
707 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
708 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
709 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
710 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
711 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
712 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
713 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
714 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
715 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
716 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
717 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
718};
719
720static struct intc_sense_reg sense_registers[] __initdata = {
721 { 0xa414001c, 16, 2, /* ICR1 */
722 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
723};
724
725static struct intc_mask_reg ack_registers[] __initdata = {
726 { 0xa4140024, 0, 8, /* INTREQ00 */
727 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
728};
729
730static struct intc_desc intc_desc __initdata = {
731 .name = "sh7722",
732 .force_enable = ENABLED,
733 .force_disable = DISABLED,
734 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
735 prio_registers, sense_registers, ack_registers),
736};
737
738void __init plat_irq_setup(void)
739{
740 register_intc_controller(&intc_desc);
741}
742
743void __init plat_mem_setup(void)
744{
745 /* Register the URAM space as Node 1 */
746 setup_bootmem_node(1, 0x055f0000, 0x05610000);
747}
1/*
2 * SH7722 Setup
3 *
4 * Copyright (C) 2006 - 2008 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/mm.h>
12#include <linux/platform_device.h>
13#include <linux/serial.h>
14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/sh_intc.h>
17#include <linux/uio_driver.h>
18#include <linux/usb/m66592.h>
19
20#include <asm/clock.h>
21#include <asm/mmzone.h>
22#include <asm/siu.h>
23
24#include <cpu/dma-register.h>
25#include <cpu/sh7722.h>
26#include <cpu/serial.h>
27
28static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
29 {
30 .slave_id = SHDMA_SLAVE_SCIF0_TX,
31 .addr = 0xffe0000c,
32 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
33 .mid_rid = 0x21,
34 }, {
35 .slave_id = SHDMA_SLAVE_SCIF0_RX,
36 .addr = 0xffe00014,
37 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
38 .mid_rid = 0x22,
39 }, {
40 .slave_id = SHDMA_SLAVE_SCIF1_TX,
41 .addr = 0xffe1000c,
42 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
43 .mid_rid = 0x25,
44 }, {
45 .slave_id = SHDMA_SLAVE_SCIF1_RX,
46 .addr = 0xffe10014,
47 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
48 .mid_rid = 0x26,
49 }, {
50 .slave_id = SHDMA_SLAVE_SCIF2_TX,
51 .addr = 0xffe2000c,
52 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
53 .mid_rid = 0x29,
54 }, {
55 .slave_id = SHDMA_SLAVE_SCIF2_RX,
56 .addr = 0xffe20014,
57 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
58 .mid_rid = 0x2a,
59 }, {
60 .slave_id = SHDMA_SLAVE_SIUA_TX,
61 .addr = 0xa454c098,
62 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
63 .mid_rid = 0xb1,
64 }, {
65 .slave_id = SHDMA_SLAVE_SIUA_RX,
66 .addr = 0xa454c090,
67 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
68 .mid_rid = 0xb2,
69 }, {
70 .slave_id = SHDMA_SLAVE_SIUB_TX,
71 .addr = 0xa454c09c,
72 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
73 .mid_rid = 0xb5,
74 }, {
75 .slave_id = SHDMA_SLAVE_SIUB_RX,
76 .addr = 0xa454c094,
77 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
78 .mid_rid = 0xb6,
79 }, {
80 .slave_id = SHDMA_SLAVE_SDHI0_TX,
81 .addr = 0x04ce0030,
82 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
83 .mid_rid = 0xc1,
84 }, {
85 .slave_id = SHDMA_SLAVE_SDHI0_RX,
86 .addr = 0x04ce0030,
87 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
88 .mid_rid = 0xc2,
89 },
90};
91
92static const struct sh_dmae_channel sh7722_dmae_channels[] = {
93 {
94 .offset = 0,
95 .dmars = 0,
96 .dmars_bit = 0,
97 }, {
98 .offset = 0x10,
99 .dmars = 0,
100 .dmars_bit = 8,
101 }, {
102 .offset = 0x20,
103 .dmars = 4,
104 .dmars_bit = 0,
105 }, {
106 .offset = 0x30,
107 .dmars = 4,
108 .dmars_bit = 8,
109 }, {
110 .offset = 0x50,
111 .dmars = 8,
112 .dmars_bit = 0,
113 }, {
114 .offset = 0x60,
115 .dmars = 8,
116 .dmars_bit = 8,
117 }
118};
119
120static const unsigned int ts_shift[] = TS_SHIFT;
121
122static struct sh_dmae_pdata dma_platform_data = {
123 .slave = sh7722_dmae_slaves,
124 .slave_num = ARRAY_SIZE(sh7722_dmae_slaves),
125 .channel = sh7722_dmae_channels,
126 .channel_num = ARRAY_SIZE(sh7722_dmae_channels),
127 .ts_low_shift = CHCR_TS_LOW_SHIFT,
128 .ts_low_mask = CHCR_TS_LOW_MASK,
129 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
130 .ts_high_mask = CHCR_TS_HIGH_MASK,
131 .ts_shift = ts_shift,
132 .ts_shift_num = ARRAY_SIZE(ts_shift),
133 .dmaor_init = DMAOR_INIT,
134};
135
136static struct resource sh7722_dmae_resources[] = {
137 [0] = {
138 /* Channel registers and DMAOR */
139 .start = 0xfe008020,
140 .end = 0xfe00808f,
141 .flags = IORESOURCE_MEM,
142 },
143 [1] = {
144 /* DMARSx */
145 .start = 0xfe009000,
146 .end = 0xfe00900b,
147 .flags = IORESOURCE_MEM,
148 },
149 {
150 .name = "error_irq",
151 .start = evt2irq(0xbc0),
152 .end = evt2irq(0xbc0),
153 .flags = IORESOURCE_IRQ,
154 },
155 {
156 /* IRQ for channels 0-3 */
157 .start = evt2irq(0x800),
158 .end = evt2irq(0x860),
159 .flags = IORESOURCE_IRQ,
160 },
161 {
162 /* IRQ for channels 4-5 */
163 .start = evt2irq(0xb80),
164 .end = evt2irq(0xba0),
165 .flags = IORESOURCE_IRQ,
166 },
167};
168
169struct platform_device dma_device = {
170 .name = "sh-dma-engine",
171 .id = -1,
172 .resource = sh7722_dmae_resources,
173 .num_resources = ARRAY_SIZE(sh7722_dmae_resources),
174 .dev = {
175 .platform_data = &dma_platform_data,
176 },
177};
178
179/* Serial */
180static struct plat_sci_port scif0_platform_data = {
181 .mapbase = 0xffe00000,
182 .flags = UPF_BOOT_AUTOCONF,
183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
184 .scbrr_algo_id = SCBRR_ALGO_2,
185 .type = PORT_SCIF,
186 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
187 .ops = &sh7722_sci_port_ops,
188 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
189};
190
191static struct platform_device scif0_device = {
192 .name = "sh-sci",
193 .id = 0,
194 .dev = {
195 .platform_data = &scif0_platform_data,
196 },
197};
198
199static struct plat_sci_port scif1_platform_data = {
200 .mapbase = 0xffe10000,
201 .flags = UPF_BOOT_AUTOCONF,
202 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
203 .scbrr_algo_id = SCBRR_ALGO_2,
204 .type = PORT_SCIF,
205 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
206 .ops = &sh7722_sci_port_ops,
207 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
208};
209
210static struct platform_device scif1_device = {
211 .name = "sh-sci",
212 .id = 1,
213 .dev = {
214 .platform_data = &scif1_platform_data,
215 },
216};
217
218static struct plat_sci_port scif2_platform_data = {
219 .mapbase = 0xffe20000,
220 .flags = UPF_BOOT_AUTOCONF,
221 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
222 .scbrr_algo_id = SCBRR_ALGO_2,
223 .type = PORT_SCIF,
224 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
225 .ops = &sh7722_sci_port_ops,
226 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
227};
228
229static struct platform_device scif2_device = {
230 .name = "sh-sci",
231 .id = 2,
232 .dev = {
233 .platform_data = &scif2_platform_data,
234 },
235};
236
237static struct resource rtc_resources[] = {
238 [0] = {
239 .start = 0xa465fec0,
240 .end = 0xa465fec0 + 0x58 - 1,
241 .flags = IORESOURCE_IO,
242 },
243 [1] = {
244 /* Period IRQ */
245 .start = evt2irq(0x7a0),
246 .flags = IORESOURCE_IRQ,
247 },
248 [2] = {
249 /* Carry IRQ */
250 .start = evt2irq(0x7c0),
251 .flags = IORESOURCE_IRQ,
252 },
253 [3] = {
254 /* Alarm IRQ */
255 .start = evt2irq(0x780),
256 .flags = IORESOURCE_IRQ,
257 },
258};
259
260static struct platform_device rtc_device = {
261 .name = "sh-rtc",
262 .id = -1,
263 .num_resources = ARRAY_SIZE(rtc_resources),
264 .resource = rtc_resources,
265};
266
267static struct m66592_platdata usbf_platdata = {
268 .on_chip = 1,
269};
270
271static struct resource usbf_resources[] = {
272 [0] = {
273 .name = "USBF",
274 .start = 0x04480000,
275 .end = 0x044800FF,
276 .flags = IORESOURCE_MEM,
277 },
278 [1] = {
279 .start = evt2irq(0xa20),
280 .end = evt2irq(0xa20),
281 .flags = IORESOURCE_IRQ,
282 },
283};
284
285static struct platform_device usbf_device = {
286 .name = "m66592_udc",
287 .id = 0, /* "usbf0" clock */
288 .dev = {
289 .dma_mask = NULL,
290 .coherent_dma_mask = 0xffffffff,
291 .platform_data = &usbf_platdata,
292 },
293 .num_resources = ARRAY_SIZE(usbf_resources),
294 .resource = usbf_resources,
295};
296
297static struct resource iic_resources[] = {
298 [0] = {
299 .name = "IIC",
300 .start = 0x04470000,
301 .end = 0x04470017,
302 .flags = IORESOURCE_MEM,
303 },
304 [1] = {
305 .start = evt2irq(0xe00),
306 .end = evt2irq(0xe60),
307 .flags = IORESOURCE_IRQ,
308 },
309};
310
311static struct platform_device iic_device = {
312 .name = "i2c-sh_mobile",
313 .id = 0, /* "i2c0" clock */
314 .num_resources = ARRAY_SIZE(iic_resources),
315 .resource = iic_resources,
316};
317
318static struct uio_info vpu_platform_data = {
319 .name = "VPU4",
320 .version = "0",
321 .irq = evt2irq(0x980),
322};
323
324static struct resource vpu_resources[] = {
325 [0] = {
326 .name = "VPU",
327 .start = 0xfe900000,
328 .end = 0xfe9022eb,
329 .flags = IORESOURCE_MEM,
330 },
331 [1] = {
332 /* place holder for contiguous memory */
333 },
334};
335
336static struct platform_device vpu_device = {
337 .name = "uio_pdrv_genirq",
338 .id = 0,
339 .dev = {
340 .platform_data = &vpu_platform_data,
341 },
342 .resource = vpu_resources,
343 .num_resources = ARRAY_SIZE(vpu_resources),
344};
345
346static struct uio_info veu_platform_data = {
347 .name = "VEU",
348 .version = "0",
349 .irq = evt2irq(0x8c0),
350};
351
352static struct resource veu_resources[] = {
353 [0] = {
354 .name = "VEU",
355 .start = 0xfe920000,
356 .end = 0xfe9200b7,
357 .flags = IORESOURCE_MEM,
358 },
359 [1] = {
360 /* place holder for contiguous memory */
361 },
362};
363
364static struct platform_device veu_device = {
365 .name = "uio_pdrv_genirq",
366 .id = 1,
367 .dev = {
368 .platform_data = &veu_platform_data,
369 },
370 .resource = veu_resources,
371 .num_resources = ARRAY_SIZE(veu_resources),
372};
373
374static struct uio_info jpu_platform_data = {
375 .name = "JPU",
376 .version = "0",
377 .irq = evt2irq(0x560),
378};
379
380static struct resource jpu_resources[] = {
381 [0] = {
382 .name = "JPU",
383 .start = 0xfea00000,
384 .end = 0xfea102d3,
385 .flags = IORESOURCE_MEM,
386 },
387 [1] = {
388 /* place holder for contiguous memory */
389 },
390};
391
392static struct platform_device jpu_device = {
393 .name = "uio_pdrv_genirq",
394 .id = 2,
395 .dev = {
396 .platform_data = &jpu_platform_data,
397 },
398 .resource = jpu_resources,
399 .num_resources = ARRAY_SIZE(jpu_resources),
400};
401
402static struct sh_timer_config cmt_platform_data = {
403 .channel_offset = 0x60,
404 .timer_bit = 5,
405 .clockevent_rating = 125,
406 .clocksource_rating = 125,
407};
408
409static struct resource cmt_resources[] = {
410 [0] = {
411 .start = 0x044a0060,
412 .end = 0x044a006b,
413 .flags = IORESOURCE_MEM,
414 },
415 [1] = {
416 .start = evt2irq(0xf00),
417 .flags = IORESOURCE_IRQ,
418 },
419};
420
421static struct platform_device cmt_device = {
422 .name = "sh_cmt",
423 .id = 0,
424 .dev = {
425 .platform_data = &cmt_platform_data,
426 },
427 .resource = cmt_resources,
428 .num_resources = ARRAY_SIZE(cmt_resources),
429};
430
431static struct sh_timer_config tmu0_platform_data = {
432 .channel_offset = 0x04,
433 .timer_bit = 0,
434 .clockevent_rating = 200,
435};
436
437static struct resource tmu0_resources[] = {
438 [0] = {
439 .start = 0xffd80008,
440 .end = 0xffd80013,
441 .flags = IORESOURCE_MEM,
442 },
443 [1] = {
444 .start = evt2irq(0x400),
445 .flags = IORESOURCE_IRQ,
446 },
447};
448
449static struct platform_device tmu0_device = {
450 .name = "sh_tmu",
451 .id = 0,
452 .dev = {
453 .platform_data = &tmu0_platform_data,
454 },
455 .resource = tmu0_resources,
456 .num_resources = ARRAY_SIZE(tmu0_resources),
457};
458
459static struct sh_timer_config tmu1_platform_data = {
460 .channel_offset = 0x10,
461 .timer_bit = 1,
462 .clocksource_rating = 200,
463};
464
465static struct resource tmu1_resources[] = {
466 [0] = {
467 .start = 0xffd80014,
468 .end = 0xffd8001f,
469 .flags = IORESOURCE_MEM,
470 },
471 [1] = {
472 .start = evt2irq(0x420),
473 .flags = IORESOURCE_IRQ,
474 },
475};
476
477static struct platform_device tmu1_device = {
478 .name = "sh_tmu",
479 .id = 1,
480 .dev = {
481 .platform_data = &tmu1_platform_data,
482 },
483 .resource = tmu1_resources,
484 .num_resources = ARRAY_SIZE(tmu1_resources),
485};
486
487static struct sh_timer_config tmu2_platform_data = {
488 .channel_offset = 0x1c,
489 .timer_bit = 2,
490};
491
492static struct resource tmu2_resources[] = {
493 [0] = {
494 .start = 0xffd80020,
495 .end = 0xffd8002b,
496 .flags = IORESOURCE_MEM,
497 },
498 [1] = {
499 .start = 18,
500 .flags = IORESOURCE_IRQ,
501 },
502};
503
504static struct platform_device tmu2_device = {
505 .name = "sh_tmu",
506 .id = 2,
507 .dev = {
508 .platform_data = &tmu2_platform_data,
509 },
510 .resource = tmu2_resources,
511 .num_resources = ARRAY_SIZE(tmu2_resources),
512};
513
514static struct siu_platform siu_platform_data = {
515 .dma_dev = &dma_device.dev,
516 .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
517 .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
518 .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
519 .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
520};
521
522static struct resource siu_resources[] = {
523 [0] = {
524 .start = 0xa4540000,
525 .end = 0xa454c10f,
526 .flags = IORESOURCE_MEM,
527 },
528 [1] = {
529 .start = evt2irq(0xf80),
530 .flags = IORESOURCE_IRQ,
531 },
532};
533
534static struct platform_device siu_device = {
535 .name = "siu-pcm-audio",
536 .id = -1,
537 .dev = {
538 .platform_data = &siu_platform_data,
539 },
540 .resource = siu_resources,
541 .num_resources = ARRAY_SIZE(siu_resources),
542};
543
544static struct platform_device *sh7722_devices[] __initdata = {
545 &scif0_device,
546 &scif1_device,
547 &scif2_device,
548 &cmt_device,
549 &tmu0_device,
550 &tmu1_device,
551 &tmu2_device,
552 &rtc_device,
553 &usbf_device,
554 &iic_device,
555 &vpu_device,
556 &veu_device,
557 &jpu_device,
558 &siu_device,
559 &dma_device,
560};
561
562static int __init sh7722_devices_setup(void)
563{
564 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
565 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
566 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
567
568 return platform_add_devices(sh7722_devices,
569 ARRAY_SIZE(sh7722_devices));
570}
571arch_initcall(sh7722_devices_setup);
572
573static struct platform_device *sh7722_early_devices[] __initdata = {
574 &scif0_device,
575 &scif1_device,
576 &scif2_device,
577 &cmt_device,
578 &tmu0_device,
579 &tmu1_device,
580 &tmu2_device,
581};
582
583void __init plat_early_device_setup(void)
584{
585 early_platform_add_devices(sh7722_early_devices,
586 ARRAY_SIZE(sh7722_early_devices));
587}
588
589enum {
590 UNUSED=0,
591 ENABLED,
592 DISABLED,
593
594 /* interrupt sources */
595 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
596 HUDI,
597 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
598 RTC_ATI, RTC_PRI, RTC_CUI,
599 DMAC0, DMAC1, DMAC2, DMAC3,
600 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
601 VPU, TPU,
602 USB_USBI0, USB_USBI1,
603 DMAC4, DMAC5, DMAC_DADERR,
604 KEYSC,
605 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
606 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
607 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
608 CMT, TSIF, SIU, TWODG,
609 TMU0, TMU1, TMU2,
610 IRDA, JPU, LCDC,
611
612 /* interrupt groups */
613 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
614};
615
616static struct intc_vect vectors[] __initdata = {
617 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
618 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
619 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
620 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
621 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
622 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
623 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
624 INTC_VECT(RTC_CUI, 0x7c0),
625 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
626 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
627 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
628 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
629 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
630 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
631 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
632 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
633 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
634 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
635 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
636 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
637 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
638 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
639 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
640 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
641 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
642 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
643 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
644 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
645 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
646 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
647};
648
649static struct intc_group groups[] __initdata = {
650 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
651 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
652 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
653 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
654 INTC_GROUP(USB, USB_USBI0, USB_USBI1),
655 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
656 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
657 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
658 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
659};
660
661static struct intc_mask_reg mask_registers[] __initdata = {
662 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
663 { } },
664 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
665 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
666 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
667 { 0, 0, 0, VPU, } },
668 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
669 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
670 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
671 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
672 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
673 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
674 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
675 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
676 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
677 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
678 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
679 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
680 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
681 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
682 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
683 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
684 { } },
685 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
686 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
687 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
688 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
689};
690
691static struct intc_prio_reg prio_registers[] __initdata = {
692 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
693 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
694 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
695 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
696 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
697 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
698 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
699 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
700 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
701 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
702 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
703 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
704 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
705 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
706};
707
708static struct intc_sense_reg sense_registers[] __initdata = {
709 { 0xa414001c, 16, 2, /* ICR1 */
710 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
711};
712
713static struct intc_mask_reg ack_registers[] __initdata = {
714 { 0xa4140024, 0, 8, /* INTREQ00 */
715 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
716};
717
718static struct intc_desc intc_desc __initdata = {
719 .name = "sh7722",
720 .force_enable = ENABLED,
721 .force_disable = DISABLED,
722 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
723 prio_registers, sense_registers, ack_registers),
724};
725
726void __init plat_irq_setup(void)
727{
728 register_intc_controller(&intc_desc);
729}
730
731void __init plat_mem_setup(void)
732{
733 /* Register the URAM space as Node 1 */
734 setup_bootmem_node(1, 0x055f0000, 0x05610000);
735}