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1/*
2 * SH7206 Setup
3 *
4 * Copyright (C) 2006 Yoshinori Sato
5 * Copyright (C) 2009 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/serial.h>
14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
17
18enum {
19 UNUSED = 0,
20
21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
24 ADC_ADI0, ADC_ADI1,
25
26 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
27
28 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
29 MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
30 IIC3,
31
32 CMT0, CMT1, BSC, WDT,
33
34 MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V,
35
36 POE2_OEI3,
37
38 SCIF0, SCIF1, SCIF2, SCIF3,
39
40 /* interrupt groups */
41 PINT,
42};
43
44static struct intc_vect vectors[] __initdata = {
45 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
46 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
47 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
48 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
49 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
50 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
51 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
52 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
53 INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
54 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
55 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
56 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
57 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
58 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
59 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
60 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
61 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
62 INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
63 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
64 INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157),
65 INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159),
66 INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161),
67 INTC_IRQ(MTU0_VEF, 162),
68 INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165),
69 INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169),
70 INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173),
71 INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177),
72 INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181),
73 INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183),
74 INTC_IRQ(MTU2_TCI3V, 184),
75 INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189),
76 INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191),
77 INTC_IRQ(MTU2_TCI4V, 192),
78 INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197),
79 INTC_IRQ(MTU5, 198),
80 INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201),
81 INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205),
82 INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207),
83 INTC_IRQ(MTU2S_TCI3V, 208),
84 INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213),
85 INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215),
86 INTC_IRQ(MTU2S_TCI4V, 216),
87 INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221),
88 INTC_IRQ(MTU5S, 222),
89 INTC_IRQ(POE2_OEI3, 224),
90 INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229),
91 INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231),
92 INTC_IRQ(IIC3, 232),
93 INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241),
94 INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243),
95 INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245),
96 INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247),
97 INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249),
98 INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251),
99 INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253),
100 INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255),
101};
102
103static struct intc_group groups[] __initdata = {
104 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
105 PINT4, PINT5, PINT6, PINT7),
106};
107
108static struct intc_prio_reg prio_registers[] __initdata = {
109 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
110 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
111 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } },
112 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
113 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
114 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
115 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF,
116 MTU1_AB, MTU1_VU } },
117 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU,
118 MTU3_ABCD, MTU2_TCI3V } },
119 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V,
120 MTU5, POE2_12 } },
121 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V,
122 MTU4S_ABCD, MTU2S_TCI4V } },
123 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } },
124 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
125};
126
127static struct intc_mask_reg mask_registers[] __initdata = {
128 { 0xfffe0808, 0, 16, /* PINTER */
129 { 0, 0, 0, 0, 0, 0, 0, 0,
130 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
131};
132
133static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
134 mask_registers, prio_registers, NULL);
135
136static struct plat_sci_port scif0_platform_data = {
137 .flags = UPF_BOOT_AUTOCONF,
138 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
139 .type = PORT_SCIF,
140};
141
142static struct resource scif0_resources[] = {
143 DEFINE_RES_MEM(0xfffe8000, 0x100),
144 DEFINE_RES_IRQ(240),
145};
146
147static struct platform_device scif0_device = {
148 .name = "sh-sci",
149 .id = 0,
150 .resource = scif0_resources,
151 .num_resources = ARRAY_SIZE(scif0_resources),
152 .dev = {
153 .platform_data = &scif0_platform_data,
154 },
155};
156
157static struct plat_sci_port scif1_platform_data = {
158 .flags = UPF_BOOT_AUTOCONF,
159 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
160 .type = PORT_SCIF,
161};
162
163static struct resource scif1_resources[] = {
164 DEFINE_RES_MEM(0xfffe8800, 0x100),
165 DEFINE_RES_IRQ(244),
166};
167
168static struct platform_device scif1_device = {
169 .name = "sh-sci",
170 .id = 1,
171 .resource = scif1_resources,
172 .num_resources = ARRAY_SIZE(scif1_resources),
173 .dev = {
174 .platform_data = &scif1_platform_data,
175 },
176};
177
178static struct plat_sci_port scif2_platform_data = {
179 .flags = UPF_BOOT_AUTOCONF,
180 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
181 .type = PORT_SCIF,
182};
183
184static struct resource scif2_resources[] = {
185 DEFINE_RES_MEM(0xfffe9000, 0x100),
186 DEFINE_RES_IRQ(248),
187};
188
189static struct platform_device scif2_device = {
190 .name = "sh-sci",
191 .id = 2,
192 .resource = scif2_resources,
193 .num_resources = ARRAY_SIZE(scif2_resources),
194 .dev = {
195 .platform_data = &scif2_platform_data,
196 },
197};
198
199static struct plat_sci_port scif3_platform_data = {
200 .flags = UPF_BOOT_AUTOCONF,
201 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
202 .type = PORT_SCIF,
203};
204
205static struct resource scif3_resources[] = {
206 DEFINE_RES_MEM(0xfffe9800, 0x100),
207 DEFINE_RES_IRQ(252),
208};
209
210static struct platform_device scif3_device = {
211 .name = "sh-sci",
212 .id = 3,
213 .resource = scif3_resources,
214 .num_resources = ARRAY_SIZE(scif3_resources),
215 .dev = {
216 .platform_data = &scif3_platform_data,
217 },
218};
219
220static struct sh_timer_config cmt0_platform_data = {
221 .channel_offset = 0x02,
222 .timer_bit = 0,
223 .clockevent_rating = 125,
224 .clocksource_rating = 0, /* disabled due to code generation issues */
225};
226
227static struct resource cmt0_resources[] = {
228 [0] = {
229 .start = 0xfffec002,
230 .end = 0xfffec007,
231 .flags = IORESOURCE_MEM,
232 },
233 [1] = {
234 .start = 140,
235 .flags = IORESOURCE_IRQ,
236 },
237};
238
239static struct platform_device cmt0_device = {
240 .name = "sh_cmt",
241 .id = 0,
242 .dev = {
243 .platform_data = &cmt0_platform_data,
244 },
245 .resource = cmt0_resources,
246 .num_resources = ARRAY_SIZE(cmt0_resources),
247};
248
249static struct sh_timer_config cmt1_platform_data = {
250 .channel_offset = 0x08,
251 .timer_bit = 1,
252 .clockevent_rating = 125,
253 .clocksource_rating = 0, /* disabled due to code generation issues */
254};
255
256static struct resource cmt1_resources[] = {
257 [0] = {
258 .start = 0xfffec008,
259 .end = 0xfffec00d,
260 .flags = IORESOURCE_MEM,
261 },
262 [1] = {
263 .start = 144,
264 .flags = IORESOURCE_IRQ,
265 },
266};
267
268static struct platform_device cmt1_device = {
269 .name = "sh_cmt",
270 .id = 1,
271 .dev = {
272 .platform_data = &cmt1_platform_data,
273 },
274 .resource = cmt1_resources,
275 .num_resources = ARRAY_SIZE(cmt1_resources),
276};
277
278static struct sh_timer_config mtu2_0_platform_data = {
279 .channel_offset = -0x80,
280 .timer_bit = 0,
281 .clockevent_rating = 200,
282};
283
284static struct resource mtu2_0_resources[] = {
285 [0] = {
286 .start = 0xfffe4300,
287 .end = 0xfffe4326,
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
291 .start = 156,
292 .flags = IORESOURCE_IRQ,
293 },
294};
295
296static struct platform_device mtu2_0_device = {
297 .name = "sh_mtu2",
298 .id = 0,
299 .dev = {
300 .platform_data = &mtu2_0_platform_data,
301 },
302 .resource = mtu2_0_resources,
303 .num_resources = ARRAY_SIZE(mtu2_0_resources),
304};
305
306static struct sh_timer_config mtu2_1_platform_data = {
307 .channel_offset = -0x100,
308 .timer_bit = 1,
309 .clockevent_rating = 200,
310};
311
312static struct resource mtu2_1_resources[] = {
313 [0] = {
314 .start = 0xfffe4380,
315 .end = 0xfffe4390,
316 .flags = IORESOURCE_MEM,
317 },
318 [1] = {
319 .start = 164,
320 .flags = IORESOURCE_IRQ,
321 },
322};
323
324static struct platform_device mtu2_1_device = {
325 .name = "sh_mtu2",
326 .id = 1,
327 .dev = {
328 .platform_data = &mtu2_1_platform_data,
329 },
330 .resource = mtu2_1_resources,
331 .num_resources = ARRAY_SIZE(mtu2_1_resources),
332};
333
334static struct sh_timer_config mtu2_2_platform_data = {
335 .channel_offset = 0x80,
336 .timer_bit = 2,
337 .clockevent_rating = 200,
338};
339
340static struct resource mtu2_2_resources[] = {
341 [0] = {
342 .start = 0xfffe4000,
343 .end = 0xfffe400a,
344 .flags = IORESOURCE_MEM,
345 },
346 [1] = {
347 .start = 180,
348 .flags = IORESOURCE_IRQ,
349 },
350};
351
352static struct platform_device mtu2_2_device = {
353 .name = "sh_mtu2",
354 .id = 2,
355 .dev = {
356 .platform_data = &mtu2_2_platform_data,
357 },
358 .resource = mtu2_2_resources,
359 .num_resources = ARRAY_SIZE(mtu2_2_resources),
360};
361
362static struct platform_device *sh7206_devices[] __initdata = {
363 &scif0_device,
364 &scif1_device,
365 &scif2_device,
366 &scif3_device,
367 &cmt0_device,
368 &cmt1_device,
369 &mtu2_0_device,
370 &mtu2_1_device,
371 &mtu2_2_device,
372};
373
374static int __init sh7206_devices_setup(void)
375{
376 return platform_add_devices(sh7206_devices,
377 ARRAY_SIZE(sh7206_devices));
378}
379arch_initcall(sh7206_devices_setup);
380
381void __init plat_irq_setup(void)
382{
383 register_intc_controller(&intc_desc);
384}
385
386static struct platform_device *sh7206_early_devices[] __initdata = {
387 &scif0_device,
388 &scif1_device,
389 &scif2_device,
390 &scif3_device,
391 &cmt0_device,
392 &cmt1_device,
393 &mtu2_0_device,
394 &mtu2_1_device,
395 &mtu2_2_device,
396};
397
398#define STBCR3 0xfffe0408
399#define STBCR4 0xfffe040c
400
401void __init plat_early_device_setup(void)
402{
403 /* enable CMT clock */
404 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
405
406 /* enable MTU2 clock */
407 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
408
409 early_platform_add_devices(sh7206_early_devices,
410 ARRAY_SIZE(sh7206_early_devices));
411}
1/*
2 * SH7206 Setup
3 *
4 * Copyright (C) 2006 Yoshinori Sato
5 * Copyright (C) 2009 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/serial.h>
14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
17
18enum {
19 UNUSED = 0,
20
21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
24 ADC_ADI0, ADC_ADI1,
25
26 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
27
28 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
29 MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
30 IIC3,
31
32 CMT0, CMT1, BSC, WDT,
33
34 MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V,
35
36 POE2_OEI3,
37
38 SCIF0, SCIF1, SCIF2, SCIF3,
39
40 /* interrupt groups */
41 PINT,
42};
43
44static struct intc_vect vectors[] __initdata = {
45 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
46 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
47 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
48 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
49 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
50 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
51 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
52 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
53 INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
54 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
55 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
56 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
57 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
58 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
59 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
60 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
61 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
62 INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
63 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
64 INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157),
65 INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159),
66 INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161),
67 INTC_IRQ(MTU0_VEF, 162),
68 INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165),
69 INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169),
70 INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173),
71 INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177),
72 INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181),
73 INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183),
74 INTC_IRQ(MTU2_TCI3V, 184),
75 INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189),
76 INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191),
77 INTC_IRQ(MTU2_TCI4V, 192),
78 INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197),
79 INTC_IRQ(MTU5, 198),
80 INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201),
81 INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205),
82 INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207),
83 INTC_IRQ(MTU2S_TCI3V, 208),
84 INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213),
85 INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215),
86 INTC_IRQ(MTU2S_TCI4V, 216),
87 INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221),
88 INTC_IRQ(MTU5S, 222),
89 INTC_IRQ(POE2_OEI3, 224),
90 INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229),
91 INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231),
92 INTC_IRQ(IIC3, 232),
93 INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241),
94 INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243),
95 INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245),
96 INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247),
97 INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249),
98 INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251),
99 INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253),
100 INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255),
101};
102
103static struct intc_group groups[] __initdata = {
104 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
105 PINT4, PINT5, PINT6, PINT7),
106};
107
108static struct intc_prio_reg prio_registers[] __initdata = {
109 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
110 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
111 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } },
112 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
113 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
114 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
115 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF,
116 MTU1_AB, MTU1_VU } },
117 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU,
118 MTU3_ABCD, MTU2_TCI3V } },
119 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V,
120 MTU5, POE2_12 } },
121 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V,
122 MTU4S_ABCD, MTU2S_TCI4V } },
123 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } },
124 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
125};
126
127static struct intc_mask_reg mask_registers[] __initdata = {
128 { 0xfffe0808, 0, 16, /* PINTER */
129 { 0, 0, 0, 0, 0, 0, 0, 0,
130 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
131};
132
133static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
134 mask_registers, prio_registers, NULL);
135
136static struct plat_sci_port scif0_platform_data = {
137 .mapbase = 0xfffe8000,
138 .flags = UPF_BOOT_AUTOCONF,
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
140 .scbrr_algo_id = SCBRR_ALGO_2,
141 .type = PORT_SCIF,
142 .irqs = SCIx_IRQ_MUXED(240),
143};
144
145static struct platform_device scif0_device = {
146 .name = "sh-sci",
147 .id = 0,
148 .dev = {
149 .platform_data = &scif0_platform_data,
150 },
151};
152
153static struct plat_sci_port scif1_platform_data = {
154 .mapbase = 0xfffe8800,
155 .flags = UPF_BOOT_AUTOCONF,
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
157 .scbrr_algo_id = SCBRR_ALGO_2,
158 .type = PORT_SCIF,
159 .irqs = SCIx_IRQ_MUXED(244),
160};
161
162static struct platform_device scif1_device = {
163 .name = "sh-sci",
164 .id = 1,
165 .dev = {
166 .platform_data = &scif1_platform_data,
167 },
168};
169
170static struct plat_sci_port scif2_platform_data = {
171 .mapbase = 0xfffe9000,
172 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
174 .scbrr_algo_id = SCBRR_ALGO_2,
175 .type = PORT_SCIF,
176 .irqs = SCIx_IRQ_MUXED(248),
177};
178
179static struct platform_device scif2_device = {
180 .name = "sh-sci",
181 .id = 2,
182 .dev = {
183 .platform_data = &scif2_platform_data,
184 },
185};
186
187static struct plat_sci_port scif3_platform_data = {
188 .mapbase = 0xfffe9800,
189 .flags = UPF_BOOT_AUTOCONF,
190 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
191 .scbrr_algo_id = SCBRR_ALGO_2,
192 .type = PORT_SCIF,
193 .irqs = SCIx_IRQ_MUXED(252),
194};
195
196static struct platform_device scif3_device = {
197 .name = "sh-sci",
198 .id = 3,
199 .dev = {
200 .platform_data = &scif3_platform_data,
201 },
202};
203
204static struct sh_timer_config cmt0_platform_data = {
205 .channel_offset = 0x02,
206 .timer_bit = 0,
207 .clockevent_rating = 125,
208 .clocksource_rating = 0, /* disabled due to code generation issues */
209};
210
211static struct resource cmt0_resources[] = {
212 [0] = {
213 .start = 0xfffec002,
214 .end = 0xfffec007,
215 .flags = IORESOURCE_MEM,
216 },
217 [1] = {
218 .start = 140,
219 .flags = IORESOURCE_IRQ,
220 },
221};
222
223static struct platform_device cmt0_device = {
224 .name = "sh_cmt",
225 .id = 0,
226 .dev = {
227 .platform_data = &cmt0_platform_data,
228 },
229 .resource = cmt0_resources,
230 .num_resources = ARRAY_SIZE(cmt0_resources),
231};
232
233static struct sh_timer_config cmt1_platform_data = {
234 .channel_offset = 0x08,
235 .timer_bit = 1,
236 .clockevent_rating = 125,
237 .clocksource_rating = 0, /* disabled due to code generation issues */
238};
239
240static struct resource cmt1_resources[] = {
241 [0] = {
242 .start = 0xfffec008,
243 .end = 0xfffec00d,
244 .flags = IORESOURCE_MEM,
245 },
246 [1] = {
247 .start = 144,
248 .flags = IORESOURCE_IRQ,
249 },
250};
251
252static struct platform_device cmt1_device = {
253 .name = "sh_cmt",
254 .id = 1,
255 .dev = {
256 .platform_data = &cmt1_platform_data,
257 },
258 .resource = cmt1_resources,
259 .num_resources = ARRAY_SIZE(cmt1_resources),
260};
261
262static struct sh_timer_config mtu2_0_platform_data = {
263 .channel_offset = -0x80,
264 .timer_bit = 0,
265 .clockevent_rating = 200,
266};
267
268static struct resource mtu2_0_resources[] = {
269 [0] = {
270 .start = 0xfffe4300,
271 .end = 0xfffe4326,
272 .flags = IORESOURCE_MEM,
273 },
274 [1] = {
275 .start = 156,
276 .flags = IORESOURCE_IRQ,
277 },
278};
279
280static struct platform_device mtu2_0_device = {
281 .name = "sh_mtu2",
282 .id = 0,
283 .dev = {
284 .platform_data = &mtu2_0_platform_data,
285 },
286 .resource = mtu2_0_resources,
287 .num_resources = ARRAY_SIZE(mtu2_0_resources),
288};
289
290static struct sh_timer_config mtu2_1_platform_data = {
291 .channel_offset = -0x100,
292 .timer_bit = 1,
293 .clockevent_rating = 200,
294};
295
296static struct resource mtu2_1_resources[] = {
297 [0] = {
298 .start = 0xfffe4380,
299 .end = 0xfffe4390,
300 .flags = IORESOURCE_MEM,
301 },
302 [1] = {
303 .start = 164,
304 .flags = IORESOURCE_IRQ,
305 },
306};
307
308static struct platform_device mtu2_1_device = {
309 .name = "sh_mtu2",
310 .id = 1,
311 .dev = {
312 .platform_data = &mtu2_1_platform_data,
313 },
314 .resource = mtu2_1_resources,
315 .num_resources = ARRAY_SIZE(mtu2_1_resources),
316};
317
318static struct sh_timer_config mtu2_2_platform_data = {
319 .channel_offset = 0x80,
320 .timer_bit = 2,
321 .clockevent_rating = 200,
322};
323
324static struct resource mtu2_2_resources[] = {
325 [0] = {
326 .start = 0xfffe4000,
327 .end = 0xfffe400a,
328 .flags = IORESOURCE_MEM,
329 },
330 [1] = {
331 .start = 180,
332 .flags = IORESOURCE_IRQ,
333 },
334};
335
336static struct platform_device mtu2_2_device = {
337 .name = "sh_mtu2",
338 .id = 2,
339 .dev = {
340 .platform_data = &mtu2_2_platform_data,
341 },
342 .resource = mtu2_2_resources,
343 .num_resources = ARRAY_SIZE(mtu2_2_resources),
344};
345
346static struct platform_device *sh7206_devices[] __initdata = {
347 &scif0_device,
348 &scif1_device,
349 &scif2_device,
350 &scif3_device,
351 &cmt0_device,
352 &cmt1_device,
353 &mtu2_0_device,
354 &mtu2_1_device,
355 &mtu2_2_device,
356};
357
358static int __init sh7206_devices_setup(void)
359{
360 return platform_add_devices(sh7206_devices,
361 ARRAY_SIZE(sh7206_devices));
362}
363arch_initcall(sh7206_devices_setup);
364
365void __init plat_irq_setup(void)
366{
367 register_intc_controller(&intc_desc);
368}
369
370static struct platform_device *sh7206_early_devices[] __initdata = {
371 &scif0_device,
372 &scif1_device,
373 &scif2_device,
374 &scif3_device,
375 &cmt0_device,
376 &cmt1_device,
377 &mtu2_0_device,
378 &mtu2_1_device,
379 &mtu2_2_device,
380};
381
382#define STBCR3 0xfffe0408
383#define STBCR4 0xfffe040c
384
385void __init plat_early_device_setup(void)
386{
387 /* enable CMT clock */
388 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
389
390 /* enable MTU2 clock */
391 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
392
393 early_platform_add_devices(sh7206_early_devices,
394 ARRAY_SIZE(sh7206_early_devices));
395}