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1/*
2 * Copyright 2002 Integrated Device Technology, Inc.
3 * All rights reserved.
4 *
5 * DMA register definition.
6 *
7 * Author : ryan.holmQVist@idt.com
8 * Date : 20011005
9 */
10
11#ifndef __ASM_RC32434_DMA_H
12#define __ASM_RC32434_DMA_H
13
14#include <asm/mach-rc32434/rb.h>
15
16#define DMA0_BASE_ADDR 0x18040000
17
18/*
19 * DMA descriptor (in physical memory).
20 */
21
22struct dma_desc {
23 u32 control; /* Control. use DMAD_* */
24 u32 ca; /* Current Address. */
25 u32 devcs; /* Device control and status. */
26 u32 link; /* Next descriptor in chain. */
27};
28
29#define DMA_DESC_SIZ sizeof(struct dma_desc)
30#define DMA_DESC_COUNT_BIT 0
31#define DMA_DESC_COUNT_MSK 0x0003ffff
32#define DMA_DESC_DS_BIT 20
33#define DMA_DESC_DS_MSK 0x00300000
34
35#define DMA_DESC_DEV_CMD_BIT 22
36#define DMA_DESC_DEV_CMD_MSK 0x01c00000
37
38/* DMA command sizes */
39#define DMA_DESC_DEV_CMD_BYTE 0
40#define DMA_DESC_DEV_CMD_HLF_WD 1
41#define DMA_DESC_DEV_CMD_WORD 2
42#define DMA_DESC_DEV_CMD_2WORDS 3
43#define DMA_DESC_DEV_CMD_4WORDS 4
44#define DMA_DESC_DEV_CMD_6WORDS 5
45#define DMA_DESC_DEV_CMD_8WORDS 6
46#define DMA_DESC_DEV_CMD_16WORDS 7
47
48/* DMA descriptors interrupts */
49#define DMA_DESC_COF (1 << 25) /* Chain on finished */
50#define DMA_DESC_COD (1 << 26) /* Chain on done */
51#define DMA_DESC_IOF (1 << 27) /* Interrupt on finished */
52#define DMA_DESC_IOD (1 << 28) /* Interrupt on done */
53#define DMA_DESC_TERM (1 << 29) /* Terminated */
54#define DMA_DESC_DONE (1 << 30) /* Done */
55#define DMA_DESC_FINI (1 << 31) /* Finished */
56
57/*
58 * DMA register (within Internal Register Map).
59 */
60
61struct dma_reg {
62 u32 dmac; /* Control. */
63 u32 dmas; /* Status. */
64 u32 dmasm; /* Mask. */
65 u32 dmadptr; /* Descriptor pointer. */
66 u32 dmandptr; /* Next descriptor pointer. */
67};
68
69/* DMA channels specific registers */
70#define DMA_CHAN_RUN_BIT (1 << 0)
71#define DMA_CHAN_DONE_BIT (1 << 1)
72#define DMA_CHAN_MODE_BIT (1 << 2)
73#define DMA_CHAN_MODE_MSK 0x0000000c
74#define DMA_CHAN_MODE_AUTO 0
75#define DMA_CHAN_MODE_BURST 1
76#define DMA_CHAN_MODE_XFRT 2
77#define DMA_CHAN_MODE_RSVD 3
78#define DMA_CHAN_ACT_BIT (1 << 4)
79
80/* DMA status registers */
81#define DMA_STAT_FINI (1 << 0)
82#define DMA_STAT_DONE (1 << 1)
83#define DMA_STAT_CHAIN (1 << 2)
84#define DMA_STAT_ERR (1 << 3)
85#define DMA_STAT_HALT (1 << 4)
86
87/*
88 * DMA channel definitions
89 */
90
91#define DMA_CHAN_ETH_RCV 0
92#define DMA_CHAN_ETH_XMT 1
93#define DMA_CHAN_MEM_TO_FIFO 2
94#define DMA_CHAN_FIFO_TO_MEM 3
95#define DMA_CHAN_PCI_TO_MEM 4
96#define DMA_CHAN_MEM_TO_PCI 5
97#define DMA_CHAN_COUNT 6
98
99struct dma_channel {
100 struct dma_reg ch[DMA_CHAN_COUNT];
101};
102
103#endif /* __ASM_RC32434_DMA_H */
1/*
2 * Copyright 2002 Integrated Device Technology, Inc.
3 * All rights reserved.
4 *
5 * DMA register definition.
6 *
7 * Author : ryan.holmQVist@idt.com
8 * Date : 20011005
9 */
10
11#ifndef __ASM_RC32434_DMA_H
12#define __ASM_RC32434_DMA_H
13
14#include <asm/mach-rc32434/rb.h>
15
16#define DMA0_BASE_ADDR 0x18040000
17
18/*
19 * DMA descriptor (in physical memory).
20 */
21
22struct dma_desc {
23 u32 control; /* Control. use DMAD_* */
24 u32 ca; /* Current Address. */
25 u32 devcs; /* Device control and status. */
26 u32 link; /* Next descriptor in chain. */
27};
28
29#define DMA_DESC_SIZ sizeof(struct dma_desc)
30#define DMA_DESC_COUNT_BIT 0
31#define DMA_DESC_COUNT_MSK 0x0003ffff
32#define DMA_DESC_DS_BIT 20
33#define DMA_DESC_DS_MSK 0x00300000
34
35#define DMA_DESC_DEV_CMD_BIT 22
36#define DMA_DESC_DEV_CMD_MSK 0x01c00000
37
38/* DMA command sizes */
39#define DMA_DESC_DEV_CMD_BYTE 0
40#define DMA_DESC_DEV_CMD_HLF_WD 1
41#define DMA_DESC_DEV_CMD_WORD 2
42#define DMA_DESC_DEV_CMD_2WORDS 3
43#define DMA_DESC_DEV_CMD_4WORDS 4
44#define DMA_DESC_DEV_CMD_6WORDS 5
45#define DMA_DESC_DEV_CMD_8WORDS 6
46#define DMA_DESC_DEV_CMD_16WORDS 7
47
48/* DMA descriptors interrupts */
49#define DMA_DESC_COF (1 << 25) /* Chain on finished */
50#define DMA_DESC_COD (1 << 26) /* Chain on done */
51#define DMA_DESC_IOF (1 << 27) /* Interrupt on finished */
52#define DMA_DESC_IOD (1 << 28) /* Interrupt on done */
53#define DMA_DESC_TERM (1 << 29) /* Terminated */
54#define DMA_DESC_DONE (1 << 30) /* Done */
55#define DMA_DESC_FINI (1 << 31) /* Finished */
56
57/*
58 * DMA register (within Internal Register Map).
59 */
60
61struct dma_reg {
62 u32 dmac; /* Control. */
63 u32 dmas; /* Status. */
64 u32 dmasm; /* Mask. */
65 u32 dmadptr; /* Descriptor pointer. */
66 u32 dmandptr; /* Next descriptor pointer. */
67};
68
69/* DMA channels specific registers */
70#define DMA_CHAN_RUN_BIT (1 << 0)
71#define DMA_CHAN_DONE_BIT (1 << 1)
72#define DMA_CHAN_MODE_BIT (1 << 2)
73#define DMA_CHAN_MODE_MSK 0x0000000c
74#define DMA_CHAN_MODE_AUTO 0
75#define DMA_CHAN_MODE_BURST 1
76#define DMA_CHAN_MODE_XFRT 2
77#define DMA_CHAN_MODE_RSVD 3
78#define DMA_CHAN_ACT_BIT (1 << 4)
79
80/* DMA status registers */
81#define DMA_STAT_FINI (1 << 0)
82#define DMA_STAT_DONE (1 << 1)
83#define DMA_STAT_CHAIN (1 << 2)
84#define DMA_STAT_ERR (1 << 3)
85#define DMA_STAT_HALT (1 << 4)
86
87/*
88 * DMA channel definitions
89 */
90
91#define DMA_CHAN_ETH_RCV 0
92#define DMA_CHAN_ETH_XMT 1
93#define DMA_CHAN_MEM_TO_FIFO 2
94#define DMA_CHAN_FIFO_TO_MEM 3
95#define DMA_CHAN_PCI_TO_MEM 4
96#define DMA_CHAN_MEM_TO_PCI 5
97#define DMA_CHAN_COUNT 6
98
99struct dma_channel {
100 struct dma_reg ch[DMA_CHAN_COUNT];
101};
102
103#endif /* __ASM_RC32434_DMA_H */