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1/*
2 * linux/arch/arm/mm/mmu.c
3 *
4 * Copyright (C) 1995-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/mman.h>
15#include <linux/nodemask.h>
16#include <linux/memblock.h>
17#include <linux/fs.h>
18#include <linux/vmalloc.h>
19#include <linux/sizes.h>
20
21#include <asm/cp15.h>
22#include <asm/cputype.h>
23#include <asm/sections.h>
24#include <asm/cachetype.h>
25#include <asm/sections.h>
26#include <asm/setup.h>
27#include <asm/smp_plat.h>
28#include <asm/tlb.h>
29#include <asm/highmem.h>
30#include <asm/system_info.h>
31#include <asm/traps.h>
32#include <asm/procinfo.h>
33#include <asm/memory.h>
34
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/pci.h>
38
39#include "mm.h"
40#include "tcm.h"
41
42/*
43 * empty_zero_page is a special page that is used for
44 * zero-initialized data and COW.
45 */
46struct page *empty_zero_page;
47EXPORT_SYMBOL(empty_zero_page);
48
49/*
50 * The pmd table for the upper-most set of pages.
51 */
52pmd_t *top_pmd;
53
54#define CPOLICY_UNCACHED 0
55#define CPOLICY_BUFFERED 1
56#define CPOLICY_WRITETHROUGH 2
57#define CPOLICY_WRITEBACK 3
58#define CPOLICY_WRITEALLOC 4
59
60static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
61static unsigned int ecc_mask __initdata = 0;
62pgprot_t pgprot_user;
63pgprot_t pgprot_kernel;
64pgprot_t pgprot_hyp_device;
65pgprot_t pgprot_s2;
66pgprot_t pgprot_s2_device;
67
68EXPORT_SYMBOL(pgprot_user);
69EXPORT_SYMBOL(pgprot_kernel);
70
71struct cachepolicy {
72 const char policy[16];
73 unsigned int cr_mask;
74 pmdval_t pmd;
75 pteval_t pte;
76 pteval_t pte_s2;
77};
78
79#ifdef CONFIG_ARM_LPAE
80#define s2_policy(policy) policy
81#else
82#define s2_policy(policy) 0
83#endif
84
85static struct cachepolicy cache_policies[] __initdata = {
86 {
87 .policy = "uncached",
88 .cr_mask = CR_W|CR_C,
89 .pmd = PMD_SECT_UNCACHED,
90 .pte = L_PTE_MT_UNCACHED,
91 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
92 }, {
93 .policy = "buffered",
94 .cr_mask = CR_C,
95 .pmd = PMD_SECT_BUFFERED,
96 .pte = L_PTE_MT_BUFFERABLE,
97 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
98 }, {
99 .policy = "writethrough",
100 .cr_mask = 0,
101 .pmd = PMD_SECT_WT,
102 .pte = L_PTE_MT_WRITETHROUGH,
103 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
104 }, {
105 .policy = "writeback",
106 .cr_mask = 0,
107 .pmd = PMD_SECT_WB,
108 .pte = L_PTE_MT_WRITEBACK,
109 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
110 }, {
111 .policy = "writealloc",
112 .cr_mask = 0,
113 .pmd = PMD_SECT_WBWA,
114 .pte = L_PTE_MT_WRITEALLOC,
115 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
116 }
117};
118
119#ifdef CONFIG_CPU_CP15
120/*
121 * These are useful for identifying cache coherency
122 * problems by allowing the cache or the cache and
123 * writebuffer to be turned off. (Note: the write
124 * buffer should not be on and the cache off).
125 */
126static int __init early_cachepolicy(char *p)
127{
128 int i;
129
130 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
131 int len = strlen(cache_policies[i].policy);
132
133 if (memcmp(p, cache_policies[i].policy, len) == 0) {
134 cachepolicy = i;
135 cr_alignment &= ~cache_policies[i].cr_mask;
136 cr_no_alignment &= ~cache_policies[i].cr_mask;
137 break;
138 }
139 }
140 if (i == ARRAY_SIZE(cache_policies))
141 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
142 /*
143 * This restriction is partly to do with the way we boot; it is
144 * unpredictable to have memory mapped using two different sets of
145 * memory attributes (shared, type, and cache attribs). We can not
146 * change these attributes once the initial assembly has setup the
147 * page tables.
148 */
149 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
150 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
151 cachepolicy = CPOLICY_WRITEBACK;
152 }
153 flush_cache_all();
154 set_cr(cr_alignment);
155 return 0;
156}
157early_param("cachepolicy", early_cachepolicy);
158
159static int __init early_nocache(char *__unused)
160{
161 char *p = "buffered";
162 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
163 early_cachepolicy(p);
164 return 0;
165}
166early_param("nocache", early_nocache);
167
168static int __init early_nowrite(char *__unused)
169{
170 char *p = "uncached";
171 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
172 early_cachepolicy(p);
173 return 0;
174}
175early_param("nowb", early_nowrite);
176
177#ifndef CONFIG_ARM_LPAE
178static int __init early_ecc(char *p)
179{
180 if (memcmp(p, "on", 2) == 0)
181 ecc_mask = PMD_PROTECTION;
182 else if (memcmp(p, "off", 3) == 0)
183 ecc_mask = 0;
184 return 0;
185}
186early_param("ecc", early_ecc);
187#endif
188
189static int __init noalign_setup(char *__unused)
190{
191 cr_alignment &= ~CR_A;
192 cr_no_alignment &= ~CR_A;
193 set_cr(cr_alignment);
194 return 1;
195}
196__setup("noalign", noalign_setup);
197
198#ifndef CONFIG_SMP
199void adjust_cr(unsigned long mask, unsigned long set)
200{
201 unsigned long flags;
202
203 mask &= ~CR_A;
204
205 set &= mask;
206
207 local_irq_save(flags);
208
209 cr_no_alignment = (cr_no_alignment & ~mask) | set;
210 cr_alignment = (cr_alignment & ~mask) | set;
211
212 set_cr((get_cr() & ~mask) | set);
213
214 local_irq_restore(flags);
215}
216#endif
217
218#else /* ifdef CONFIG_CPU_CP15 */
219
220static int __init early_cachepolicy(char *p)
221{
222 pr_warning("cachepolicy kernel parameter not supported without cp15\n");
223}
224early_param("cachepolicy", early_cachepolicy);
225
226static int __init noalign_setup(char *__unused)
227{
228 pr_warning("noalign kernel parameter not supported without cp15\n");
229}
230__setup("noalign", noalign_setup);
231
232#endif /* ifdef CONFIG_CPU_CP15 / else */
233
234#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
235#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
236#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
237
238static struct mem_type mem_types[] = {
239 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
240 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
241 L_PTE_SHARED,
242 .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
243 s2_policy(L_PTE_S2_MT_DEV_SHARED) |
244 L_PTE_SHARED,
245 .prot_l1 = PMD_TYPE_TABLE,
246 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
247 .domain = DOMAIN_IO,
248 },
249 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
250 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
251 .prot_l1 = PMD_TYPE_TABLE,
252 .prot_sect = PROT_SECT_DEVICE,
253 .domain = DOMAIN_IO,
254 },
255 [MT_DEVICE_CACHED] = { /* ioremap_cached */
256 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
257 .prot_l1 = PMD_TYPE_TABLE,
258 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
259 .domain = DOMAIN_IO,
260 },
261 [MT_DEVICE_WC] = { /* ioremap_wc */
262 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
263 .prot_l1 = PMD_TYPE_TABLE,
264 .prot_sect = PROT_SECT_DEVICE,
265 .domain = DOMAIN_IO,
266 },
267 [MT_UNCACHED] = {
268 .prot_pte = PROT_PTE_DEVICE,
269 .prot_l1 = PMD_TYPE_TABLE,
270 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
271 .domain = DOMAIN_IO,
272 },
273 [MT_CACHECLEAN] = {
274 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
275 .domain = DOMAIN_KERNEL,
276 },
277#ifndef CONFIG_ARM_LPAE
278 [MT_MINICLEAN] = {
279 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
280 .domain = DOMAIN_KERNEL,
281 },
282#endif
283 [MT_LOW_VECTORS] = {
284 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
285 L_PTE_RDONLY,
286 .prot_l1 = PMD_TYPE_TABLE,
287 .domain = DOMAIN_USER,
288 },
289 [MT_HIGH_VECTORS] = {
290 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
291 L_PTE_USER | L_PTE_RDONLY,
292 .prot_l1 = PMD_TYPE_TABLE,
293 .domain = DOMAIN_USER,
294 },
295 [MT_MEMORY_RWX] = {
296 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
297 .prot_l1 = PMD_TYPE_TABLE,
298 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
299 .domain = DOMAIN_KERNEL,
300 },
301 [MT_MEMORY_RW] = {
302 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
303 L_PTE_XN,
304 .prot_l1 = PMD_TYPE_TABLE,
305 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
306 .domain = DOMAIN_KERNEL,
307 },
308 [MT_ROM] = {
309 .prot_sect = PMD_TYPE_SECT,
310 .domain = DOMAIN_KERNEL,
311 },
312 [MT_MEMORY_RWX_NONCACHED] = {
313 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
314 L_PTE_MT_BUFFERABLE,
315 .prot_l1 = PMD_TYPE_TABLE,
316 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
317 .domain = DOMAIN_KERNEL,
318 },
319 [MT_MEMORY_RW_DTCM] = {
320 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
321 L_PTE_XN,
322 .prot_l1 = PMD_TYPE_TABLE,
323 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
324 .domain = DOMAIN_KERNEL,
325 },
326 [MT_MEMORY_RWX_ITCM] = {
327 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
328 .prot_l1 = PMD_TYPE_TABLE,
329 .domain = DOMAIN_KERNEL,
330 },
331 [MT_MEMORY_RW_SO] = {
332 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
333 L_PTE_MT_UNCACHED | L_PTE_XN,
334 .prot_l1 = PMD_TYPE_TABLE,
335 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
336 PMD_SECT_UNCACHED | PMD_SECT_XN,
337 .domain = DOMAIN_KERNEL,
338 },
339 [MT_MEMORY_DMA_READY] = {
340 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
341 L_PTE_XN,
342 .prot_l1 = PMD_TYPE_TABLE,
343 .domain = DOMAIN_KERNEL,
344 },
345};
346
347const struct mem_type *get_mem_type(unsigned int type)
348{
349 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
350}
351EXPORT_SYMBOL(get_mem_type);
352
353#define PTE_SET_FN(_name, pteop) \
354static int pte_set_##_name(pte_t *ptep, pgtable_t token, unsigned long addr, \
355 void *data) \
356{ \
357 pte_t pte = pteop(*ptep); \
358\
359 set_pte_ext(ptep, pte, 0); \
360 return 0; \
361} \
362
363#define SET_MEMORY_FN(_name, callback) \
364int set_memory_##_name(unsigned long addr, int numpages) \
365{ \
366 unsigned long start = addr; \
367 unsigned long size = PAGE_SIZE*numpages; \
368 unsigned end = start + size; \
369\
370 if (start < MODULES_VADDR || start >= MODULES_END) \
371 return -EINVAL;\
372\
373 if (end < MODULES_VADDR || end >= MODULES_END) \
374 return -EINVAL; \
375\
376 apply_to_page_range(&init_mm, start, size, callback, NULL); \
377 flush_tlb_kernel_range(start, end); \
378 return 0;\
379}
380
381PTE_SET_FN(ro, pte_wrprotect)
382PTE_SET_FN(rw, pte_mkwrite)
383PTE_SET_FN(x, pte_mkexec)
384PTE_SET_FN(nx, pte_mknexec)
385
386SET_MEMORY_FN(ro, pte_set_ro)
387SET_MEMORY_FN(rw, pte_set_rw)
388SET_MEMORY_FN(x, pte_set_x)
389SET_MEMORY_FN(nx, pte_set_nx)
390
391/*
392 * Adjust the PMD section entries according to the CPU in use.
393 */
394static void __init build_mem_type_table(void)
395{
396 struct cachepolicy *cp;
397 unsigned int cr = get_cr();
398 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
399 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
400 int cpu_arch = cpu_architecture();
401 int i;
402
403 if (cpu_arch < CPU_ARCH_ARMv6) {
404#if defined(CONFIG_CPU_DCACHE_DISABLE)
405 if (cachepolicy > CPOLICY_BUFFERED)
406 cachepolicy = CPOLICY_BUFFERED;
407#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
408 if (cachepolicy > CPOLICY_WRITETHROUGH)
409 cachepolicy = CPOLICY_WRITETHROUGH;
410#endif
411 }
412 if (cpu_arch < CPU_ARCH_ARMv5) {
413 if (cachepolicy >= CPOLICY_WRITEALLOC)
414 cachepolicy = CPOLICY_WRITEBACK;
415 ecc_mask = 0;
416 }
417 if (is_smp())
418 cachepolicy = CPOLICY_WRITEALLOC;
419
420 /*
421 * Strip out features not present on earlier architectures.
422 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
423 * without extended page tables don't have the 'Shared' bit.
424 */
425 if (cpu_arch < CPU_ARCH_ARMv5)
426 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
427 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
428 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
429 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
430 mem_types[i].prot_sect &= ~PMD_SECT_S;
431
432 /*
433 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
434 * "update-able on write" bit on ARM610). However, Xscale and
435 * Xscale3 require this bit to be cleared.
436 */
437 if (cpu_is_xscale() || cpu_is_xsc3()) {
438 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
439 mem_types[i].prot_sect &= ~PMD_BIT4;
440 mem_types[i].prot_l1 &= ~PMD_BIT4;
441 }
442 } else if (cpu_arch < CPU_ARCH_ARMv6) {
443 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
444 if (mem_types[i].prot_l1)
445 mem_types[i].prot_l1 |= PMD_BIT4;
446 if (mem_types[i].prot_sect)
447 mem_types[i].prot_sect |= PMD_BIT4;
448 }
449 }
450
451 /*
452 * Mark the device areas according to the CPU/architecture.
453 */
454 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
455 if (!cpu_is_xsc3()) {
456 /*
457 * Mark device regions on ARMv6+ as execute-never
458 * to prevent speculative instruction fetches.
459 */
460 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
461 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
462 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
463 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
464
465 /* Also setup NX memory mapping */
466 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
467 }
468 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
469 /*
470 * For ARMv7 with TEX remapping,
471 * - shared device is SXCB=1100
472 * - nonshared device is SXCB=0100
473 * - write combine device mem is SXCB=0001
474 * (Uncached Normal memory)
475 */
476 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
477 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
478 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
479 } else if (cpu_is_xsc3()) {
480 /*
481 * For Xscale3,
482 * - shared device is TEXCB=00101
483 * - nonshared device is TEXCB=01000
484 * - write combine device mem is TEXCB=00100
485 * (Inner/Outer Uncacheable in xsc3 parlance)
486 */
487 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
488 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
489 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
490 } else {
491 /*
492 * For ARMv6 and ARMv7 without TEX remapping,
493 * - shared device is TEXCB=00001
494 * - nonshared device is TEXCB=01000
495 * - write combine device mem is TEXCB=00100
496 * (Uncached Normal in ARMv6 parlance).
497 */
498 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
499 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
500 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
501 }
502 } else {
503 /*
504 * On others, write combining is "Uncached/Buffered"
505 */
506 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
507 }
508
509 /*
510 * Now deal with the memory-type mappings
511 */
512 cp = &cache_policies[cachepolicy];
513 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
514 s2_pgprot = cp->pte_s2;
515 hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
516 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
517
518 /*
519 * We don't use domains on ARMv6 (since this causes problems with
520 * v6/v7 kernels), so we must use a separate memory type for user
521 * r/o, kernel r/w to map the vectors page.
522 */
523#ifndef CONFIG_ARM_LPAE
524 if (cpu_arch == CPU_ARCH_ARMv6)
525 vecs_pgprot |= L_PTE_MT_VECTORS;
526#endif
527
528 /*
529 * ARMv6 and above have extended page tables.
530 */
531 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
532#ifndef CONFIG_ARM_LPAE
533 /*
534 * Mark cache clean areas and XIP ROM read only
535 * from SVC mode and no access from userspace.
536 */
537 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
538 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
539 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
540#endif
541
542 if (is_smp()) {
543 /*
544 * Mark memory with the "shared" attribute
545 * for SMP systems
546 */
547 user_pgprot |= L_PTE_SHARED;
548 kern_pgprot |= L_PTE_SHARED;
549 vecs_pgprot |= L_PTE_SHARED;
550 s2_pgprot |= L_PTE_SHARED;
551 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
552 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
553 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
554 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
555 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
556 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
557 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
558 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
559 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
560 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
561 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
562 }
563 }
564
565 /*
566 * Non-cacheable Normal - intended for memory areas that must
567 * not cause dirty cache line writebacks when used
568 */
569 if (cpu_arch >= CPU_ARCH_ARMv6) {
570 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
571 /* Non-cacheable Normal is XCB = 001 */
572 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
573 PMD_SECT_BUFFERED;
574 } else {
575 /* For both ARMv6 and non-TEX-remapping ARMv7 */
576 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
577 PMD_SECT_TEX(1);
578 }
579 } else {
580 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
581 }
582
583#ifdef CONFIG_ARM_LPAE
584 /*
585 * Do not generate access flag faults for the kernel mappings.
586 */
587 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
588 mem_types[i].prot_pte |= PTE_EXT_AF;
589 if (mem_types[i].prot_sect)
590 mem_types[i].prot_sect |= PMD_SECT_AF;
591 }
592 kern_pgprot |= PTE_EXT_AF;
593 vecs_pgprot |= PTE_EXT_AF;
594#endif
595
596 for (i = 0; i < 16; i++) {
597 pteval_t v = pgprot_val(protection_map[i]);
598 protection_map[i] = __pgprot(v | user_pgprot);
599 }
600
601 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
602 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
603
604 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
605 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
606 L_PTE_DIRTY | kern_pgprot);
607 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
608 pgprot_s2_device = __pgprot(s2_device_pgprot);
609 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
610
611 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
612 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
613 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
614 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
615 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
616 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
617 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
618 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
619 mem_types[MT_ROM].prot_sect |= cp->pmd;
620
621 switch (cp->pmd) {
622 case PMD_SECT_WT:
623 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
624 break;
625 case PMD_SECT_WB:
626 case PMD_SECT_WBWA:
627 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
628 break;
629 }
630 pr_info("Memory policy: %sData cache %s\n",
631 ecc_mask ? "ECC enabled, " : "", cp->policy);
632
633 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
634 struct mem_type *t = &mem_types[i];
635 if (t->prot_l1)
636 t->prot_l1 |= PMD_DOMAIN(t->domain);
637 if (t->prot_sect)
638 t->prot_sect |= PMD_DOMAIN(t->domain);
639 }
640}
641
642#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
643pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
644 unsigned long size, pgprot_t vma_prot)
645{
646 if (!pfn_valid(pfn))
647 return pgprot_noncached(vma_prot);
648 else if (file->f_flags & O_SYNC)
649 return pgprot_writecombine(vma_prot);
650 return vma_prot;
651}
652EXPORT_SYMBOL(phys_mem_access_prot);
653#endif
654
655#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
656
657static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
658{
659 void *ptr = __va(memblock_alloc(sz, align));
660 memset(ptr, 0, sz);
661 return ptr;
662}
663
664static void __init *early_alloc(unsigned long sz)
665{
666 return early_alloc_aligned(sz, sz);
667}
668
669static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
670{
671 if (pmd_none(*pmd)) {
672 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
673 __pmd_populate(pmd, __pa(pte), prot);
674 }
675 BUG_ON(pmd_bad(*pmd));
676 return pte_offset_kernel(pmd, addr);
677}
678
679static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
680 unsigned long end, unsigned long pfn,
681 const struct mem_type *type)
682{
683 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
684 do {
685 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
686 pfn++;
687 } while (pte++, addr += PAGE_SIZE, addr != end);
688}
689
690static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
691 unsigned long end, phys_addr_t phys,
692 const struct mem_type *type)
693{
694 pmd_t *p = pmd;
695
696#ifndef CONFIG_ARM_LPAE
697 /*
698 * In classic MMU format, puds and pmds are folded in to
699 * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
700 * group of L1 entries making up one logical pointer to
701 * an L2 table (2MB), where as PMDs refer to the individual
702 * L1 entries (1MB). Hence increment to get the correct
703 * offset for odd 1MB sections.
704 * (See arch/arm/include/asm/pgtable-2level.h)
705 */
706 if (addr & SECTION_SIZE)
707 pmd++;
708#endif
709 do {
710 *pmd = __pmd(phys | type->prot_sect);
711 phys += SECTION_SIZE;
712 } while (pmd++, addr += SECTION_SIZE, addr != end);
713
714 flush_pmd_entry(p);
715}
716
717static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
718 unsigned long end, phys_addr_t phys,
719 const struct mem_type *type)
720{
721 pmd_t *pmd = pmd_offset(pud, addr);
722 unsigned long next;
723
724 do {
725 /*
726 * With LPAE, we must loop over to map
727 * all the pmds for the given range.
728 */
729 next = pmd_addr_end(addr, end);
730
731 /*
732 * Try a section mapping - addr, next and phys must all be
733 * aligned to a section boundary.
734 */
735 if (type->prot_sect &&
736 ((addr | next | phys) & ~SECTION_MASK) == 0) {
737 __map_init_section(pmd, addr, next, phys, type);
738 } else {
739 alloc_init_pte(pmd, addr, next,
740 __phys_to_pfn(phys), type);
741 }
742
743 phys += next - addr;
744
745 } while (pmd++, addr = next, addr != end);
746}
747
748static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
749 unsigned long end, phys_addr_t phys,
750 const struct mem_type *type)
751{
752 pud_t *pud = pud_offset(pgd, addr);
753 unsigned long next;
754
755 do {
756 next = pud_addr_end(addr, end);
757 alloc_init_pmd(pud, addr, next, phys, type);
758 phys += next - addr;
759 } while (pud++, addr = next, addr != end);
760}
761
762#ifndef CONFIG_ARM_LPAE
763static void __init create_36bit_mapping(struct map_desc *md,
764 const struct mem_type *type)
765{
766 unsigned long addr, length, end;
767 phys_addr_t phys;
768 pgd_t *pgd;
769
770 addr = md->virtual;
771 phys = __pfn_to_phys(md->pfn);
772 length = PAGE_ALIGN(md->length);
773
774 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
775 printk(KERN_ERR "MM: CPU does not support supersection "
776 "mapping for 0x%08llx at 0x%08lx\n",
777 (long long)__pfn_to_phys((u64)md->pfn), addr);
778 return;
779 }
780
781 /* N.B. ARMv6 supersections are only defined to work with domain 0.
782 * Since domain assignments can in fact be arbitrary, the
783 * 'domain == 0' check below is required to insure that ARMv6
784 * supersections are only allocated for domain 0 regardless
785 * of the actual domain assignments in use.
786 */
787 if (type->domain) {
788 printk(KERN_ERR "MM: invalid domain in supersection "
789 "mapping for 0x%08llx at 0x%08lx\n",
790 (long long)__pfn_to_phys((u64)md->pfn), addr);
791 return;
792 }
793
794 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
795 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
796 " at 0x%08lx invalid alignment\n",
797 (long long)__pfn_to_phys((u64)md->pfn), addr);
798 return;
799 }
800
801 /*
802 * Shift bits [35:32] of address into bits [23:20] of PMD
803 * (See ARMv6 spec).
804 */
805 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
806
807 pgd = pgd_offset_k(addr);
808 end = addr + length;
809 do {
810 pud_t *pud = pud_offset(pgd, addr);
811 pmd_t *pmd = pmd_offset(pud, addr);
812 int i;
813
814 for (i = 0; i < 16; i++)
815 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
816
817 addr += SUPERSECTION_SIZE;
818 phys += SUPERSECTION_SIZE;
819 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
820 } while (addr != end);
821}
822#endif /* !CONFIG_ARM_LPAE */
823
824/*
825 * Create the page directory entries and any necessary
826 * page tables for the mapping specified by `md'. We
827 * are able to cope here with varying sizes and address
828 * offsets, and we take full advantage of sections and
829 * supersections.
830 */
831static void __init create_mapping(struct map_desc *md)
832{
833 unsigned long addr, length, end;
834 phys_addr_t phys;
835 const struct mem_type *type;
836 pgd_t *pgd;
837
838 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
839 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
840 " at 0x%08lx in user region\n",
841 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
842 return;
843 }
844
845 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
846 md->virtual >= PAGE_OFFSET &&
847 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
848 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
849 " at 0x%08lx out of vmalloc space\n",
850 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
851 }
852
853 type = &mem_types[md->type];
854
855#ifndef CONFIG_ARM_LPAE
856 /*
857 * Catch 36-bit addresses
858 */
859 if (md->pfn >= 0x100000) {
860 create_36bit_mapping(md, type);
861 return;
862 }
863#endif
864
865 addr = md->virtual & PAGE_MASK;
866 phys = __pfn_to_phys(md->pfn);
867 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
868
869 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
870 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
871 "be mapped using pages, ignoring.\n",
872 (long long)__pfn_to_phys(md->pfn), addr);
873 return;
874 }
875
876 pgd = pgd_offset_k(addr);
877 end = addr + length;
878 do {
879 unsigned long next = pgd_addr_end(addr, end);
880
881 alloc_init_pud(pgd, addr, next, phys, type);
882
883 phys += next - addr;
884 addr = next;
885 } while (pgd++, addr != end);
886}
887
888/*
889 * Create the architecture specific mappings
890 */
891void __init iotable_init(struct map_desc *io_desc, int nr)
892{
893 struct map_desc *md;
894 struct vm_struct *vm;
895 struct static_vm *svm;
896
897 if (!nr)
898 return;
899
900 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
901
902 for (md = io_desc; nr; md++, nr--) {
903 create_mapping(md);
904
905 vm = &svm->vm;
906 vm->addr = (void *)(md->virtual & PAGE_MASK);
907 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
908 vm->phys_addr = __pfn_to_phys(md->pfn);
909 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
910 vm->flags |= VM_ARM_MTYPE(md->type);
911 vm->caller = iotable_init;
912 add_static_vm_early(svm++);
913 }
914}
915
916void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
917 void *caller)
918{
919 struct vm_struct *vm;
920 struct static_vm *svm;
921
922 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
923
924 vm = &svm->vm;
925 vm->addr = (void *)addr;
926 vm->size = size;
927 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
928 vm->caller = caller;
929 add_static_vm_early(svm);
930}
931
932#ifndef CONFIG_ARM_LPAE
933
934/*
935 * The Linux PMD is made of two consecutive section entries covering 2MB
936 * (see definition in include/asm/pgtable-2level.h). However a call to
937 * create_mapping() may optimize static mappings by using individual
938 * 1MB section mappings. This leaves the actual PMD potentially half
939 * initialized if the top or bottom section entry isn't used, leaving it
940 * open to problems if a subsequent ioremap() or vmalloc() tries to use
941 * the virtual space left free by that unused section entry.
942 *
943 * Let's avoid the issue by inserting dummy vm entries covering the unused
944 * PMD halves once the static mappings are in place.
945 */
946
947static void __init pmd_empty_section_gap(unsigned long addr)
948{
949 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
950}
951
952static void __init fill_pmd_gaps(void)
953{
954 struct static_vm *svm;
955 struct vm_struct *vm;
956 unsigned long addr, next = 0;
957 pmd_t *pmd;
958
959 list_for_each_entry(svm, &static_vmlist, list) {
960 vm = &svm->vm;
961 addr = (unsigned long)vm->addr;
962 if (addr < next)
963 continue;
964
965 /*
966 * Check if this vm starts on an odd section boundary.
967 * If so and the first section entry for this PMD is free
968 * then we block the corresponding virtual address.
969 */
970 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
971 pmd = pmd_off_k(addr);
972 if (pmd_none(*pmd))
973 pmd_empty_section_gap(addr & PMD_MASK);
974 }
975
976 /*
977 * Then check if this vm ends on an odd section boundary.
978 * If so and the second section entry for this PMD is empty
979 * then we block the corresponding virtual address.
980 */
981 addr += vm->size;
982 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
983 pmd = pmd_off_k(addr) + 1;
984 if (pmd_none(*pmd))
985 pmd_empty_section_gap(addr);
986 }
987
988 /* no need to look at any vm entry until we hit the next PMD */
989 next = (addr + PMD_SIZE - 1) & PMD_MASK;
990 }
991}
992
993#else
994#define fill_pmd_gaps() do { } while (0)
995#endif
996
997#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
998static void __init pci_reserve_io(void)
999{
1000 struct static_vm *svm;
1001
1002 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1003 if (svm)
1004 return;
1005
1006 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1007}
1008#else
1009#define pci_reserve_io() do { } while (0)
1010#endif
1011
1012#ifdef CONFIG_DEBUG_LL
1013void __init debug_ll_io_init(void)
1014{
1015 struct map_desc map;
1016
1017 debug_ll_addr(&map.pfn, &map.virtual);
1018 if (!map.pfn || !map.virtual)
1019 return;
1020 map.pfn = __phys_to_pfn(map.pfn);
1021 map.virtual &= PAGE_MASK;
1022 map.length = PAGE_SIZE;
1023 map.type = MT_DEVICE;
1024 iotable_init(&map, 1);
1025}
1026#endif
1027
1028static void * __initdata vmalloc_min =
1029 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1030
1031/*
1032 * vmalloc=size forces the vmalloc area to be exactly 'size'
1033 * bytes. This can be used to increase (or decrease) the vmalloc
1034 * area - the default is 240m.
1035 */
1036static int __init early_vmalloc(char *arg)
1037{
1038 unsigned long vmalloc_reserve = memparse(arg, NULL);
1039
1040 if (vmalloc_reserve < SZ_16M) {
1041 vmalloc_reserve = SZ_16M;
1042 printk(KERN_WARNING
1043 "vmalloc area too small, limiting to %luMB\n",
1044 vmalloc_reserve >> 20);
1045 }
1046
1047 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1048 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1049 printk(KERN_WARNING
1050 "vmalloc area is too big, limiting to %luMB\n",
1051 vmalloc_reserve >> 20);
1052 }
1053
1054 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1055 return 0;
1056}
1057early_param("vmalloc", early_vmalloc);
1058
1059phys_addr_t arm_lowmem_limit __initdata = 0;
1060
1061void __init sanity_check_meminfo(void)
1062{
1063 phys_addr_t memblock_limit = 0;
1064 int i, j, highmem = 0;
1065 phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
1066
1067 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
1068 struct membank *bank = &meminfo.bank[j];
1069 phys_addr_t size_limit;
1070
1071 *bank = meminfo.bank[i];
1072 size_limit = bank->size;
1073
1074 if (bank->start >= vmalloc_limit)
1075 highmem = 1;
1076 else
1077 size_limit = vmalloc_limit - bank->start;
1078
1079 bank->highmem = highmem;
1080
1081#ifdef CONFIG_HIGHMEM
1082 /*
1083 * Split those memory banks which are partially overlapping
1084 * the vmalloc area greatly simplifying things later.
1085 */
1086 if (!highmem && bank->size > size_limit) {
1087 if (meminfo.nr_banks >= NR_BANKS) {
1088 printk(KERN_CRIT "NR_BANKS too low, "
1089 "ignoring high memory\n");
1090 } else {
1091 memmove(bank + 1, bank,
1092 (meminfo.nr_banks - i) * sizeof(*bank));
1093 meminfo.nr_banks++;
1094 i++;
1095 bank[1].size -= size_limit;
1096 bank[1].start = vmalloc_limit;
1097 bank[1].highmem = highmem = 1;
1098 j++;
1099 }
1100 bank->size = size_limit;
1101 }
1102#else
1103 /*
1104 * Highmem banks not allowed with !CONFIG_HIGHMEM.
1105 */
1106 if (highmem) {
1107 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1108 "(!CONFIG_HIGHMEM).\n",
1109 (unsigned long long)bank->start,
1110 (unsigned long long)bank->start + bank->size - 1);
1111 continue;
1112 }
1113
1114 /*
1115 * Check whether this memory bank would partially overlap
1116 * the vmalloc area.
1117 */
1118 if (bank->size > size_limit) {
1119 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1120 "to -%.8llx (vmalloc region overlap).\n",
1121 (unsigned long long)bank->start,
1122 (unsigned long long)bank->start + bank->size - 1,
1123 (unsigned long long)bank->start + size_limit - 1);
1124 bank->size = size_limit;
1125 }
1126#endif
1127 if (!bank->highmem) {
1128 phys_addr_t bank_end = bank->start + bank->size;
1129
1130 if (bank_end > arm_lowmem_limit)
1131 arm_lowmem_limit = bank_end;
1132
1133 /*
1134 * Find the first non-section-aligned page, and point
1135 * memblock_limit at it. This relies on rounding the
1136 * limit down to be section-aligned, which happens at
1137 * the end of this function.
1138 *
1139 * With this algorithm, the start or end of almost any
1140 * bank can be non-section-aligned. The only exception
1141 * is that the start of the bank 0 must be section-
1142 * aligned, since otherwise memory would need to be
1143 * allocated when mapping the start of bank 0, which
1144 * occurs before any free memory is mapped.
1145 */
1146 if (!memblock_limit) {
1147 if (!IS_ALIGNED(bank->start, SECTION_SIZE))
1148 memblock_limit = bank->start;
1149 else if (!IS_ALIGNED(bank_end, SECTION_SIZE))
1150 memblock_limit = bank_end;
1151 }
1152 }
1153 j++;
1154 }
1155#ifdef CONFIG_HIGHMEM
1156 if (highmem) {
1157 const char *reason = NULL;
1158
1159 if (cache_is_vipt_aliasing()) {
1160 /*
1161 * Interactions between kmap and other mappings
1162 * make highmem support with aliasing VIPT caches
1163 * rather difficult.
1164 */
1165 reason = "with VIPT aliasing cache";
1166 }
1167 if (reason) {
1168 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1169 reason);
1170 while (j > 0 && meminfo.bank[j - 1].highmem)
1171 j--;
1172 }
1173 }
1174#endif
1175 meminfo.nr_banks = j;
1176 high_memory = __va(arm_lowmem_limit - 1) + 1;
1177
1178 /*
1179 * Round the memblock limit down to a section size. This
1180 * helps to ensure that we will allocate memory from the
1181 * last full section, which should be mapped.
1182 */
1183 if (memblock_limit)
1184 memblock_limit = round_down(memblock_limit, SECTION_SIZE);
1185 if (!memblock_limit)
1186 memblock_limit = arm_lowmem_limit;
1187
1188 memblock_set_current_limit(memblock_limit);
1189}
1190
1191static inline void prepare_page_table(void)
1192{
1193 unsigned long addr;
1194 phys_addr_t end;
1195
1196 /*
1197 * Clear out all the mappings below the kernel image.
1198 */
1199 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1200 pmd_clear(pmd_off_k(addr));
1201
1202#ifdef CONFIG_XIP_KERNEL
1203 /* The XIP kernel is mapped in the module area -- skip over it */
1204 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1205#endif
1206 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1207 pmd_clear(pmd_off_k(addr));
1208
1209 /*
1210 * Find the end of the first block of lowmem.
1211 */
1212 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1213 if (end >= arm_lowmem_limit)
1214 end = arm_lowmem_limit;
1215
1216 /*
1217 * Clear out all the kernel space mappings, except for the first
1218 * memory bank, up to the vmalloc region.
1219 */
1220 for (addr = __phys_to_virt(end);
1221 addr < VMALLOC_START; addr += PMD_SIZE)
1222 pmd_clear(pmd_off_k(addr));
1223}
1224
1225#ifdef CONFIG_ARM_LPAE
1226/* the first page is reserved for pgd */
1227#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1228 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1229#else
1230#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1231#endif
1232
1233/*
1234 * Reserve the special regions of memory
1235 */
1236void __init arm_mm_memblock_reserve(void)
1237{
1238 /*
1239 * Reserve the page tables. These are already in use,
1240 * and can only be in node 0.
1241 */
1242 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1243
1244#ifdef CONFIG_SA1111
1245 /*
1246 * Because of the SA1111 DMA bug, we want to preserve our
1247 * precious DMA-able memory...
1248 */
1249 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1250#endif
1251}
1252
1253/*
1254 * Set up the device mappings. Since we clear out the page tables for all
1255 * mappings above VMALLOC_START, we will remove any debug device mappings.
1256 * This means you have to be careful how you debug this function, or any
1257 * called function. This means you can't use any function or debugging
1258 * method which may touch any device, otherwise the kernel _will_ crash.
1259 */
1260static void __init devicemaps_init(const struct machine_desc *mdesc)
1261{
1262 struct map_desc map;
1263 unsigned long addr;
1264 void *vectors;
1265
1266 /*
1267 * Allocate the vector page early.
1268 */
1269 vectors = early_alloc(PAGE_SIZE * 2);
1270
1271 early_trap_init(vectors);
1272
1273 for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1274 pmd_clear(pmd_off_k(addr));
1275
1276 /*
1277 * Map the kernel if it is XIP.
1278 * It is always first in the modulearea.
1279 */
1280#ifdef CONFIG_XIP_KERNEL
1281 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1282 map.virtual = MODULES_VADDR;
1283 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1284 map.type = MT_ROM;
1285 create_mapping(&map);
1286#endif
1287
1288 /*
1289 * Map the cache flushing regions.
1290 */
1291#ifdef FLUSH_BASE
1292 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1293 map.virtual = FLUSH_BASE;
1294 map.length = SZ_1M;
1295 map.type = MT_CACHECLEAN;
1296 create_mapping(&map);
1297#endif
1298#ifdef FLUSH_BASE_MINICACHE
1299 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1300 map.virtual = FLUSH_BASE_MINICACHE;
1301 map.length = SZ_1M;
1302 map.type = MT_MINICLEAN;
1303 create_mapping(&map);
1304#endif
1305
1306 /*
1307 * Create a mapping for the machine vectors at the high-vectors
1308 * location (0xffff0000). If we aren't using high-vectors, also
1309 * create a mapping at the low-vectors virtual address.
1310 */
1311 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1312 map.virtual = 0xffff0000;
1313 map.length = PAGE_SIZE;
1314#ifdef CONFIG_KUSER_HELPERS
1315 map.type = MT_HIGH_VECTORS;
1316#else
1317 map.type = MT_LOW_VECTORS;
1318#endif
1319 create_mapping(&map);
1320
1321 if (!vectors_high()) {
1322 map.virtual = 0;
1323 map.length = PAGE_SIZE * 2;
1324 map.type = MT_LOW_VECTORS;
1325 create_mapping(&map);
1326 }
1327
1328 /* Now create a kernel read-only mapping */
1329 map.pfn += 1;
1330 map.virtual = 0xffff0000 + PAGE_SIZE;
1331 map.length = PAGE_SIZE;
1332 map.type = MT_LOW_VECTORS;
1333 create_mapping(&map);
1334
1335 /*
1336 * Ask the machine support to map in the statically mapped devices.
1337 */
1338 if (mdesc->map_io)
1339 mdesc->map_io();
1340 else
1341 debug_ll_io_init();
1342 fill_pmd_gaps();
1343
1344 /* Reserve fixed i/o space in VMALLOC region */
1345 pci_reserve_io();
1346
1347 /*
1348 * Finally flush the caches and tlb to ensure that we're in a
1349 * consistent state wrt the writebuffer. This also ensures that
1350 * any write-allocated cache lines in the vector page are written
1351 * back. After this point, we can start to touch devices again.
1352 */
1353 local_flush_tlb_all();
1354 flush_cache_all();
1355}
1356
1357static void __init kmap_init(void)
1358{
1359#ifdef CONFIG_HIGHMEM
1360 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1361 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1362#endif
1363}
1364
1365static void __init map_lowmem(void)
1366{
1367 struct memblock_region *reg;
1368 unsigned long kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
1369 unsigned long kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1370
1371 /* Map all the lowmem memory banks. */
1372 for_each_memblock(memory, reg) {
1373 phys_addr_t start = reg->base;
1374 phys_addr_t end = start + reg->size;
1375 struct map_desc map;
1376
1377 if (end > arm_lowmem_limit)
1378 end = arm_lowmem_limit;
1379 if (start >= end)
1380 break;
1381
1382 if (end < kernel_x_start || start >= kernel_x_end) {
1383 map.pfn = __phys_to_pfn(start);
1384 map.virtual = __phys_to_virt(start);
1385 map.length = end - start;
1386 map.type = MT_MEMORY_RWX;
1387
1388 create_mapping(&map);
1389 } else {
1390 /* This better cover the entire kernel */
1391 if (start < kernel_x_start) {
1392 map.pfn = __phys_to_pfn(start);
1393 map.virtual = __phys_to_virt(start);
1394 map.length = kernel_x_start - start;
1395 map.type = MT_MEMORY_RW;
1396
1397 create_mapping(&map);
1398 }
1399
1400 map.pfn = __phys_to_pfn(kernel_x_start);
1401 map.virtual = __phys_to_virt(kernel_x_start);
1402 map.length = kernel_x_end - kernel_x_start;
1403 map.type = MT_MEMORY_RWX;
1404
1405 create_mapping(&map);
1406
1407 if (kernel_x_end < end) {
1408 map.pfn = __phys_to_pfn(kernel_x_end);
1409 map.virtual = __phys_to_virt(kernel_x_end);
1410 map.length = end - kernel_x_end;
1411 map.type = MT_MEMORY_RW;
1412
1413 create_mapping(&map);
1414 }
1415 }
1416 }
1417}
1418
1419#ifdef CONFIG_ARM_LPAE
1420/*
1421 * early_paging_init() recreates boot time page table setup, allowing machines
1422 * to switch over to a high (>4G) address space on LPAE systems
1423 */
1424void __init early_paging_init(const struct machine_desc *mdesc,
1425 struct proc_info_list *procinfo)
1426{
1427 pmdval_t pmdprot = procinfo->__cpu_mm_mmu_flags;
1428 unsigned long map_start, map_end;
1429 pgd_t *pgd0, *pgdk;
1430 pud_t *pud0, *pudk, *pud_start;
1431 pmd_t *pmd0, *pmdk;
1432 phys_addr_t phys;
1433 int i;
1434
1435 if (!(mdesc->init_meminfo))
1436 return;
1437
1438 /* remap kernel code and data */
1439 map_start = init_mm.start_code;
1440 map_end = init_mm.brk;
1441
1442 /* get a handle on things... */
1443 pgd0 = pgd_offset_k(0);
1444 pud_start = pud0 = pud_offset(pgd0, 0);
1445 pmd0 = pmd_offset(pud0, 0);
1446
1447 pgdk = pgd_offset_k(map_start);
1448 pudk = pud_offset(pgdk, map_start);
1449 pmdk = pmd_offset(pudk, map_start);
1450
1451 mdesc->init_meminfo();
1452
1453 /* Run the patch stub to update the constants */
1454 fixup_pv_table(&__pv_table_begin,
1455 (&__pv_table_end - &__pv_table_begin) << 2);
1456
1457 /*
1458 * Cache cleaning operations for self-modifying code
1459 * We should clean the entries by MVA but running a
1460 * for loop over every pv_table entry pointer would
1461 * just complicate the code.
1462 */
1463 flush_cache_louis();
1464 dsb();
1465 isb();
1466
1467 /* remap level 1 table */
1468 for (i = 0; i < PTRS_PER_PGD; pud0++, i++) {
1469 set_pud(pud0,
1470 __pud(__pa(pmd0) | PMD_TYPE_TABLE | L_PGD_SWAPPER));
1471 pmd0 += PTRS_PER_PMD;
1472 }
1473
1474 /* remap pmds for kernel mapping */
1475 phys = __pa(map_start) & PMD_MASK;
1476 do {
1477 *pmdk++ = __pmd(phys | pmdprot);
1478 phys += PMD_SIZE;
1479 } while (phys < map_end);
1480
1481 flush_cache_all();
1482 cpu_switch_mm(pgd0, &init_mm);
1483 cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET);
1484 local_flush_bp_all();
1485 local_flush_tlb_all();
1486}
1487
1488#else
1489
1490void __init early_paging_init(const struct machine_desc *mdesc,
1491 struct proc_info_list *procinfo)
1492{
1493 if (mdesc->init_meminfo)
1494 mdesc->init_meminfo();
1495}
1496
1497#endif
1498
1499/*
1500 * paging_init() sets up the page tables, initialises the zone memory
1501 * maps, and sets up the zero page, bad page and bad page tables.
1502 */
1503void __init paging_init(const struct machine_desc *mdesc)
1504{
1505 void *zero_page;
1506
1507 build_mem_type_table();
1508 prepare_page_table();
1509 map_lowmem();
1510 dma_contiguous_remap();
1511 devicemaps_init(mdesc);
1512 kmap_init();
1513 tcm_init();
1514
1515 top_pmd = pmd_off_k(0xffff0000);
1516
1517 /* allocate the zero page. */
1518 zero_page = early_alloc(PAGE_SIZE);
1519
1520 bootmem_init();
1521
1522 empty_zero_page = virt_to_page(zero_page);
1523 __flush_dcache_page(NULL, empty_zero_page);
1524}
1/*
2 * linux/arch/arm/mm/mmu.c
3 *
4 * Copyright (C) 1995-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/mman.h>
15#include <linux/nodemask.h>
16#include <linux/memblock.h>
17#include <linux/fs.h>
18#include <linux/vmalloc.h>
19
20#include <asm/cp15.h>
21#include <asm/cputype.h>
22#include <asm/sections.h>
23#include <asm/cachetype.h>
24#include <asm/setup.h>
25#include <asm/sizes.h>
26#include <asm/smp_plat.h>
27#include <asm/tlb.h>
28#include <asm/highmem.h>
29#include <asm/system_info.h>
30#include <asm/traps.h>
31
32#include <asm/mach/arch.h>
33#include <asm/mach/map.h>
34
35#include "mm.h"
36
37/*
38 * empty_zero_page is a special page that is used for
39 * zero-initialized data and COW.
40 */
41struct page *empty_zero_page;
42EXPORT_SYMBOL(empty_zero_page);
43
44/*
45 * The pmd table for the upper-most set of pages.
46 */
47pmd_t *top_pmd;
48
49#define CPOLICY_UNCACHED 0
50#define CPOLICY_BUFFERED 1
51#define CPOLICY_WRITETHROUGH 2
52#define CPOLICY_WRITEBACK 3
53#define CPOLICY_WRITEALLOC 4
54
55static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
56static unsigned int ecc_mask __initdata = 0;
57pgprot_t pgprot_user;
58pgprot_t pgprot_kernel;
59
60EXPORT_SYMBOL(pgprot_user);
61EXPORT_SYMBOL(pgprot_kernel);
62
63struct cachepolicy {
64 const char policy[16];
65 unsigned int cr_mask;
66 pmdval_t pmd;
67 pteval_t pte;
68};
69
70static struct cachepolicy cache_policies[] __initdata = {
71 {
72 .policy = "uncached",
73 .cr_mask = CR_W|CR_C,
74 .pmd = PMD_SECT_UNCACHED,
75 .pte = L_PTE_MT_UNCACHED,
76 }, {
77 .policy = "buffered",
78 .cr_mask = CR_C,
79 .pmd = PMD_SECT_BUFFERED,
80 .pte = L_PTE_MT_BUFFERABLE,
81 }, {
82 .policy = "writethrough",
83 .cr_mask = 0,
84 .pmd = PMD_SECT_WT,
85 .pte = L_PTE_MT_WRITETHROUGH,
86 }, {
87 .policy = "writeback",
88 .cr_mask = 0,
89 .pmd = PMD_SECT_WB,
90 .pte = L_PTE_MT_WRITEBACK,
91 }, {
92 .policy = "writealloc",
93 .cr_mask = 0,
94 .pmd = PMD_SECT_WBWA,
95 .pte = L_PTE_MT_WRITEALLOC,
96 }
97};
98
99/*
100 * These are useful for identifying cache coherency
101 * problems by allowing the cache or the cache and
102 * writebuffer to be turned off. (Note: the write
103 * buffer should not be on and the cache off).
104 */
105static int __init early_cachepolicy(char *p)
106{
107 int i;
108
109 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
110 int len = strlen(cache_policies[i].policy);
111
112 if (memcmp(p, cache_policies[i].policy, len) == 0) {
113 cachepolicy = i;
114 cr_alignment &= ~cache_policies[i].cr_mask;
115 cr_no_alignment &= ~cache_policies[i].cr_mask;
116 break;
117 }
118 }
119 if (i == ARRAY_SIZE(cache_policies))
120 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
121 /*
122 * This restriction is partly to do with the way we boot; it is
123 * unpredictable to have memory mapped using two different sets of
124 * memory attributes (shared, type, and cache attribs). We can not
125 * change these attributes once the initial assembly has setup the
126 * page tables.
127 */
128 if (cpu_architecture() >= CPU_ARCH_ARMv6) {
129 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
130 cachepolicy = CPOLICY_WRITEBACK;
131 }
132 flush_cache_all();
133 set_cr(cr_alignment);
134 return 0;
135}
136early_param("cachepolicy", early_cachepolicy);
137
138static int __init early_nocache(char *__unused)
139{
140 char *p = "buffered";
141 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
142 early_cachepolicy(p);
143 return 0;
144}
145early_param("nocache", early_nocache);
146
147static int __init early_nowrite(char *__unused)
148{
149 char *p = "uncached";
150 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
151 early_cachepolicy(p);
152 return 0;
153}
154early_param("nowb", early_nowrite);
155
156#ifndef CONFIG_ARM_LPAE
157static int __init early_ecc(char *p)
158{
159 if (memcmp(p, "on", 2) == 0)
160 ecc_mask = PMD_PROTECTION;
161 else if (memcmp(p, "off", 3) == 0)
162 ecc_mask = 0;
163 return 0;
164}
165early_param("ecc", early_ecc);
166#endif
167
168static int __init noalign_setup(char *__unused)
169{
170 cr_alignment &= ~CR_A;
171 cr_no_alignment &= ~CR_A;
172 set_cr(cr_alignment);
173 return 1;
174}
175__setup("noalign", noalign_setup);
176
177#ifndef CONFIG_SMP
178void adjust_cr(unsigned long mask, unsigned long set)
179{
180 unsigned long flags;
181
182 mask &= ~CR_A;
183
184 set &= mask;
185
186 local_irq_save(flags);
187
188 cr_no_alignment = (cr_no_alignment & ~mask) | set;
189 cr_alignment = (cr_alignment & ~mask) | set;
190
191 set_cr((get_cr() & ~mask) | set);
192
193 local_irq_restore(flags);
194}
195#endif
196
197#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
198#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
199
200static struct mem_type mem_types[] = {
201 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
202 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
203 L_PTE_SHARED,
204 .prot_l1 = PMD_TYPE_TABLE,
205 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
206 .domain = DOMAIN_IO,
207 },
208 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
209 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
210 .prot_l1 = PMD_TYPE_TABLE,
211 .prot_sect = PROT_SECT_DEVICE,
212 .domain = DOMAIN_IO,
213 },
214 [MT_DEVICE_CACHED] = { /* ioremap_cached */
215 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
216 .prot_l1 = PMD_TYPE_TABLE,
217 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
218 .domain = DOMAIN_IO,
219 },
220 [MT_DEVICE_WC] = { /* ioremap_wc */
221 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
222 .prot_l1 = PMD_TYPE_TABLE,
223 .prot_sect = PROT_SECT_DEVICE,
224 .domain = DOMAIN_IO,
225 },
226 [MT_UNCACHED] = {
227 .prot_pte = PROT_PTE_DEVICE,
228 .prot_l1 = PMD_TYPE_TABLE,
229 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
230 .domain = DOMAIN_IO,
231 },
232 [MT_CACHECLEAN] = {
233 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
234 .domain = DOMAIN_KERNEL,
235 },
236#ifndef CONFIG_ARM_LPAE
237 [MT_MINICLEAN] = {
238 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
239 .domain = DOMAIN_KERNEL,
240 },
241#endif
242 [MT_LOW_VECTORS] = {
243 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
244 L_PTE_RDONLY,
245 .prot_l1 = PMD_TYPE_TABLE,
246 .domain = DOMAIN_USER,
247 },
248 [MT_HIGH_VECTORS] = {
249 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
250 L_PTE_USER | L_PTE_RDONLY,
251 .prot_l1 = PMD_TYPE_TABLE,
252 .domain = DOMAIN_USER,
253 },
254 [MT_MEMORY] = {
255 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
256 .prot_l1 = PMD_TYPE_TABLE,
257 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
258 .domain = DOMAIN_KERNEL,
259 },
260 [MT_ROM] = {
261 .prot_sect = PMD_TYPE_SECT,
262 .domain = DOMAIN_KERNEL,
263 },
264 [MT_MEMORY_NONCACHED] = {
265 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
266 L_PTE_MT_BUFFERABLE,
267 .prot_l1 = PMD_TYPE_TABLE,
268 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
269 .domain = DOMAIN_KERNEL,
270 },
271 [MT_MEMORY_DTCM] = {
272 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
273 L_PTE_XN,
274 .prot_l1 = PMD_TYPE_TABLE,
275 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
276 .domain = DOMAIN_KERNEL,
277 },
278 [MT_MEMORY_ITCM] = {
279 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
280 .prot_l1 = PMD_TYPE_TABLE,
281 .domain = DOMAIN_KERNEL,
282 },
283 [MT_MEMORY_SO] = {
284 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
285 L_PTE_MT_UNCACHED,
286 .prot_l1 = PMD_TYPE_TABLE,
287 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
288 PMD_SECT_UNCACHED | PMD_SECT_XN,
289 .domain = DOMAIN_KERNEL,
290 },
291 [MT_MEMORY_DMA_READY] = {
292 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
293 .prot_l1 = PMD_TYPE_TABLE,
294 .domain = DOMAIN_KERNEL,
295 },
296};
297
298const struct mem_type *get_mem_type(unsigned int type)
299{
300 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
301}
302EXPORT_SYMBOL(get_mem_type);
303
304/*
305 * Adjust the PMD section entries according to the CPU in use.
306 */
307static void __init build_mem_type_table(void)
308{
309 struct cachepolicy *cp;
310 unsigned int cr = get_cr();
311 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
312 int cpu_arch = cpu_architecture();
313 int i;
314
315 if (cpu_arch < CPU_ARCH_ARMv6) {
316#if defined(CONFIG_CPU_DCACHE_DISABLE)
317 if (cachepolicy > CPOLICY_BUFFERED)
318 cachepolicy = CPOLICY_BUFFERED;
319#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
320 if (cachepolicy > CPOLICY_WRITETHROUGH)
321 cachepolicy = CPOLICY_WRITETHROUGH;
322#endif
323 }
324 if (cpu_arch < CPU_ARCH_ARMv5) {
325 if (cachepolicy >= CPOLICY_WRITEALLOC)
326 cachepolicy = CPOLICY_WRITEBACK;
327 ecc_mask = 0;
328 }
329 if (is_smp())
330 cachepolicy = CPOLICY_WRITEALLOC;
331
332 /*
333 * Strip out features not present on earlier architectures.
334 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
335 * without extended page tables don't have the 'Shared' bit.
336 */
337 if (cpu_arch < CPU_ARCH_ARMv5)
338 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
339 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
340 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
341 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
342 mem_types[i].prot_sect &= ~PMD_SECT_S;
343
344 /*
345 * ARMv5 and lower, bit 4 must be set for page tables (was: cache
346 * "update-able on write" bit on ARM610). However, Xscale and
347 * Xscale3 require this bit to be cleared.
348 */
349 if (cpu_is_xscale() || cpu_is_xsc3()) {
350 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
351 mem_types[i].prot_sect &= ~PMD_BIT4;
352 mem_types[i].prot_l1 &= ~PMD_BIT4;
353 }
354 } else if (cpu_arch < CPU_ARCH_ARMv6) {
355 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
356 if (mem_types[i].prot_l1)
357 mem_types[i].prot_l1 |= PMD_BIT4;
358 if (mem_types[i].prot_sect)
359 mem_types[i].prot_sect |= PMD_BIT4;
360 }
361 }
362
363 /*
364 * Mark the device areas according to the CPU/architecture.
365 */
366 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
367 if (!cpu_is_xsc3()) {
368 /*
369 * Mark device regions on ARMv6+ as execute-never
370 * to prevent speculative instruction fetches.
371 */
372 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
373 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
374 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
375 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
376 }
377 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
378 /*
379 * For ARMv7 with TEX remapping,
380 * - shared device is SXCB=1100
381 * - nonshared device is SXCB=0100
382 * - write combine device mem is SXCB=0001
383 * (Uncached Normal memory)
384 */
385 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
386 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
387 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
388 } else if (cpu_is_xsc3()) {
389 /*
390 * For Xscale3,
391 * - shared device is TEXCB=00101
392 * - nonshared device is TEXCB=01000
393 * - write combine device mem is TEXCB=00100
394 * (Inner/Outer Uncacheable in xsc3 parlance)
395 */
396 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
397 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
398 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
399 } else {
400 /*
401 * For ARMv6 and ARMv7 without TEX remapping,
402 * - shared device is TEXCB=00001
403 * - nonshared device is TEXCB=01000
404 * - write combine device mem is TEXCB=00100
405 * (Uncached Normal in ARMv6 parlance).
406 */
407 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
408 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
409 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
410 }
411 } else {
412 /*
413 * On others, write combining is "Uncached/Buffered"
414 */
415 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
416 }
417
418 /*
419 * Now deal with the memory-type mappings
420 */
421 cp = &cache_policies[cachepolicy];
422 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
423
424 /*
425 * Only use write-through for non-SMP systems
426 */
427 if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
428 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
429
430 /*
431 * Enable CPU-specific coherency if supported.
432 * (Only available on XSC3 at the moment.)
433 */
434 if (arch_is_coherent() && cpu_is_xsc3()) {
435 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
436 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
437 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
438 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
439 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
440 }
441 /*
442 * ARMv6 and above have extended page tables.
443 */
444 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
445#ifndef CONFIG_ARM_LPAE
446 /*
447 * Mark cache clean areas and XIP ROM read only
448 * from SVC mode and no access from userspace.
449 */
450 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
451 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
452 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
453#endif
454
455 if (is_smp()) {
456 /*
457 * Mark memory with the "shared" attribute
458 * for SMP systems
459 */
460 user_pgprot |= L_PTE_SHARED;
461 kern_pgprot |= L_PTE_SHARED;
462 vecs_pgprot |= L_PTE_SHARED;
463 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
464 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
465 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
466 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
467 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
468 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
469 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
470 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
471 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
472 }
473 }
474
475 /*
476 * Non-cacheable Normal - intended for memory areas that must
477 * not cause dirty cache line writebacks when used
478 */
479 if (cpu_arch >= CPU_ARCH_ARMv6) {
480 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
481 /* Non-cacheable Normal is XCB = 001 */
482 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
483 PMD_SECT_BUFFERED;
484 } else {
485 /* For both ARMv6 and non-TEX-remapping ARMv7 */
486 mem_types[MT_MEMORY_NONCACHED].prot_sect |=
487 PMD_SECT_TEX(1);
488 }
489 } else {
490 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
491 }
492
493#ifdef CONFIG_ARM_LPAE
494 /*
495 * Do not generate access flag faults for the kernel mappings.
496 */
497 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
498 mem_types[i].prot_pte |= PTE_EXT_AF;
499 if (mem_types[i].prot_sect)
500 mem_types[i].prot_sect |= PMD_SECT_AF;
501 }
502 kern_pgprot |= PTE_EXT_AF;
503 vecs_pgprot |= PTE_EXT_AF;
504#endif
505
506 for (i = 0; i < 16; i++) {
507 unsigned long v = pgprot_val(protection_map[i]);
508 protection_map[i] = __pgprot(v | user_pgprot);
509 }
510
511 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
512 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
513
514 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
515 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
516 L_PTE_DIRTY | kern_pgprot);
517
518 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
519 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
520 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
521 mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
522 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
523 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
524 mem_types[MT_ROM].prot_sect |= cp->pmd;
525
526 switch (cp->pmd) {
527 case PMD_SECT_WT:
528 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
529 break;
530 case PMD_SECT_WB:
531 case PMD_SECT_WBWA:
532 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
533 break;
534 }
535 printk("Memory policy: ECC %sabled, Data cache %s\n",
536 ecc_mask ? "en" : "dis", cp->policy);
537
538 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
539 struct mem_type *t = &mem_types[i];
540 if (t->prot_l1)
541 t->prot_l1 |= PMD_DOMAIN(t->domain);
542 if (t->prot_sect)
543 t->prot_sect |= PMD_DOMAIN(t->domain);
544 }
545}
546
547#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
548pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
549 unsigned long size, pgprot_t vma_prot)
550{
551 if (!pfn_valid(pfn))
552 return pgprot_noncached(vma_prot);
553 else if (file->f_flags & O_SYNC)
554 return pgprot_writecombine(vma_prot);
555 return vma_prot;
556}
557EXPORT_SYMBOL(phys_mem_access_prot);
558#endif
559
560#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
561
562static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
563{
564 void *ptr = __va(memblock_alloc(sz, align));
565 memset(ptr, 0, sz);
566 return ptr;
567}
568
569static void __init *early_alloc(unsigned long sz)
570{
571 return early_alloc_aligned(sz, sz);
572}
573
574static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
575{
576 if (pmd_none(*pmd)) {
577 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
578 __pmd_populate(pmd, __pa(pte), prot);
579 }
580 BUG_ON(pmd_bad(*pmd));
581 return pte_offset_kernel(pmd, addr);
582}
583
584static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
585 unsigned long end, unsigned long pfn,
586 const struct mem_type *type)
587{
588 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
589 do {
590 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
591 pfn++;
592 } while (pte++, addr += PAGE_SIZE, addr != end);
593}
594
595static void __init alloc_init_section(pud_t *pud, unsigned long addr,
596 unsigned long end, phys_addr_t phys,
597 const struct mem_type *type)
598{
599 pmd_t *pmd = pmd_offset(pud, addr);
600
601 /*
602 * Try a section mapping - end, addr and phys must all be aligned
603 * to a section boundary. Note that PMDs refer to the individual
604 * L1 entries, whereas PGDs refer to a group of L1 entries making
605 * up one logical pointer to an L2 table.
606 */
607 if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
608 pmd_t *p = pmd;
609
610#ifndef CONFIG_ARM_LPAE
611 if (addr & SECTION_SIZE)
612 pmd++;
613#endif
614
615 do {
616 *pmd = __pmd(phys | type->prot_sect);
617 phys += SECTION_SIZE;
618 } while (pmd++, addr += SECTION_SIZE, addr != end);
619
620 flush_pmd_entry(p);
621 } else {
622 /*
623 * No need to loop; pte's aren't interested in the
624 * individual L1 entries.
625 */
626 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
627 }
628}
629
630static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
631 unsigned long end, unsigned long phys, const struct mem_type *type)
632{
633 pud_t *pud = pud_offset(pgd, addr);
634 unsigned long next;
635
636 do {
637 next = pud_addr_end(addr, end);
638 alloc_init_section(pud, addr, next, phys, type);
639 phys += next - addr;
640 } while (pud++, addr = next, addr != end);
641}
642
643#ifndef CONFIG_ARM_LPAE
644static void __init create_36bit_mapping(struct map_desc *md,
645 const struct mem_type *type)
646{
647 unsigned long addr, length, end;
648 phys_addr_t phys;
649 pgd_t *pgd;
650
651 addr = md->virtual;
652 phys = __pfn_to_phys(md->pfn);
653 length = PAGE_ALIGN(md->length);
654
655 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
656 printk(KERN_ERR "MM: CPU does not support supersection "
657 "mapping for 0x%08llx at 0x%08lx\n",
658 (long long)__pfn_to_phys((u64)md->pfn), addr);
659 return;
660 }
661
662 /* N.B. ARMv6 supersections are only defined to work with domain 0.
663 * Since domain assignments can in fact be arbitrary, the
664 * 'domain == 0' check below is required to insure that ARMv6
665 * supersections are only allocated for domain 0 regardless
666 * of the actual domain assignments in use.
667 */
668 if (type->domain) {
669 printk(KERN_ERR "MM: invalid domain in supersection "
670 "mapping for 0x%08llx at 0x%08lx\n",
671 (long long)__pfn_to_phys((u64)md->pfn), addr);
672 return;
673 }
674
675 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
676 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
677 " at 0x%08lx invalid alignment\n",
678 (long long)__pfn_to_phys((u64)md->pfn), addr);
679 return;
680 }
681
682 /*
683 * Shift bits [35:32] of address into bits [23:20] of PMD
684 * (See ARMv6 spec).
685 */
686 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
687
688 pgd = pgd_offset_k(addr);
689 end = addr + length;
690 do {
691 pud_t *pud = pud_offset(pgd, addr);
692 pmd_t *pmd = pmd_offset(pud, addr);
693 int i;
694
695 for (i = 0; i < 16; i++)
696 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
697
698 addr += SUPERSECTION_SIZE;
699 phys += SUPERSECTION_SIZE;
700 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
701 } while (addr != end);
702}
703#endif /* !CONFIG_ARM_LPAE */
704
705/*
706 * Create the page directory entries and any necessary
707 * page tables for the mapping specified by `md'. We
708 * are able to cope here with varying sizes and address
709 * offsets, and we take full advantage of sections and
710 * supersections.
711 */
712static void __init create_mapping(struct map_desc *md)
713{
714 unsigned long addr, length, end;
715 phys_addr_t phys;
716 const struct mem_type *type;
717 pgd_t *pgd;
718
719 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
720 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
721 " at 0x%08lx in user region\n",
722 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
723 return;
724 }
725
726 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
727 md->virtual >= PAGE_OFFSET &&
728 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
729 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
730 " at 0x%08lx out of vmalloc space\n",
731 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
732 }
733
734 type = &mem_types[md->type];
735
736#ifndef CONFIG_ARM_LPAE
737 /*
738 * Catch 36-bit addresses
739 */
740 if (md->pfn >= 0x100000) {
741 create_36bit_mapping(md, type);
742 return;
743 }
744#endif
745
746 addr = md->virtual & PAGE_MASK;
747 phys = __pfn_to_phys(md->pfn);
748 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
749
750 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
751 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
752 "be mapped using pages, ignoring.\n",
753 (long long)__pfn_to_phys(md->pfn), addr);
754 return;
755 }
756
757 pgd = pgd_offset_k(addr);
758 end = addr + length;
759 do {
760 unsigned long next = pgd_addr_end(addr, end);
761
762 alloc_init_pud(pgd, addr, next, phys, type);
763
764 phys += next - addr;
765 addr = next;
766 } while (pgd++, addr != end);
767}
768
769/*
770 * Create the architecture specific mappings
771 */
772void __init iotable_init(struct map_desc *io_desc, int nr)
773{
774 struct map_desc *md;
775 struct vm_struct *vm;
776
777 if (!nr)
778 return;
779
780 vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm));
781
782 for (md = io_desc; nr; md++, nr--) {
783 create_mapping(md);
784 vm->addr = (void *)(md->virtual & PAGE_MASK);
785 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
786 vm->phys_addr = __pfn_to_phys(md->pfn);
787 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
788 vm->flags |= VM_ARM_MTYPE(md->type);
789 vm->caller = iotable_init;
790 vm_area_add_early(vm++);
791 }
792}
793
794#ifndef CONFIG_ARM_LPAE
795
796/*
797 * The Linux PMD is made of two consecutive section entries covering 2MB
798 * (see definition in include/asm/pgtable-2level.h). However a call to
799 * create_mapping() may optimize static mappings by using individual
800 * 1MB section mappings. This leaves the actual PMD potentially half
801 * initialized if the top or bottom section entry isn't used, leaving it
802 * open to problems if a subsequent ioremap() or vmalloc() tries to use
803 * the virtual space left free by that unused section entry.
804 *
805 * Let's avoid the issue by inserting dummy vm entries covering the unused
806 * PMD halves once the static mappings are in place.
807 */
808
809static void __init pmd_empty_section_gap(unsigned long addr)
810{
811 struct vm_struct *vm;
812
813 vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
814 vm->addr = (void *)addr;
815 vm->size = SECTION_SIZE;
816 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
817 vm->caller = pmd_empty_section_gap;
818 vm_area_add_early(vm);
819}
820
821static void __init fill_pmd_gaps(void)
822{
823 struct vm_struct *vm;
824 unsigned long addr, next = 0;
825 pmd_t *pmd;
826
827 /* we're still single threaded hence no lock needed here */
828 for (vm = vmlist; vm; vm = vm->next) {
829 if (!(vm->flags & (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING)))
830 continue;
831 addr = (unsigned long)vm->addr;
832 if (addr < next)
833 continue;
834
835 /*
836 * Check if this vm starts on an odd section boundary.
837 * If so and the first section entry for this PMD is free
838 * then we block the corresponding virtual address.
839 */
840 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
841 pmd = pmd_off_k(addr);
842 if (pmd_none(*pmd))
843 pmd_empty_section_gap(addr & PMD_MASK);
844 }
845
846 /*
847 * Then check if this vm ends on an odd section boundary.
848 * If so and the second section entry for this PMD is empty
849 * then we block the corresponding virtual address.
850 */
851 addr += vm->size;
852 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
853 pmd = pmd_off_k(addr) + 1;
854 if (pmd_none(*pmd))
855 pmd_empty_section_gap(addr);
856 }
857
858 /* no need to look at any vm entry until we hit the next PMD */
859 next = (addr + PMD_SIZE - 1) & PMD_MASK;
860 }
861}
862
863#else
864#define fill_pmd_gaps() do { } while (0)
865#endif
866
867static void * __initdata vmalloc_min =
868 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
869
870/*
871 * vmalloc=size forces the vmalloc area to be exactly 'size'
872 * bytes. This can be used to increase (or decrease) the vmalloc
873 * area - the default is 240m.
874 */
875static int __init early_vmalloc(char *arg)
876{
877 unsigned long vmalloc_reserve = memparse(arg, NULL);
878
879 if (vmalloc_reserve < SZ_16M) {
880 vmalloc_reserve = SZ_16M;
881 printk(KERN_WARNING
882 "vmalloc area too small, limiting to %luMB\n",
883 vmalloc_reserve >> 20);
884 }
885
886 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
887 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
888 printk(KERN_WARNING
889 "vmalloc area is too big, limiting to %luMB\n",
890 vmalloc_reserve >> 20);
891 }
892
893 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
894 return 0;
895}
896early_param("vmalloc", early_vmalloc);
897
898phys_addr_t arm_lowmem_limit __initdata = 0;
899
900void __init sanity_check_meminfo(void)
901{
902 int i, j, highmem = 0;
903
904 for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
905 struct membank *bank = &meminfo.bank[j];
906 *bank = meminfo.bank[i];
907
908 if (bank->start > ULONG_MAX)
909 highmem = 1;
910
911#ifdef CONFIG_HIGHMEM
912 if (__va(bank->start) >= vmalloc_min ||
913 __va(bank->start) < (void *)PAGE_OFFSET)
914 highmem = 1;
915
916 bank->highmem = highmem;
917
918 /*
919 * Split those memory banks which are partially overlapping
920 * the vmalloc area greatly simplifying things later.
921 */
922 if (!highmem && __va(bank->start) < vmalloc_min &&
923 bank->size > vmalloc_min - __va(bank->start)) {
924 if (meminfo.nr_banks >= NR_BANKS) {
925 printk(KERN_CRIT "NR_BANKS too low, "
926 "ignoring high memory\n");
927 } else {
928 memmove(bank + 1, bank,
929 (meminfo.nr_banks - i) * sizeof(*bank));
930 meminfo.nr_banks++;
931 i++;
932 bank[1].size -= vmalloc_min - __va(bank->start);
933 bank[1].start = __pa(vmalloc_min - 1) + 1;
934 bank[1].highmem = highmem = 1;
935 j++;
936 }
937 bank->size = vmalloc_min - __va(bank->start);
938 }
939#else
940 bank->highmem = highmem;
941
942 /*
943 * Highmem banks not allowed with !CONFIG_HIGHMEM.
944 */
945 if (highmem) {
946 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
947 "(!CONFIG_HIGHMEM).\n",
948 (unsigned long long)bank->start,
949 (unsigned long long)bank->start + bank->size - 1);
950 continue;
951 }
952
953 /*
954 * Check whether this memory bank would entirely overlap
955 * the vmalloc area.
956 */
957 if (__va(bank->start) >= vmalloc_min ||
958 __va(bank->start) < (void *)PAGE_OFFSET) {
959 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
960 "(vmalloc region overlap).\n",
961 (unsigned long long)bank->start,
962 (unsigned long long)bank->start + bank->size - 1);
963 continue;
964 }
965
966 /*
967 * Check whether this memory bank would partially overlap
968 * the vmalloc area.
969 */
970 if (__va(bank->start + bank->size) > vmalloc_min ||
971 __va(bank->start + bank->size) < __va(bank->start)) {
972 unsigned long newsize = vmalloc_min - __va(bank->start);
973 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
974 "to -%.8llx (vmalloc region overlap).\n",
975 (unsigned long long)bank->start,
976 (unsigned long long)bank->start + bank->size - 1,
977 (unsigned long long)bank->start + newsize - 1);
978 bank->size = newsize;
979 }
980#endif
981 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
982 arm_lowmem_limit = bank->start + bank->size;
983
984 j++;
985 }
986#ifdef CONFIG_HIGHMEM
987 if (highmem) {
988 const char *reason = NULL;
989
990 if (cache_is_vipt_aliasing()) {
991 /*
992 * Interactions between kmap and other mappings
993 * make highmem support with aliasing VIPT caches
994 * rather difficult.
995 */
996 reason = "with VIPT aliasing cache";
997 }
998 if (reason) {
999 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1000 reason);
1001 while (j > 0 && meminfo.bank[j - 1].highmem)
1002 j--;
1003 }
1004 }
1005#endif
1006 meminfo.nr_banks = j;
1007 high_memory = __va(arm_lowmem_limit - 1) + 1;
1008 memblock_set_current_limit(arm_lowmem_limit);
1009}
1010
1011static inline void prepare_page_table(void)
1012{
1013 unsigned long addr;
1014 phys_addr_t end;
1015
1016 /*
1017 * Clear out all the mappings below the kernel image.
1018 */
1019 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1020 pmd_clear(pmd_off_k(addr));
1021
1022#ifdef CONFIG_XIP_KERNEL
1023 /* The XIP kernel is mapped in the module area -- skip over it */
1024 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1025#endif
1026 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1027 pmd_clear(pmd_off_k(addr));
1028
1029 /*
1030 * Find the end of the first block of lowmem.
1031 */
1032 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1033 if (end >= arm_lowmem_limit)
1034 end = arm_lowmem_limit;
1035
1036 /*
1037 * Clear out all the kernel space mappings, except for the first
1038 * memory bank, up to the vmalloc region.
1039 */
1040 for (addr = __phys_to_virt(end);
1041 addr < VMALLOC_START; addr += PMD_SIZE)
1042 pmd_clear(pmd_off_k(addr));
1043}
1044
1045#ifdef CONFIG_ARM_LPAE
1046/* the first page is reserved for pgd */
1047#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1048 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1049#else
1050#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1051#endif
1052
1053/*
1054 * Reserve the special regions of memory
1055 */
1056void __init arm_mm_memblock_reserve(void)
1057{
1058 /*
1059 * Reserve the page tables. These are already in use,
1060 * and can only be in node 0.
1061 */
1062 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1063
1064#ifdef CONFIG_SA1111
1065 /*
1066 * Because of the SA1111 DMA bug, we want to preserve our
1067 * precious DMA-able memory...
1068 */
1069 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1070#endif
1071}
1072
1073/*
1074 * Set up the device mappings. Since we clear out the page tables for all
1075 * mappings above VMALLOC_START, we will remove any debug device mappings.
1076 * This means you have to be careful how you debug this function, or any
1077 * called function. This means you can't use any function or debugging
1078 * method which may touch any device, otherwise the kernel _will_ crash.
1079 */
1080static void __init devicemaps_init(struct machine_desc *mdesc)
1081{
1082 struct map_desc map;
1083 unsigned long addr;
1084 void *vectors;
1085
1086 /*
1087 * Allocate the vector page early.
1088 */
1089 vectors = early_alloc(PAGE_SIZE);
1090
1091 early_trap_init(vectors);
1092
1093 for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1094 pmd_clear(pmd_off_k(addr));
1095
1096 /*
1097 * Map the kernel if it is XIP.
1098 * It is always first in the modulearea.
1099 */
1100#ifdef CONFIG_XIP_KERNEL
1101 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1102 map.virtual = MODULES_VADDR;
1103 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1104 map.type = MT_ROM;
1105 create_mapping(&map);
1106#endif
1107
1108 /*
1109 * Map the cache flushing regions.
1110 */
1111#ifdef FLUSH_BASE
1112 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1113 map.virtual = FLUSH_BASE;
1114 map.length = SZ_1M;
1115 map.type = MT_CACHECLEAN;
1116 create_mapping(&map);
1117#endif
1118#ifdef FLUSH_BASE_MINICACHE
1119 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1120 map.virtual = FLUSH_BASE_MINICACHE;
1121 map.length = SZ_1M;
1122 map.type = MT_MINICLEAN;
1123 create_mapping(&map);
1124#endif
1125
1126 /*
1127 * Create a mapping for the machine vectors at the high-vectors
1128 * location (0xffff0000). If we aren't using high-vectors, also
1129 * create a mapping at the low-vectors virtual address.
1130 */
1131 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1132 map.virtual = 0xffff0000;
1133 map.length = PAGE_SIZE;
1134 map.type = MT_HIGH_VECTORS;
1135 create_mapping(&map);
1136
1137 if (!vectors_high()) {
1138 map.virtual = 0;
1139 map.type = MT_LOW_VECTORS;
1140 create_mapping(&map);
1141 }
1142
1143 /*
1144 * Ask the machine support to map in the statically mapped devices.
1145 */
1146 if (mdesc->map_io)
1147 mdesc->map_io();
1148 fill_pmd_gaps();
1149
1150 /*
1151 * Finally flush the caches and tlb to ensure that we're in a
1152 * consistent state wrt the writebuffer. This also ensures that
1153 * any write-allocated cache lines in the vector page are written
1154 * back. After this point, we can start to touch devices again.
1155 */
1156 local_flush_tlb_all();
1157 flush_cache_all();
1158}
1159
1160static void __init kmap_init(void)
1161{
1162#ifdef CONFIG_HIGHMEM
1163 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1164 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1165#endif
1166}
1167
1168static void __init map_lowmem(void)
1169{
1170 struct memblock_region *reg;
1171
1172 /* Map all the lowmem memory banks. */
1173 for_each_memblock(memory, reg) {
1174 phys_addr_t start = reg->base;
1175 phys_addr_t end = start + reg->size;
1176 struct map_desc map;
1177
1178 if (end > arm_lowmem_limit)
1179 end = arm_lowmem_limit;
1180 if (start >= end)
1181 break;
1182
1183 map.pfn = __phys_to_pfn(start);
1184 map.virtual = __phys_to_virt(start);
1185 map.length = end - start;
1186 map.type = MT_MEMORY;
1187
1188 create_mapping(&map);
1189 }
1190}
1191
1192/*
1193 * paging_init() sets up the page tables, initialises the zone memory
1194 * maps, and sets up the zero page, bad page and bad page tables.
1195 */
1196void __init paging_init(struct machine_desc *mdesc)
1197{
1198 void *zero_page;
1199
1200 memblock_set_current_limit(arm_lowmem_limit);
1201
1202 build_mem_type_table();
1203 prepare_page_table();
1204 map_lowmem();
1205 dma_contiguous_remap();
1206 devicemaps_init(mdesc);
1207 kmap_init();
1208
1209 top_pmd = pmd_off_k(0xffff0000);
1210
1211 /* allocate the zero page. */
1212 zero_page = early_alloc(PAGE_SIZE);
1213
1214 bootmem_init();
1215
1216 empty_zero_page = virt_to_page(zero_page);
1217 __flush_dcache_page(NULL, empty_zero_page);
1218}