1/*
   2 * Hardware modules present on the OMAP44xx chips
   3 *
   4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5 * Copyright (C) 2009-2010 Nokia Corporation
   6 *
   7 * Paul Walmsley
   8 * Benoit Cousson
   9 *
  10 * This file is automatically generated from the OMAP hardware databases.
  11 * We respectfully ask that any modifications to this file be coordinated
  12 * with the public linux-omap@vger.kernel.org mailing list and the
  13 * authors above to ensure that the autogeneration scripts are kept
  14 * up-to-date with the file contents.
  15 * Note that this file is currently not in sync with autogeneration scripts.
  16 * The above note to be removed, once it is synced up.
  17 *
  18 * This program is free software; you can redistribute it and/or modify
  19 * it under the terms of the GNU General Public License version 2 as
  20 * published by the Free Software Foundation.
  21 */
  22
  23#include <linux/io.h>
  24#include <linux/platform_data/gpio-omap.h>
  25#include <linux/power/smartreflex.h>
  26#include <linux/i2c-omap.h>
  27
  28#include <linux/omap-dma.h>
  29
  30#include <linux/platform_data/spi-omap2-mcspi.h>
  31#include <linux/platform_data/asoc-ti-mcbsp.h>
  32#include <linux/platform_data/iommu-omap.h>
  33#include <plat/dmtimer.h>
 
  34
  35#include "omap_hwmod.h"
  36#include "omap_hwmod_common_data.h"
 
 
  37#include "cm1_44xx.h"
  38#include "cm2_44xx.h"
  39#include "prm44xx.h"
  40#include "prm-regbits-44xx.h"
  41#include "i2c.h"
  42#include "mmc.h"
  43#include "wd_timer.h"
  44
  45/* Base offset for all OMAP4 interrupts external to MPUSS */
  46#define OMAP44XX_IRQ_GIC_START	32
  47
  48/* Base offset for all OMAP4 dma requests */
  49#define OMAP44XX_DMA_REQ_START	1
  50
  51/*
  52 * IP blocks
  53 */
  54
  55/*
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  56 * 'dmm' class
  57 * instance(s): dmm
  58 */
  59static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  60	.name	= "dmm",
  61};
  62
  63/* dmm */
 
 
 
 
 
  64static struct omap_hwmod omap44xx_dmm_hwmod = {
  65	.name		= "dmm",
  66	.class		= &omap44xx_dmm_hwmod_class,
  67	.clkdm_name	= "l3_emif_clkdm",
 
  68	.prcm = {
  69		.omap4 = {
  70			.clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  71			.context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  72		},
  73	},
  74};
  75
  76/*
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  77 * 'l3' class
  78 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  79 */
  80static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  81	.name	= "l3",
  82};
  83
  84/* l3_instr */
  85static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  86	.name		= "l3_instr",
  87	.class		= &omap44xx_l3_hwmod_class,
  88	.clkdm_name	= "l3_instr_clkdm",
  89	.prcm = {
  90		.omap4 = {
  91			.clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  92			.context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  93			.modulemode   = MODULEMODE_HWCTRL,
  94		},
  95	},
  96};
  97
  98/* l3_main_1 */
 
 
 
 
 
 
  99static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 100	.name		= "l3_main_1",
 101	.class		= &omap44xx_l3_hwmod_class,
 102	.clkdm_name	= "l3_1_clkdm",
 
 103	.prcm = {
 104		.omap4 = {
 105			.clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 106			.context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 107		},
 108	},
 109};
 110
 111/* l3_main_2 */
 112static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 113	.name		= "l3_main_2",
 114	.class		= &omap44xx_l3_hwmod_class,
 115	.clkdm_name	= "l3_2_clkdm",
 116	.prcm = {
 117		.omap4 = {
 118			.clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 119			.context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 120		},
 121	},
 122};
 123
 124/* l3_main_3 */
 125static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 126	.name		= "l3_main_3",
 127	.class		= &omap44xx_l3_hwmod_class,
 128	.clkdm_name	= "l3_instr_clkdm",
 129	.prcm = {
 130		.omap4 = {
 131			.clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 132			.context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 133			.modulemode   = MODULEMODE_HWCTRL,
 134		},
 135	},
 136};
 137
 138/*
 139 * 'l4' class
 140 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 141 */
 142static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 143	.name	= "l4",
 144};
 145
 146/* l4_abe */
 147static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 148	.name		= "l4_abe",
 149	.class		= &omap44xx_l4_hwmod_class,
 150	.clkdm_name	= "abe_clkdm",
 151	.prcm = {
 152		.omap4 = {
 153			.clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 154			.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 155			.lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 156			.flags	      = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 157		},
 158	},
 159};
 160
 161/* l4_cfg */
 162static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 163	.name		= "l4_cfg",
 164	.class		= &omap44xx_l4_hwmod_class,
 165	.clkdm_name	= "l4_cfg_clkdm",
 166	.prcm = {
 167		.omap4 = {
 168			.clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 169			.context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 170		},
 171	},
 172};
 173
 174/* l4_per */
 175static struct omap_hwmod omap44xx_l4_per_hwmod = {
 176	.name		= "l4_per",
 177	.class		= &omap44xx_l4_hwmod_class,
 178	.clkdm_name	= "l4_per_clkdm",
 179	.prcm = {
 180		.omap4 = {
 181			.clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 182			.context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 183		},
 184	},
 185};
 186
 187/* l4_wkup */
 188static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 189	.name		= "l4_wkup",
 190	.class		= &omap44xx_l4_hwmod_class,
 191	.clkdm_name	= "l4_wkup_clkdm",
 192	.prcm = {
 193		.omap4 = {
 194			.clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 195			.context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 196		},
 197	},
 198};
 199
 200/*
 201 * 'mpu_bus' class
 202 * instance(s): mpu_private
 203 */
 204static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 205	.name	= "mpu_bus",
 206};
 207
 208/* mpu_private */
 209static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 210	.name		= "mpu_private",
 211	.class		= &omap44xx_mpu_bus_hwmod_class,
 212	.clkdm_name	= "mpuss_clkdm",
 213	.prcm = {
 214		.omap4 = {
 215			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 216		},
 217	},
 218};
 219
 220/*
 221 * 'ocp_wp_noc' class
 222 * instance(s): ocp_wp_noc
 223 */
 224static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 225	.name	= "ocp_wp_noc",
 226};
 227
 228/* ocp_wp_noc */
 229static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 230	.name		= "ocp_wp_noc",
 231	.class		= &omap44xx_ocp_wp_noc_hwmod_class,
 232	.clkdm_name	= "l3_instr_clkdm",
 233	.prcm = {
 234		.omap4 = {
 235			.clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 236			.context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 237			.modulemode   = MODULEMODE_HWCTRL,
 238		},
 239	},
 240};
 241
 242/*
 243 * Modules omap_hwmod structures
 244 *
 245 * The following IPs are excluded for the moment because:
 246 * - They do not need an explicit SW control using omap_hwmod API.
 247 * - They still need to be validated with the driver
 248 *   properly adapted to omap_hwmod / omap_device
 249 *
 250 * usim
 251 */
 252
 253/*
 254 * 'aess' class
 255 * audio engine sub system
 256 */
 257
 258static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 259	.rev_offs	= 0x0000,
 260	.sysc_offs	= 0x0010,
 261	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 262	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 263			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 264			   MSTANDBY_SMART_WKUP),
 265	.sysc_fields	= &omap_hwmod_sysc_type2,
 266};
 267
 268static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 269	.name	= "aess",
 270	.sysc	= &omap44xx_aess_sysc,
 271	.enable_preprogram = omap_hwmod_aess_preprogram,
 272};
 273
 274/* aess */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 275static struct omap_hwmod omap44xx_aess_hwmod = {
 276	.name		= "aess",
 277	.class		= &omap44xx_aess_hwmod_class,
 278	.clkdm_name	= "abe_clkdm",
 279	.main_clk	= "aess_fclk",
 
 
 280	.prcm = {
 281		.omap4 = {
 282			.clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 283			.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 284			.lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 285			.modulemode   = MODULEMODE_SWCTRL,
 286		},
 287	},
 288};
 289
 290/*
 291 * 'c2c' class
 292 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 293 * soc
 294 */
 295
 296static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 297	.name	= "c2c",
 298};
 299
 300/* c2c */
 
 
 
 
 
 
 
 
 
 
 301static struct omap_hwmod omap44xx_c2c_hwmod = {
 302	.name		= "c2c",
 303	.class		= &omap44xx_c2c_hwmod_class,
 304	.clkdm_name	= "d2d_clkdm",
 
 
 305	.prcm = {
 306		.omap4 = {
 307			.clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 308			.context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 309		},
 310	},
 311};
 312
 313/*
 314 * 'counter' class
 315 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 316 */
 317
 318static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 319	.rev_offs	= 0x0000,
 320	.sysc_offs	= 0x0004,
 321	.sysc_flags	= SYSC_HAS_SIDLEMODE,
 322	.idlemodes	= (SIDLE_FORCE | SIDLE_NO),
 323	.sysc_fields	= &omap_hwmod_sysc_type1,
 324};
 325
 326static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 327	.name	= "counter",
 328	.sysc	= &omap44xx_counter_sysc,
 329};
 330
 331/* counter_32k */
 332static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 333	.name		= "counter_32k",
 334	.class		= &omap44xx_counter_hwmod_class,
 335	.clkdm_name	= "l4_wkup_clkdm",
 336	.flags		= HWMOD_SWSUP_SIDLE,
 337	.main_clk	= "sys_32k_ck",
 338	.prcm = {
 339		.omap4 = {
 340			.clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 341			.context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 342		},
 343	},
 344};
 345
 346/*
 347 * 'ctrl_module' class
 348 * attila core control module + core pad control module + wkup pad control
 349 * module + attila wkup control module
 350 */
 351
 352static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 353	.rev_offs	= 0x0000,
 354	.sysc_offs	= 0x0010,
 355	.sysc_flags	= SYSC_HAS_SIDLEMODE,
 356	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 357			   SIDLE_SMART_WKUP),
 358	.sysc_fields	= &omap_hwmod_sysc_type2,
 359};
 360
 361static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 362	.name	= "ctrl_module",
 363	.sysc	= &omap44xx_ctrl_module_sysc,
 364};
 365
 366/* ctrl_module_core */
 
 
 
 
 
 367static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 368	.name		= "ctrl_module_core",
 369	.class		= &omap44xx_ctrl_module_hwmod_class,
 370	.clkdm_name	= "l4_cfg_clkdm",
 371	.prcm = {
 372		.omap4 = {
 373			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 374		},
 375	},
 376};
 377
 378/* ctrl_module_pad_core */
 379static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 380	.name		= "ctrl_module_pad_core",
 381	.class		= &omap44xx_ctrl_module_hwmod_class,
 382	.clkdm_name	= "l4_cfg_clkdm",
 383	.prcm = {
 384		.omap4 = {
 385			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 386		},
 387	},
 388};
 389
 390/* ctrl_module_wkup */
 391static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 392	.name		= "ctrl_module_wkup",
 393	.class		= &omap44xx_ctrl_module_hwmod_class,
 394	.clkdm_name	= "l4_wkup_clkdm",
 395	.prcm = {
 396		.omap4 = {
 397			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 398		},
 399	},
 400};
 401
 402/* ctrl_module_pad_wkup */
 403static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 404	.name		= "ctrl_module_pad_wkup",
 405	.class		= &omap44xx_ctrl_module_hwmod_class,
 406	.clkdm_name	= "l4_wkup_clkdm",
 407	.prcm = {
 408		.omap4 = {
 409			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 410		},
 411	},
 412};
 413
 414/*
 415 * 'debugss' class
 416 * debug and emulation sub system
 417 */
 418
 419static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 420	.name	= "debugss",
 421};
 422
 423/* debugss */
 424static struct omap_hwmod omap44xx_debugss_hwmod = {
 425	.name		= "debugss",
 426	.class		= &omap44xx_debugss_hwmod_class,
 427	.clkdm_name	= "emu_sys_clkdm",
 428	.main_clk	= "trace_clk_div_ck",
 429	.prcm = {
 430		.omap4 = {
 431			.clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 432			.context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 433		},
 434	},
 435};
 436
 437/*
 438 * 'dma' class
 439 * dma controller for data exchange between memory to memory (i.e. internal or
 440 * external memory) and gp peripherals to memory or memory to gp peripherals
 441 */
 442
 443static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 444	.rev_offs	= 0x0000,
 445	.sysc_offs	= 0x002c,
 446	.syss_offs	= 0x0028,
 447	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 448			   SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 449			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 450			   SYSS_HAS_RESET_STATUS),
 451	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 452			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 453	.sysc_fields	= &omap_hwmod_sysc_type1,
 454};
 455
 456static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 457	.name	= "dma",
 458	.sysc	= &omap44xx_dma_sysc,
 459};
 460
 461/* dma dev_attr */
 462static struct omap_dma_dev_attr dma_dev_attr = {
 463	.dev_caps	= RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 464			  IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 465	.lch_count	= 32,
 466};
 467
 468/* dma_system */
 469static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 470	{ .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 471	{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 472	{ .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 473	{ .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 474	{ .irq = -1 }
 475};
 476
 477static struct omap_hwmod omap44xx_dma_system_hwmod = {
 478	.name		= "dma_system",
 479	.class		= &omap44xx_dma_hwmod_class,
 480	.clkdm_name	= "l3_dma_clkdm",
 481	.mpu_irqs	= omap44xx_dma_system_irqs,
 482	.main_clk	= "l3_div_ck",
 483	.prcm = {
 484		.omap4 = {
 485			.clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 486			.context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 487		},
 488	},
 489	.dev_attr	= &dma_dev_attr,
 490};
 491
 492/*
 493 * 'dmic' class
 494 * digital microphone controller
 495 */
 496
 497static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 498	.rev_offs	= 0x0000,
 499	.sysc_offs	= 0x0010,
 500	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 501			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 502	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 503			   SIDLE_SMART_WKUP),
 504	.sysc_fields	= &omap_hwmod_sysc_type2,
 505};
 506
 507static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 508	.name	= "dmic",
 509	.sysc	= &omap44xx_dmic_sysc,
 510};
 511
 512/* dmic */
 
 
 
 
 
 
 
 
 
 
 513static struct omap_hwmod omap44xx_dmic_hwmod = {
 514	.name		= "dmic",
 515	.class		= &omap44xx_dmic_hwmod_class,
 516	.clkdm_name	= "abe_clkdm",
 517	.main_clk	= "func_dmic_abe_gfclk",
 
 
 518	.prcm = {
 519		.omap4 = {
 520			.clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 521			.context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 522			.modulemode   = MODULEMODE_SWCTRL,
 523		},
 524	},
 525};
 526
 527/*
 528 * 'dsp' class
 529 * dsp sub-system
 530 */
 531
 532static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 533	.name	= "dsp",
 534};
 535
 536/* dsp */
 
 
 
 
 
 537static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 538	{ .name = "dsp", .rst_shift = 0 },
 
 539};
 540
 541static struct omap_hwmod omap44xx_dsp_hwmod = {
 542	.name		= "dsp",
 543	.class		= &omap44xx_dsp_hwmod_class,
 544	.clkdm_name	= "tesla_clkdm",
 
 545	.rst_lines	= omap44xx_dsp_resets,
 546	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_dsp_resets),
 547	.main_clk	= "dpll_iva_m4x2_ck",
 548	.prcm = {
 549		.omap4 = {
 550			.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 551			.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 552			.context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 553			.modulemode   = MODULEMODE_HWCTRL,
 554		},
 555	},
 556};
 557
 558/*
 559 * 'dss' class
 560 * display sub-system
 561 */
 562
 563static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 564	.rev_offs	= 0x0000,
 565	.syss_offs	= 0x0014,
 566	.sysc_flags	= SYSS_HAS_RESET_STATUS,
 567};
 568
 569static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 570	.name	= "dss",
 571	.sysc	= &omap44xx_dss_sysc,
 572	.reset	= omap_dss_reset,
 573};
 574
 575/* dss */
 576static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 577	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 578	{ .role = "tv_clk", .clk = "dss_tv_clk" },
 579	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 580};
 581
 582static struct omap_hwmod omap44xx_dss_hwmod = {
 583	.name		= "dss_core",
 584	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 585	.class		= &omap44xx_dss_hwmod_class,
 586	.clkdm_name	= "l3_dss_clkdm",
 587	.main_clk	= "dss_dss_clk",
 588	.prcm = {
 589		.omap4 = {
 590			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 591			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 592		},
 593	},
 594	.opt_clks	= dss_opt_clks,
 595	.opt_clks_cnt	= ARRAY_SIZE(dss_opt_clks),
 596};
 597
 598/*
 599 * 'dispc' class
 600 * display controller
 601 */
 602
 603static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 604	.rev_offs	= 0x0000,
 605	.sysc_offs	= 0x0010,
 606	.syss_offs	= 0x0014,
 607	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 608			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 609			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 610			   SYSS_HAS_RESET_STATUS),
 611	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 612			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 613	.sysc_fields	= &omap_hwmod_sysc_type1,
 614};
 615
 616static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 617	.name	= "dispc",
 618	.sysc	= &omap44xx_dispc_sysc,
 619};
 620
 621/* dss_dispc */
 622static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 623	{ .irq = 25 + OMAP44XX_IRQ_GIC_START },
 624	{ .irq = -1 }
 625};
 626
 627static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 628	{ .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 629	{ .dma_req = -1 }
 630};
 631
 632static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 633	.manager_count		= 3,
 634	.has_framedonetv_irq	= 1
 635};
 636
 637static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 638	.name		= "dss_dispc",
 639	.class		= &omap44xx_dispc_hwmod_class,
 640	.clkdm_name	= "l3_dss_clkdm",
 641	.mpu_irqs	= omap44xx_dss_dispc_irqs,
 642	.sdma_reqs	= omap44xx_dss_dispc_sdma_reqs,
 643	.main_clk	= "dss_dss_clk",
 644	.prcm = {
 645		.omap4 = {
 646			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 647			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 648		},
 649	},
 650	.dev_attr	= &omap44xx_dss_dispc_dev_attr
 651};
 652
 653/*
 654 * 'dsi' class
 655 * display serial interface controller
 656 */
 657
 658static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 659	.rev_offs	= 0x0000,
 660	.sysc_offs	= 0x0010,
 661	.syss_offs	= 0x0014,
 662	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 663			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 664			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 665	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 666	.sysc_fields	= &omap_hwmod_sysc_type1,
 667};
 668
 669static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 670	.name	= "dsi",
 671	.sysc	= &omap44xx_dsi_sysc,
 672};
 673
 674/* dss_dsi1 */
 675static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 676	{ .irq = 53 + OMAP44XX_IRQ_GIC_START },
 677	{ .irq = -1 }
 678};
 679
 680static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 681	{ .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 682	{ .dma_req = -1 }
 683};
 684
 685static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 686	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 687};
 688
 689static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 690	.name		= "dss_dsi1",
 691	.class		= &omap44xx_dsi_hwmod_class,
 692	.clkdm_name	= "l3_dss_clkdm",
 693	.mpu_irqs	= omap44xx_dss_dsi1_irqs,
 694	.sdma_reqs	= omap44xx_dss_dsi1_sdma_reqs,
 695	.main_clk	= "dss_dss_clk",
 696	.prcm = {
 697		.omap4 = {
 698			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 699			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 700		},
 701	},
 702	.opt_clks	= dss_dsi1_opt_clks,
 703	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi1_opt_clks),
 704};
 705
 706/* dss_dsi2 */
 707static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 708	{ .irq = 84 + OMAP44XX_IRQ_GIC_START },
 709	{ .irq = -1 }
 710};
 711
 712static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 713	{ .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 714	{ .dma_req = -1 }
 715};
 716
 717static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 718	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 719};
 720
 721static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 722	.name		= "dss_dsi2",
 723	.class		= &omap44xx_dsi_hwmod_class,
 724	.clkdm_name	= "l3_dss_clkdm",
 725	.mpu_irqs	= omap44xx_dss_dsi2_irqs,
 726	.sdma_reqs	= omap44xx_dss_dsi2_sdma_reqs,
 727	.main_clk	= "dss_dss_clk",
 728	.prcm = {
 729		.omap4 = {
 730			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 731			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 732		},
 733	},
 734	.opt_clks	= dss_dsi2_opt_clks,
 735	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi2_opt_clks),
 736};
 737
 738/*
 739 * 'hdmi' class
 740 * hdmi controller
 741 */
 742
 743static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 744	.rev_offs	= 0x0000,
 745	.sysc_offs	= 0x0010,
 746	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 747			   SYSC_HAS_SOFTRESET),
 748	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 749			   SIDLE_SMART_WKUP),
 750	.sysc_fields	= &omap_hwmod_sysc_type2,
 751};
 752
 753static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 754	.name	= "hdmi",
 755	.sysc	= &omap44xx_hdmi_sysc,
 756};
 757
 758/* dss_hdmi */
 759static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 760	{ .irq = 101 + OMAP44XX_IRQ_GIC_START },
 761	{ .irq = -1 }
 762};
 763
 764static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 765	{ .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 766	{ .dma_req = -1 }
 767};
 768
 769static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 770	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 771};
 772
 773static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 774	.name		= "dss_hdmi",
 775	.class		= &omap44xx_hdmi_hwmod_class,
 776	.clkdm_name	= "l3_dss_clkdm",
 777	/*
 778	 * HDMI audio requires to use no-idle mode. Hence,
 779	 * set idle mode by software.
 780	 */
 781	.flags		= HWMOD_SWSUP_SIDLE,
 782	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
 783	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
 784	.main_clk	= "dss_48mhz_clk",
 785	.prcm = {
 786		.omap4 = {
 787			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 788			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 789		},
 790	},
 791	.opt_clks	= dss_hdmi_opt_clks,
 792	.opt_clks_cnt	= ARRAY_SIZE(dss_hdmi_opt_clks),
 793};
 794
 795/*
 796 * 'rfbi' class
 797 * remote frame buffer interface
 798 */
 799
 800static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 801	.rev_offs	= 0x0000,
 802	.sysc_offs	= 0x0010,
 803	.syss_offs	= 0x0014,
 804	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 805			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 806	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 807	.sysc_fields	= &omap_hwmod_sysc_type1,
 808};
 809
 810static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 811	.name	= "rfbi",
 812	.sysc	= &omap44xx_rfbi_sysc,
 813};
 814
 815/* dss_rfbi */
 816static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 817	{ .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 818	{ .dma_req = -1 }
 819};
 820
 821static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 822	{ .role = "ick", .clk = "dss_fck" },
 823};
 824
 825static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 826	.name		= "dss_rfbi",
 827	.class		= &omap44xx_rfbi_hwmod_class,
 828	.clkdm_name	= "l3_dss_clkdm",
 829	.sdma_reqs	= omap44xx_dss_rfbi_sdma_reqs,
 830	.main_clk	= "dss_dss_clk",
 831	.prcm = {
 832		.omap4 = {
 833			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 834			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 835		},
 836	},
 837	.opt_clks	= dss_rfbi_opt_clks,
 838	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
 839};
 840
 841/*
 842 * 'venc' class
 843 * video encoder
 844 */
 845
 846static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 847	.name	= "venc",
 848};
 849
 850/* dss_venc */
 851static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 852	.name		= "dss_venc",
 853	.class		= &omap44xx_venc_hwmod_class,
 854	.clkdm_name	= "l3_dss_clkdm",
 855	.main_clk	= "dss_tv_clk",
 856	.prcm = {
 857		.omap4 = {
 858			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 859			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 860		},
 861	},
 862};
 863
 864/*
 865 * 'elm' class
 866 * bch error location module
 867 */
 868
 869static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 870	.rev_offs	= 0x0000,
 871	.sysc_offs	= 0x0010,
 872	.syss_offs	= 0x0014,
 873	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 874			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 875			   SYSS_HAS_RESET_STATUS),
 876	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 877	.sysc_fields	= &omap_hwmod_sysc_type1,
 878};
 879
 880static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 881	.name	= "elm",
 882	.sysc	= &omap44xx_elm_sysc,
 883};
 884
 885/* elm */
 
 
 
 
 
 886static struct omap_hwmod omap44xx_elm_hwmod = {
 887	.name		= "elm",
 888	.class		= &omap44xx_elm_hwmod_class,
 889	.clkdm_name	= "l4_per_clkdm",
 
 890	.prcm = {
 891		.omap4 = {
 892			.clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 893			.context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 894		},
 895	},
 896};
 897
 898/*
 899 * 'emif' class
 900 * external memory interface no1
 901 */
 902
 903static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 904	.rev_offs	= 0x0000,
 905};
 906
 907static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 908	.name	= "emif",
 909	.sysc	= &omap44xx_emif_sysc,
 910};
 911
 912/* emif1 */
 
 
 
 
 
 913static struct omap_hwmod omap44xx_emif1_hwmod = {
 914	.name		= "emif1",
 915	.class		= &omap44xx_emif_hwmod_class,
 916	.clkdm_name	= "l3_emif_clkdm",
 917	.flags		= HWMOD_INIT_NO_IDLE,
 
 918	.main_clk	= "ddrphy_ck",
 919	.prcm = {
 920		.omap4 = {
 921			.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 922			.context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 923			.modulemode   = MODULEMODE_HWCTRL,
 924		},
 925	},
 926};
 927
 928/* emif2 */
 
 
 
 
 
 929static struct omap_hwmod omap44xx_emif2_hwmod = {
 930	.name		= "emif2",
 931	.class		= &omap44xx_emif_hwmod_class,
 932	.clkdm_name	= "l3_emif_clkdm",
 933	.flags		= HWMOD_INIT_NO_IDLE,
 
 934	.main_clk	= "ddrphy_ck",
 935	.prcm = {
 936		.omap4 = {
 937			.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 938			.context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 939			.modulemode   = MODULEMODE_HWCTRL,
 940		},
 941	},
 942};
 943
 944/*
 945 * 'fdif' class
 946 * face detection hw accelerator module
 947 */
 948
 949static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
 950	.rev_offs	= 0x0000,
 951	.sysc_offs	= 0x0010,
 952	/*
 953	 * FDIF needs 100 OCP clk cycles delay after a softreset before
 954	 * accessing sysconfig again.
 955	 * The lowest frequency at the moment for L3 bus is 100 MHz, so
 956	 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
 957	 *
 958	 * TODO: Indicate errata when available.
 959	 */
 960	.srst_udelay	= 2,
 961	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
 962			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 963	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 964			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 965	.sysc_fields	= &omap_hwmod_sysc_type2,
 966};
 967
 968static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
 969	.name	= "fdif",
 970	.sysc	= &omap44xx_fdif_sysc,
 971};
 972
 973/* fdif */
 
 
 
 
 
 974static struct omap_hwmod omap44xx_fdif_hwmod = {
 975	.name		= "fdif",
 976	.class		= &omap44xx_fdif_hwmod_class,
 977	.clkdm_name	= "iss_clkdm",
 
 978	.main_clk	= "fdif_fck",
 979	.prcm = {
 980		.omap4 = {
 981			.clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
 982			.context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
 983			.modulemode   = MODULEMODE_SWCTRL,
 984		},
 985	},
 986};
 987
 988/*
 989 * 'gpio' class
 990 * general purpose io module
 991 */
 992
 993static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
 994	.rev_offs	= 0x0000,
 995	.sysc_offs	= 0x0010,
 996	.syss_offs	= 0x0114,
 997	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 998			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 999			   SYSS_HAS_RESET_STATUS),
1000	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1001			   SIDLE_SMART_WKUP),
1002	.sysc_fields	= &omap_hwmod_sysc_type1,
1003};
1004
1005static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1006	.name	= "gpio",
1007	.sysc	= &omap44xx_gpio_sysc,
1008	.rev	= 2,
1009};
1010
1011/* gpio dev_attr */
1012static struct omap_gpio_dev_attr gpio_dev_attr = {
1013	.bank_width	= 32,
1014	.dbck_flag	= true,
1015};
1016
1017/* gpio1 */
 
 
 
 
 
1018static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1019	{ .role = "dbclk", .clk = "gpio1_dbclk" },
1020};
1021
1022static struct omap_hwmod omap44xx_gpio1_hwmod = {
1023	.name		= "gpio1",
1024	.class		= &omap44xx_gpio_hwmod_class,
1025	.clkdm_name	= "l4_wkup_clkdm",
1026	.main_clk	= "l4_wkup_clk_mux_ck",
 
1027	.prcm = {
1028		.omap4 = {
1029			.clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1030			.context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1031			.modulemode   = MODULEMODE_HWCTRL,
1032		},
1033	},
1034	.opt_clks	= gpio1_opt_clks,
1035	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
1036	.dev_attr	= &gpio_dev_attr,
1037};
1038
1039/* gpio2 */
 
 
 
 
 
1040static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1041	{ .role = "dbclk", .clk = "gpio2_dbclk" },
1042};
1043
1044static struct omap_hwmod omap44xx_gpio2_hwmod = {
1045	.name		= "gpio2",
1046	.class		= &omap44xx_gpio_hwmod_class,
1047	.clkdm_name	= "l4_per_clkdm",
1048	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1049	.main_clk	= "l4_div_ck",
 
1050	.prcm = {
1051		.omap4 = {
1052			.clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1053			.context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1054			.modulemode   = MODULEMODE_HWCTRL,
1055		},
1056	},
1057	.opt_clks	= gpio2_opt_clks,
1058	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
1059	.dev_attr	= &gpio_dev_attr,
1060};
1061
1062/* gpio3 */
 
 
 
 
 
1063static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1064	{ .role = "dbclk", .clk = "gpio3_dbclk" },
1065};
1066
1067static struct omap_hwmod omap44xx_gpio3_hwmod = {
1068	.name		= "gpio3",
1069	.class		= &omap44xx_gpio_hwmod_class,
1070	.clkdm_name	= "l4_per_clkdm",
1071	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1072	.main_clk	= "l4_div_ck",
 
1073	.prcm = {
1074		.omap4 = {
1075			.clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1076			.context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1077			.modulemode   = MODULEMODE_HWCTRL,
1078		},
1079	},
1080	.opt_clks	= gpio3_opt_clks,
1081	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
1082	.dev_attr	= &gpio_dev_attr,
1083};
1084
1085/* gpio4 */
 
 
 
 
 
1086static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1087	{ .role = "dbclk", .clk = "gpio4_dbclk" },
1088};
1089
1090static struct omap_hwmod omap44xx_gpio4_hwmod = {
1091	.name		= "gpio4",
1092	.class		= &omap44xx_gpio_hwmod_class,
1093	.clkdm_name	= "l4_per_clkdm",
1094	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1095	.main_clk	= "l4_div_ck",
 
1096	.prcm = {
1097		.omap4 = {
1098			.clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1099			.context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1100			.modulemode   = MODULEMODE_HWCTRL,
1101		},
1102	},
1103	.opt_clks	= gpio4_opt_clks,
1104	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
1105	.dev_attr	= &gpio_dev_attr,
1106};
1107
1108/* gpio5 */
 
 
 
 
 
1109static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1110	{ .role = "dbclk", .clk = "gpio5_dbclk" },
1111};
1112
1113static struct omap_hwmod omap44xx_gpio5_hwmod = {
1114	.name		= "gpio5",
1115	.class		= &omap44xx_gpio_hwmod_class,
1116	.clkdm_name	= "l4_per_clkdm",
1117	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1118	.main_clk	= "l4_div_ck",
 
1119	.prcm = {
1120		.omap4 = {
1121			.clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1122			.context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1123			.modulemode   = MODULEMODE_HWCTRL,
1124		},
1125	},
1126	.opt_clks	= gpio5_opt_clks,
1127	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
1128	.dev_attr	= &gpio_dev_attr,
1129};
1130
1131/* gpio6 */
 
 
 
 
 
1132static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1133	{ .role = "dbclk", .clk = "gpio6_dbclk" },
1134};
1135
1136static struct omap_hwmod omap44xx_gpio6_hwmod = {
1137	.name		= "gpio6",
1138	.class		= &omap44xx_gpio_hwmod_class,
1139	.clkdm_name	= "l4_per_clkdm",
1140	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1141	.main_clk	= "l4_div_ck",
 
1142	.prcm = {
1143		.omap4 = {
1144			.clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1145			.context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1146			.modulemode   = MODULEMODE_HWCTRL,
1147		},
1148	},
1149	.opt_clks	= gpio6_opt_clks,
1150	.opt_clks_cnt	= ARRAY_SIZE(gpio6_opt_clks),
1151	.dev_attr	= &gpio_dev_attr,
1152};
1153
1154/*
1155 * 'gpmc' class
1156 * general purpose memory controller
1157 */
1158
1159static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1160	.rev_offs	= 0x0000,
1161	.sysc_offs	= 0x0010,
1162	.syss_offs	= 0x0014,
1163	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1164			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1165	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1166	.sysc_fields	= &omap_hwmod_sysc_type1,
1167};
1168
1169static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1170	.name	= "gpmc",
1171	.sysc	= &omap44xx_gpmc_sysc,
1172};
1173
1174/* gpmc */
 
 
 
 
 
 
 
 
 
 
1175static struct omap_hwmod omap44xx_gpmc_hwmod = {
1176	.name		= "gpmc",
1177	.class		= &omap44xx_gpmc_hwmod_class,
1178	.clkdm_name	= "l3_2_clkdm",
1179	/*
1180	 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1181	 * block.  It is not being added due to any known bugs with
1182	 * resetting the GPMC IP block, but rather because any timings
1183	 * set by the bootloader are not being correctly programmed by
1184	 * the kernel from the board file or DT data.
1185	 * HWMOD_INIT_NO_RESET should be removed ASAP.
1186	 */
1187	.flags		= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 
 
1188	.prcm = {
1189		.omap4 = {
1190			.clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1191			.context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1192			.modulemode   = MODULEMODE_HWCTRL,
1193		},
1194	},
1195};
1196
1197/*
1198 * 'gpu' class
1199 * 2d/3d graphics accelerator
1200 */
1201
1202static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1203	.rev_offs	= 0x1fc00,
1204	.sysc_offs	= 0x1fc10,
1205	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1206	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1207			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1208			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1209	.sysc_fields	= &omap_hwmod_sysc_type2,
1210};
1211
1212static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1213	.name	= "gpu",
1214	.sysc	= &omap44xx_gpu_sysc,
1215};
1216
1217/* gpu */
 
 
 
 
 
1218static struct omap_hwmod omap44xx_gpu_hwmod = {
1219	.name		= "gpu",
1220	.class		= &omap44xx_gpu_hwmod_class,
1221	.clkdm_name	= "l3_gfx_clkdm",
1222	.main_clk	= "sgx_clk_mux",
 
1223	.prcm = {
1224		.omap4 = {
1225			.clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1226			.context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1227			.modulemode   = MODULEMODE_SWCTRL,
1228		},
1229	},
1230};
1231
1232/*
1233 * 'hdq1w' class
1234 * hdq / 1-wire serial interface controller
1235 */
1236
1237static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1238	.rev_offs	= 0x0000,
1239	.sysc_offs	= 0x0014,
1240	.syss_offs	= 0x0018,
1241	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1242			   SYSS_HAS_RESET_STATUS),
1243	.sysc_fields	= &omap_hwmod_sysc_type1,
1244};
1245
1246static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1247	.name	= "hdq1w",
1248	.sysc	= &omap44xx_hdq1w_sysc,
1249};
1250
1251/* hdq1w */
 
 
 
 
 
1252static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1253	.name		= "hdq1w",
1254	.class		= &omap44xx_hdq1w_hwmod_class,
1255	.clkdm_name	= "l4_per_clkdm",
1256	.flags		= HWMOD_INIT_NO_RESET, /* XXX temporary */
1257	.main_clk	= "func_12m_fclk",
 
1258	.prcm = {
1259		.omap4 = {
1260			.clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1261			.context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1262			.modulemode   = MODULEMODE_SWCTRL,
1263		},
1264	},
1265};
1266
1267/*
1268 * 'hsi' class
1269 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1270 * serial if)
1271 */
1272
1273static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1274	.rev_offs	= 0x0000,
1275	.sysc_offs	= 0x0010,
1276	.syss_offs	= 0x0014,
1277	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1278			   SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1279			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1280	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1281			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1282			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1283	.sysc_fields	= &omap_hwmod_sysc_type1,
1284};
1285
1286static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1287	.name	= "hsi",
1288	.sysc	= &omap44xx_hsi_sysc,
1289};
1290
1291/* hsi */
 
 
 
 
 
 
 
1292static struct omap_hwmod omap44xx_hsi_hwmod = {
1293	.name		= "hsi",
1294	.class		= &omap44xx_hsi_hwmod_class,
1295	.clkdm_name	= "l3_init_clkdm",
 
1296	.main_clk	= "hsi_fck",
1297	.prcm = {
1298		.omap4 = {
1299			.clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1300			.context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1301			.modulemode   = MODULEMODE_HWCTRL,
1302		},
1303	},
1304};
1305
1306/*
1307 * 'i2c' class
1308 * multimaster high-speed i2c controller
1309 */
1310
1311static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1312	.sysc_offs	= 0x0010,
1313	.syss_offs	= 0x0090,
1314	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1315			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1316			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1317	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1318			   SIDLE_SMART_WKUP),
1319	.clockact	= CLOCKACT_TEST_ICLK,
1320	.sysc_fields	= &omap_hwmod_sysc_type1,
1321};
1322
1323static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1324	.name	= "i2c",
1325	.sysc	= &omap44xx_i2c_sysc,
1326	.rev	= OMAP_I2C_IP_VERSION_2,
1327	.reset	= &omap_i2c_reset,
1328};
1329
1330static struct omap_i2c_dev_attr i2c_dev_attr = {
1331	.flags	= OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 
1332};
1333
1334/* i2c1 */
 
 
 
 
 
 
 
 
 
 
 
1335static struct omap_hwmod omap44xx_i2c1_hwmod = {
1336	.name		= "i2c1",
1337	.class		= &omap44xx_i2c_hwmod_class,
1338	.clkdm_name	= "l4_per_clkdm",
1339	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1340	.main_clk	= "func_96m_fclk",
 
 
1341	.prcm = {
1342		.omap4 = {
1343			.clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1344			.context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1345			.modulemode   = MODULEMODE_SWCTRL,
1346		},
1347	},
1348	.dev_attr	= &i2c_dev_attr,
1349};
1350
1351/* i2c2 */
 
 
 
 
 
 
 
 
 
 
 
1352static struct omap_hwmod omap44xx_i2c2_hwmod = {
1353	.name		= "i2c2",
1354	.class		= &omap44xx_i2c_hwmod_class,
1355	.clkdm_name	= "l4_per_clkdm",
1356	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1357	.main_clk	= "func_96m_fclk",
 
 
1358	.prcm = {
1359		.omap4 = {
1360			.clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1361			.context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1362			.modulemode   = MODULEMODE_SWCTRL,
1363		},
1364	},
1365	.dev_attr	= &i2c_dev_attr,
1366};
1367
1368/* i2c3 */
 
 
 
 
 
 
 
 
 
 
 
1369static struct omap_hwmod omap44xx_i2c3_hwmod = {
1370	.name		= "i2c3",
1371	.class		= &omap44xx_i2c_hwmod_class,
1372	.clkdm_name	= "l4_per_clkdm",
1373	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1374	.main_clk	= "func_96m_fclk",
 
 
1375	.prcm = {
1376		.omap4 = {
1377			.clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1378			.context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1379			.modulemode   = MODULEMODE_SWCTRL,
1380		},
1381	},
1382	.dev_attr	= &i2c_dev_attr,
1383};
1384
1385/* i2c4 */
 
 
 
 
 
 
 
 
 
 
 
1386static struct omap_hwmod omap44xx_i2c4_hwmod = {
1387	.name		= "i2c4",
1388	.class		= &omap44xx_i2c_hwmod_class,
1389	.clkdm_name	= "l4_per_clkdm",
1390	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1391	.main_clk	= "func_96m_fclk",
 
 
1392	.prcm = {
1393		.omap4 = {
1394			.clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1395			.context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1396			.modulemode   = MODULEMODE_SWCTRL,
1397		},
1398	},
1399	.dev_attr	= &i2c_dev_attr,
1400};
1401
1402/*
1403 * 'ipu' class
1404 * imaging processor unit
1405 */
1406
1407static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1408	.name	= "ipu",
1409};
1410
1411/* ipu */
 
 
 
 
 
1412static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1413	{ .name = "cpu0", .rst_shift = 0 },
1414	{ .name = "cpu1", .rst_shift = 1 },
 
1415};
1416
1417static struct omap_hwmod omap44xx_ipu_hwmod = {
1418	.name		= "ipu",
1419	.class		= &omap44xx_ipu_hwmod_class,
1420	.clkdm_name	= "ducati_clkdm",
 
1421	.rst_lines	= omap44xx_ipu_resets,
1422	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_resets),
1423	.main_clk	= "ducati_clk_mux_ck",
1424	.prcm = {
1425		.omap4 = {
1426			.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1427			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1428			.context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1429			.modulemode   = MODULEMODE_HWCTRL,
1430		},
1431	},
1432};
1433
1434/*
1435 * 'iss' class
1436 * external images sensor pixel data processor
1437 */
1438
1439static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1440	.rev_offs	= 0x0000,
1441	.sysc_offs	= 0x0010,
1442	/*
1443	 * ISS needs 100 OCP clk cycles delay after a softreset before
1444	 * accessing sysconfig again.
1445	 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1446	 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1447	 *
1448	 * TODO: Indicate errata when available.
1449	 */
1450	.srst_udelay	= 2,
1451	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1452			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1453	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1454			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1455			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1456	.sysc_fields	= &omap_hwmod_sysc_type2,
1457};
1458
1459static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1460	.name	= "iss",
1461	.sysc	= &omap44xx_iss_sysc,
1462};
1463
1464/* iss */
 
 
 
 
 
 
 
 
 
 
 
 
 
1465static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1466	{ .role = "ctrlclk", .clk = "iss_ctrlclk" },
1467};
1468
1469static struct omap_hwmod omap44xx_iss_hwmod = {
1470	.name		= "iss",
1471	.class		= &omap44xx_iss_hwmod_class,
1472	.clkdm_name	= "iss_clkdm",
1473	.main_clk	= "ducati_clk_mux_ck",
 
 
1474	.prcm = {
1475		.omap4 = {
1476			.clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1477			.context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1478			.modulemode   = MODULEMODE_SWCTRL,
1479		},
1480	},
1481	.opt_clks	= iss_opt_clks,
1482	.opt_clks_cnt	= ARRAY_SIZE(iss_opt_clks),
1483};
1484
1485/*
1486 * 'iva' class
1487 * multi-standard video encoder/decoder hardware accelerator
1488 */
1489
1490static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1491	.name	= "iva",
1492};
1493
1494/* iva */
 
 
 
 
 
 
 
1495static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1496	{ .name = "seq0", .rst_shift = 0 },
1497	{ .name = "seq1", .rst_shift = 1 },
1498	{ .name = "logic", .rst_shift = 2 },
1499};
1500
1501static struct omap_hwmod omap44xx_iva_hwmod = {
1502	.name		= "iva",
1503	.class		= &omap44xx_iva_hwmod_class,
1504	.clkdm_name	= "ivahd_clkdm",
 
1505	.rst_lines	= omap44xx_iva_resets,
1506	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_resets),
1507	.main_clk	= "dpll_iva_m5x2_ck",
1508	.prcm = {
1509		.omap4 = {
1510			.clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1511			.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1512			.context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1513			.modulemode   = MODULEMODE_HWCTRL,
1514		},
1515	},
1516};
1517
1518/*
1519 * 'kbd' class
1520 * keyboard controller
1521 */
1522
1523static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1524	.rev_offs	= 0x0000,
1525	.sysc_offs	= 0x0010,
1526	.syss_offs	= 0x0014,
1527	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1528			   SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1529			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1530			   SYSS_HAS_RESET_STATUS),
1531	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1532	.sysc_fields	= &omap_hwmod_sysc_type1,
1533};
1534
1535static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1536	.name	= "kbd",
1537	.sysc	= &omap44xx_kbd_sysc,
1538};
1539
1540/* kbd */
 
 
 
 
 
1541static struct omap_hwmod omap44xx_kbd_hwmod = {
1542	.name		= "kbd",
1543	.class		= &omap44xx_kbd_hwmod_class,
1544	.clkdm_name	= "l4_wkup_clkdm",
1545	.main_clk	= "sys_32k_ck",
 
1546	.prcm = {
1547		.omap4 = {
1548			.clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1549			.context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1550			.modulemode   = MODULEMODE_SWCTRL,
1551		},
1552	},
1553};
1554
1555/*
1556 * 'mailbox' class
1557 * mailbox module allowing communication between the on-chip processors using a
1558 * queued mailbox-interrupt mechanism.
1559 */
1560
1561static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1562	.rev_offs	= 0x0000,
1563	.sysc_offs	= 0x0010,
1564	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1565			   SYSC_HAS_SOFTRESET),
1566	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1567	.sysc_fields	= &omap_hwmod_sysc_type2,
1568};
1569
1570static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1571	.name	= "mailbox",
1572	.sysc	= &omap44xx_mailbox_sysc,
1573};
1574
1575/* mailbox */
 
 
 
 
 
1576static struct omap_hwmod omap44xx_mailbox_hwmod = {
1577	.name		= "mailbox",
1578	.class		= &omap44xx_mailbox_hwmod_class,
1579	.clkdm_name	= "l4_cfg_clkdm",
 
1580	.prcm = {
1581		.omap4 = {
1582			.clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1583			.context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1584		},
1585	},
1586};
1587
1588/*
1589 * 'mcasp' class
1590 * multi-channel audio serial port controller
1591 */
1592
1593/* The IP is not compliant to type1 / type2 scheme */
1594static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1595	.sidle_shift	= 0,
1596};
1597
1598static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1599	.sysc_offs	= 0x0004,
1600	.sysc_flags	= SYSC_HAS_SIDLEMODE,
1601	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1602			   SIDLE_SMART_WKUP),
1603	.sysc_fields	= &omap_hwmod_sysc_type_mcasp,
1604};
1605
1606static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1607	.name	= "mcasp",
1608	.sysc	= &omap44xx_mcasp_sysc,
1609};
1610
1611/* mcasp */
 
 
 
 
 
 
 
 
 
 
 
 
1612static struct omap_hwmod omap44xx_mcasp_hwmod = {
1613	.name		= "mcasp",
1614	.class		= &omap44xx_mcasp_hwmod_class,
1615	.clkdm_name	= "abe_clkdm",
1616	.main_clk	= "func_mcasp_abe_gfclk",
 
 
1617	.prcm = {
1618		.omap4 = {
1619			.clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1620			.context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1621			.modulemode   = MODULEMODE_SWCTRL,
1622		},
1623	},
1624};
1625
1626/*
1627 * 'mcbsp' class
1628 * multi channel buffered serial port controller
1629 */
1630
1631static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1632	.sysc_offs	= 0x008c,
1633	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1634			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1635	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1636	.sysc_fields	= &omap_hwmod_sysc_type1,
1637};
1638
1639static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1640	.name	= "mcbsp",
1641	.sysc	= &omap44xx_mcbsp_sysc,
1642	.rev	= MCBSP_CONFIG_TYPE4,
1643};
1644
1645/* mcbsp1 */
 
 
 
 
 
 
 
 
 
 
 
1646static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1647	{ .role = "pad_fck", .clk = "pad_clks_ck" },
1648	{ .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1649};
1650
1651static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1652	.name		= "mcbsp1",
1653	.class		= &omap44xx_mcbsp_hwmod_class,
1654	.clkdm_name	= "abe_clkdm",
1655	.main_clk	= "func_mcbsp1_gfclk",
 
 
1656	.prcm = {
1657		.omap4 = {
1658			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1659			.context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1660			.modulemode   = MODULEMODE_SWCTRL,
1661		},
1662	},
1663	.opt_clks	= mcbsp1_opt_clks,
1664	.opt_clks_cnt	= ARRAY_SIZE(mcbsp1_opt_clks),
1665};
1666
1667/* mcbsp2 */
 
 
 
 
 
 
 
 
 
 
 
1668static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1669	{ .role = "pad_fck", .clk = "pad_clks_ck" },
1670	{ .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1671};
1672
1673static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1674	.name		= "mcbsp2",
1675	.class		= &omap44xx_mcbsp_hwmod_class,
1676	.clkdm_name	= "abe_clkdm",
1677	.main_clk	= "func_mcbsp2_gfclk",
 
 
1678	.prcm = {
1679		.omap4 = {
1680			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1681			.context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1682			.modulemode   = MODULEMODE_SWCTRL,
1683		},
1684	},
1685	.opt_clks	= mcbsp2_opt_clks,
1686	.opt_clks_cnt	= ARRAY_SIZE(mcbsp2_opt_clks),
1687};
1688
1689/* mcbsp3 */
 
 
 
 
 
 
 
 
 
 
 
1690static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1691	{ .role = "pad_fck", .clk = "pad_clks_ck" },
1692	{ .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1693};
1694
1695static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1696	.name		= "mcbsp3",
1697	.class		= &omap44xx_mcbsp_hwmod_class,
1698	.clkdm_name	= "abe_clkdm",
1699	.main_clk	= "func_mcbsp3_gfclk",
 
 
1700	.prcm = {
1701		.omap4 = {
1702			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1703			.context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1704			.modulemode   = MODULEMODE_SWCTRL,
1705		},
1706	},
1707	.opt_clks	= mcbsp3_opt_clks,
1708	.opt_clks_cnt	= ARRAY_SIZE(mcbsp3_opt_clks),
1709};
1710
1711/* mcbsp4 */
 
 
 
 
 
 
 
 
 
 
 
1712static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1713	{ .role = "pad_fck", .clk = "pad_clks_ck" },
1714	{ .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1715};
1716
1717static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1718	.name		= "mcbsp4",
1719	.class		= &omap44xx_mcbsp_hwmod_class,
1720	.clkdm_name	= "l4_per_clkdm",
1721	.main_clk	= "per_mcbsp4_gfclk",
 
 
1722	.prcm = {
1723		.omap4 = {
1724			.clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1725			.context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1726			.modulemode   = MODULEMODE_SWCTRL,
1727		},
1728	},
1729	.opt_clks	= mcbsp4_opt_clks,
1730	.opt_clks_cnt	= ARRAY_SIZE(mcbsp4_opt_clks),
1731};
1732
1733/*
1734 * 'mcpdm' class
1735 * multi channel pdm controller (proprietary interface with phoenix power
1736 * ic)
1737 */
1738
1739static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1740	.rev_offs	= 0x0000,
1741	.sysc_offs	= 0x0010,
1742	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1743			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1744	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1745			   SIDLE_SMART_WKUP),
1746	.sysc_fields	= &omap_hwmod_sysc_type2,
1747};
1748
1749static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1750	.name	= "mcpdm",
1751	.sysc	= &omap44xx_mcpdm_sysc,
1752};
1753
1754/* mcpdm */
 
 
 
 
 
 
 
 
 
 
 
1755static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1756	.name		= "mcpdm",
1757	.class		= &omap44xx_mcpdm_hwmod_class,
1758	.clkdm_name	= "abe_clkdm",
1759	/*
1760	 * It's suspected that the McPDM requires an off-chip main
1761	 * functional clock, controlled via I2C.  This IP block is
1762	 * currently reset very early during boot, before I2C is
1763	 * available, so it doesn't seem that we have any choice in
1764	 * the kernel other than to avoid resetting it.
1765	 *
1766	 * Also, McPDM needs to be configured to NO_IDLE mode when it
1767	 * is in used otherwise vital clocks will be gated which
1768	 * results 'slow motion' audio playback.
1769	 */
1770	.flags		= HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1771	.main_clk	= "pad_clks_ck",
1772	.prcm = {
1773		.omap4 = {
1774			.clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1775			.context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1776			.modulemode   = MODULEMODE_SWCTRL,
1777		},
1778	},
1779};
1780
1781/*
1782 * 'mcspi' class
1783 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1784 * bus
1785 */
1786
1787static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1788	.rev_offs	= 0x0000,
1789	.sysc_offs	= 0x0010,
1790	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1791			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1792	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1793			   SIDLE_SMART_WKUP),
1794	.sysc_fields	= &omap_hwmod_sysc_type2,
1795};
1796
1797static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1798	.name	= "mcspi",
1799	.sysc	= &omap44xx_mcspi_sysc,
1800	.rev	= OMAP4_MCSPI_REV,
1801};
1802
1803/* mcspi1 */
 
 
 
 
 
1804static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
1805	{ .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
1806	{ .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
1807	{ .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
1808	{ .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
1809	{ .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
1810	{ .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
1811	{ .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
1812	{ .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
1813	{ .dma_req = -1 }
1814};
1815
1816/* mcspi1 dev_attr */
1817static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1818	.num_chipselect	= 4,
1819};
1820
1821static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1822	.name		= "mcspi1",
1823	.class		= &omap44xx_mcspi_hwmod_class,
1824	.clkdm_name	= "l4_per_clkdm",
 
1825	.sdma_reqs	= omap44xx_mcspi1_sdma_reqs,
1826	.main_clk	= "func_48m_fclk",
1827	.prcm = {
1828		.omap4 = {
1829			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1830			.context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1831			.modulemode   = MODULEMODE_SWCTRL,
1832		},
1833	},
1834	.dev_attr	= &mcspi1_dev_attr,
1835};
1836
1837/* mcspi2 */
 
 
 
 
 
1838static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
1839	{ .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
1840	{ .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
1841	{ .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
1842	{ .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
1843	{ .dma_req = -1 }
1844};
1845
1846/* mcspi2 dev_attr */
1847static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1848	.num_chipselect	= 2,
1849};
1850
1851static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1852	.name		= "mcspi2",
1853	.class		= &omap44xx_mcspi_hwmod_class,
1854	.clkdm_name	= "l4_per_clkdm",
 
1855	.sdma_reqs	= omap44xx_mcspi2_sdma_reqs,
1856	.main_clk	= "func_48m_fclk",
1857	.prcm = {
1858		.omap4 = {
1859			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1860			.context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1861			.modulemode   = MODULEMODE_SWCTRL,
1862		},
1863	},
1864	.dev_attr	= &mcspi2_dev_attr,
1865};
1866
1867/* mcspi3 */
 
 
 
 
 
1868static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
1869	{ .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
1870	{ .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
1871	{ .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
1872	{ .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
1873	{ .dma_req = -1 }
1874};
1875
1876/* mcspi3 dev_attr */
1877static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1878	.num_chipselect	= 2,
1879};
1880
1881static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1882	.name		= "mcspi3",
1883	.class		= &omap44xx_mcspi_hwmod_class,
1884	.clkdm_name	= "l4_per_clkdm",
 
1885	.sdma_reqs	= omap44xx_mcspi3_sdma_reqs,
1886	.main_clk	= "func_48m_fclk",
1887	.prcm = {
1888		.omap4 = {
1889			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1890			.context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1891			.modulemode   = MODULEMODE_SWCTRL,
1892		},
1893	},
1894	.dev_attr	= &mcspi3_dev_attr,
1895};
1896
1897/* mcspi4 */
 
 
 
 
 
1898static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
1899	{ .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
1900	{ .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
1901	{ .dma_req = -1 }
1902};
1903
1904/* mcspi4 dev_attr */
1905static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1906	.num_chipselect	= 1,
1907};
1908
1909static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1910	.name		= "mcspi4",
1911	.class		= &omap44xx_mcspi_hwmod_class,
1912	.clkdm_name	= "l4_per_clkdm",
 
1913	.sdma_reqs	= omap44xx_mcspi4_sdma_reqs,
1914	.main_clk	= "func_48m_fclk",
1915	.prcm = {
1916		.omap4 = {
1917			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1918			.context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1919			.modulemode   = MODULEMODE_SWCTRL,
1920		},
1921	},
1922	.dev_attr	= &mcspi4_dev_attr,
1923};
1924
1925/*
1926 * 'mmc' class
1927 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1928 */
1929
1930static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1931	.rev_offs	= 0x0000,
1932	.sysc_offs	= 0x0010,
1933	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1934			   SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1935			   SYSC_HAS_SOFTRESET),
1936	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1937			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1938			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1939	.sysc_fields	= &omap_hwmod_sysc_type2,
1940};
1941
1942static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1943	.name	= "mmc",
1944	.sysc	= &omap44xx_mmc_sysc,
1945};
1946
1947/* mmc1 */
 
 
 
 
 
1948static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
1949	{ .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
1950	{ .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
1951	{ .dma_req = -1 }
1952};
1953
1954/* mmc1 dev_attr */
1955static struct omap_mmc_dev_attr mmc1_dev_attr = {
1956	.flags	= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1957};
1958
1959static struct omap_hwmod omap44xx_mmc1_hwmod = {
1960	.name		= "mmc1",
1961	.class		= &omap44xx_mmc_hwmod_class,
1962	.clkdm_name	= "l3_init_clkdm",
 
1963	.sdma_reqs	= omap44xx_mmc1_sdma_reqs,
1964	.main_clk	= "hsmmc1_fclk",
1965	.prcm = {
1966		.omap4 = {
1967			.clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1968			.context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1969			.modulemode   = MODULEMODE_SWCTRL,
1970		},
1971	},
1972	.dev_attr	= &mmc1_dev_attr,
1973};
1974
1975/* mmc2 */
 
 
 
 
 
1976static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
1977	{ .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
1978	{ .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
1979	{ .dma_req = -1 }
1980};
1981
1982static struct omap_hwmod omap44xx_mmc2_hwmod = {
1983	.name		= "mmc2",
1984	.class		= &omap44xx_mmc_hwmod_class,
1985	.clkdm_name	= "l3_init_clkdm",
 
1986	.sdma_reqs	= omap44xx_mmc2_sdma_reqs,
1987	.main_clk	= "hsmmc2_fclk",
1988	.prcm = {
1989		.omap4 = {
1990			.clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1991			.context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1992			.modulemode   = MODULEMODE_SWCTRL,
1993		},
1994	},
1995};
1996
1997/* mmc3 */
 
 
 
 
 
1998static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
1999	{ .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2000	{ .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2001	{ .dma_req = -1 }
2002};
2003
2004static struct omap_hwmod omap44xx_mmc3_hwmod = {
2005	.name		= "mmc3",
2006	.class		= &omap44xx_mmc_hwmod_class,
2007	.clkdm_name	= "l4_per_clkdm",
 
2008	.sdma_reqs	= omap44xx_mmc3_sdma_reqs,
2009	.main_clk	= "func_48m_fclk",
2010	.prcm = {
2011		.omap4 = {
2012			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2013			.context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2014			.modulemode   = MODULEMODE_SWCTRL,
2015		},
2016	},
2017};
2018
2019/* mmc4 */
 
 
 
 
 
2020static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2021	{ .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2022	{ .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2023	{ .dma_req = -1 }
2024};
2025
2026static struct omap_hwmod omap44xx_mmc4_hwmod = {
2027	.name		= "mmc4",
2028	.class		= &omap44xx_mmc_hwmod_class,
2029	.clkdm_name	= "l4_per_clkdm",
 
2030	.sdma_reqs	= omap44xx_mmc4_sdma_reqs,
2031	.main_clk	= "func_48m_fclk",
2032	.prcm = {
2033		.omap4 = {
2034			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2035			.context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2036			.modulemode   = MODULEMODE_SWCTRL,
2037		},
2038	},
2039};
2040
2041/* mmc5 */
 
 
 
 
 
2042static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2043	{ .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2044	{ .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2045	{ .dma_req = -1 }
2046};
2047
2048static struct omap_hwmod omap44xx_mmc5_hwmod = {
2049	.name		= "mmc5",
2050	.class		= &omap44xx_mmc_hwmod_class,
2051	.clkdm_name	= "l4_per_clkdm",
 
2052	.sdma_reqs	= omap44xx_mmc5_sdma_reqs,
2053	.main_clk	= "func_48m_fclk",
2054	.prcm = {
2055		.omap4 = {
2056			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2057			.context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2058			.modulemode   = MODULEMODE_SWCTRL,
2059		},
2060	},
2061};
2062
2063/*
2064 * 'mmu' class
2065 * The memory management unit performs virtual to physical address translation
2066 * for its requestors.
2067 */
2068
2069static struct omap_hwmod_class_sysconfig mmu_sysc = {
2070	.rev_offs	= 0x000,
2071	.sysc_offs	= 0x010,
2072	.syss_offs	= 0x014,
2073	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2074			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2075	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2076	.sysc_fields	= &omap_hwmod_sysc_type1,
2077};
2078
2079static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2080	.name = "mmu",
2081	.sysc = &mmu_sysc,
2082};
2083
2084/* mmu ipu */
2085
2086static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2087	.da_start	= 0x0,
2088	.da_end		= 0xfffff000,
2089	.nr_tlb_entries = 32,
2090};
2091
2092static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2093static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2094	{ .name = "mmu_cache", .rst_shift = 2 },
2095};
2096
2097static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2098	{
2099		.pa_start	= 0x55082000,
2100		.pa_end		= 0x550820ff,
2101		.flags		= ADDR_TYPE_RT,
2102	},
2103	{ }
2104};
2105
2106/* l3_main_2 -> mmu_ipu */
2107static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2108	.master		= &omap44xx_l3_main_2_hwmod,
2109	.slave		= &omap44xx_mmu_ipu_hwmod,
2110	.clk		= "l3_div_ck",
2111	.addr		= omap44xx_mmu_ipu_addrs,
2112	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2113};
2114
2115static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2116	.name		= "mmu_ipu",
2117	.class		= &omap44xx_mmu_hwmod_class,
2118	.clkdm_name	= "ducati_clkdm",
2119	.rst_lines	= omap44xx_mmu_ipu_resets,
2120	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2121	.main_clk	= "ducati_clk_mux_ck",
2122	.prcm = {
2123		.omap4 = {
2124			.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2125			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2126			.context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2127			.modulemode   = MODULEMODE_HWCTRL,
2128		},
2129	},
2130	.dev_attr	= &mmu_ipu_dev_attr,
2131};
2132
2133/* mmu dsp */
2134
2135static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2136	.da_start	= 0x0,
2137	.da_end		= 0xfffff000,
2138	.nr_tlb_entries = 32,
2139};
2140
2141static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2142static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2143	{ .name = "mmu_cache", .rst_shift = 1 },
2144};
2145
2146static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2147	{
2148		.pa_start	= 0x4a066000,
2149		.pa_end		= 0x4a0660ff,
2150		.flags		= ADDR_TYPE_RT,
2151	},
2152	{ }
2153};
2154
2155/* l4_cfg -> dsp */
2156static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2157	.master		= &omap44xx_l4_cfg_hwmod,
2158	.slave		= &omap44xx_mmu_dsp_hwmod,
2159	.clk		= "l4_div_ck",
2160	.addr		= omap44xx_mmu_dsp_addrs,
2161	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2162};
2163
2164static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2165	.name		= "mmu_dsp",
2166	.class		= &omap44xx_mmu_hwmod_class,
2167	.clkdm_name	= "tesla_clkdm",
2168	.rst_lines	= omap44xx_mmu_dsp_resets,
2169	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2170	.main_clk	= "dpll_iva_m4x2_ck",
2171	.prcm = {
2172		.omap4 = {
2173			.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2174			.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2175			.context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2176			.modulemode   = MODULEMODE_HWCTRL,
2177		},
2178	},
2179	.dev_attr	= &mmu_dsp_dev_attr,
2180};
2181
2182/*
2183 * 'mpu' class
2184 * mpu sub-system
2185 */
2186
2187static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2188	.name	= "mpu",
2189};
2190
2191/* mpu */
 
 
 
 
 
 
 
2192static struct omap_hwmod omap44xx_mpu_hwmod = {
2193	.name		= "mpu",
2194	.class		= &omap44xx_mpu_hwmod_class,
2195	.clkdm_name	= "mpuss_clkdm",
2196	.flags		= HWMOD_INIT_NO_IDLE,
 
2197	.main_clk	= "dpll_mpu_m2_ck",
2198	.prcm = {
2199		.omap4 = {
2200			.clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2201			.context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2202		},
2203	},
2204};
2205
2206/*
2207 * 'ocmc_ram' class
2208 * top-level core on-chip ram
2209 */
2210
2211static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2212	.name	= "ocmc_ram",
2213};
2214
2215/* ocmc_ram */
2216static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2217	.name		= "ocmc_ram",
2218	.class		= &omap44xx_ocmc_ram_hwmod_class,
2219	.clkdm_name	= "l3_2_clkdm",
2220	.prcm = {
2221		.omap4 = {
2222			.clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2223			.context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2224		},
2225	},
2226};
2227
2228/*
2229 * 'ocp2scp' class
2230 * bridge to transform ocp interface protocol to scp (serial control port)
2231 * protocol
2232 */
2233
2234static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2235	.rev_offs	= 0x0000,
2236	.sysc_offs	= 0x0010,
2237	.syss_offs	= 0x0014,
2238	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2239			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2240	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2241	.sysc_fields	= &omap_hwmod_sysc_type1,
2242};
2243
2244static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2245	.name	= "ocp2scp",
2246	.sysc	= &omap44xx_ocp2scp_sysc,
2247};
2248
2249/* ocp2scp_usb_phy */
 
 
 
 
2250static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2251	.name		= "ocp2scp_usb_phy",
2252	.class		= &omap44xx_ocp2scp_hwmod_class,
2253	.clkdm_name	= "l3_init_clkdm",
2254	/*
2255	 * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2256	 * block as an "optional clock," and normally should never be
2257	 * specified as the main_clk for an OMAP IP block.  However it
2258	 * turns out that this clock is actually the main clock for
2259	 * the ocp2scp_usb_phy IP block:
2260	 * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2261	 * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2262	 * to be the best workaround.
2263	 */
2264	.main_clk	= "ocp2scp_usb_phy_phy_48m",
2265	.prcm = {
2266		.omap4 = {
2267			.clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2268			.context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2269			.modulemode   = MODULEMODE_HWCTRL,
2270		},
2271	},
 
 
2272};
2273
2274/*
2275 * 'prcm' class
2276 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2277 * + clock manager 1 (in always on power domain) + local prm in mpu
2278 */
2279
2280static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2281	.name	= "prcm",
2282};
2283
2284/* prcm_mpu */
2285static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2286	.name		= "prcm_mpu",
2287	.class		= &omap44xx_prcm_hwmod_class,
2288	.clkdm_name	= "l4_wkup_clkdm",
2289	.flags		= HWMOD_NO_IDLEST,
2290	.prcm = {
2291		.omap4 = {
2292			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2293		},
2294	},
2295};
2296
2297/* cm_core_aon */
2298static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2299	.name		= "cm_core_aon",
2300	.class		= &omap44xx_prcm_hwmod_class,
2301	.flags		= HWMOD_NO_IDLEST,
2302	.prcm = {
2303		.omap4 = {
2304			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2305		},
2306	},
2307};
2308
2309/* cm_core */
2310static struct omap_hwmod omap44xx_cm_core_hwmod = {
2311	.name		= "cm_core",
2312	.class		= &omap44xx_prcm_hwmod_class,
2313	.flags		= HWMOD_NO_IDLEST,
2314	.prcm = {
2315		.omap4 = {
2316			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2317		},
2318	},
2319};
2320
2321/* prm */
 
 
 
 
 
2322static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2323	{ .name = "rst_global_warm_sw", .rst_shift = 0 },
2324	{ .name = "rst_global_cold_sw", .rst_shift = 1 },
2325};
2326
2327static struct omap_hwmod omap44xx_prm_hwmod = {
2328	.name		= "prm",
2329	.class		= &omap44xx_prcm_hwmod_class,
 
 
2330	.rst_lines	= omap44xx_prm_resets,
2331	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_prm_resets),
2332};
2333
2334/*
2335 * 'scrm' class
2336 * system clock and reset manager
2337 */
2338
2339static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2340	.name	= "scrm",
2341};
2342
2343/* scrm */
2344static struct omap_hwmod omap44xx_scrm_hwmod = {
2345	.name		= "scrm",
2346	.class		= &omap44xx_scrm_hwmod_class,
2347	.clkdm_name	= "l4_wkup_clkdm",
2348	.prcm = {
2349		.omap4 = {
2350			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2351		},
2352	},
2353};
2354
2355/*
2356 * 'sl2if' class
2357 * shared level 2 memory interface
2358 */
2359
2360static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2361	.name	= "sl2if",
2362};
2363
2364/* sl2if */
2365static struct omap_hwmod omap44xx_sl2if_hwmod = {
2366	.name		= "sl2if",
2367	.class		= &omap44xx_sl2if_hwmod_class,
2368	.clkdm_name	= "ivahd_clkdm",
2369	.prcm = {
2370		.omap4 = {
2371			.clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2372			.context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2373			.modulemode   = MODULEMODE_HWCTRL,
2374		},
2375	},
2376};
2377
2378/*
2379 * 'slimbus' class
2380 * bidirectional, multi-drop, multi-channel two-line serial interface between
2381 * the device and external components
2382 */
2383
2384static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2385	.rev_offs	= 0x0000,
2386	.sysc_offs	= 0x0010,
2387	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2388			   SYSC_HAS_SOFTRESET),
2389	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2390			   SIDLE_SMART_WKUP),
2391	.sysc_fields	= &omap_hwmod_sysc_type2,
2392};
2393
2394static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2395	.name	= "slimbus",
2396	.sysc	= &omap44xx_slimbus_sysc,
2397};
2398
2399/* slimbus1 */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2400static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2401	{ .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2402	{ .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2403	{ .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2404	{ .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2405};
2406
2407static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2408	.name		= "slimbus1",
2409	.class		= &omap44xx_slimbus_hwmod_class,
2410	.clkdm_name	= "abe_clkdm",
 
 
2411	.prcm = {
2412		.omap4 = {
2413			.clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2414			.context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2415			.modulemode   = MODULEMODE_SWCTRL,
2416		},
2417	},
2418	.opt_clks	= slimbus1_opt_clks,
2419	.opt_clks_cnt	= ARRAY_SIZE(slimbus1_opt_clks),
2420};
2421
2422/* slimbus2 */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2423static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2424	{ .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2425	{ .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2426	{ .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2427};
2428
2429static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2430	.name		= "slimbus2",
2431	.class		= &omap44xx_slimbus_hwmod_class,
2432	.clkdm_name	= "l4_per_clkdm",
 
 
2433	.prcm = {
2434		.omap4 = {
2435			.clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2436			.context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2437			.modulemode   = MODULEMODE_SWCTRL,
2438		},
2439	},
2440	.opt_clks	= slimbus2_opt_clks,
2441	.opt_clks_cnt	= ARRAY_SIZE(slimbus2_opt_clks),
2442};
2443
2444/*
2445 * 'smartreflex' class
2446 * smartreflex module (monitor silicon performance and outputs a measure of
2447 * performance error)
2448 */
2449
2450/* The IP is not compliant to type1 / type2 scheme */
2451static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2452	.sidle_shift	= 24,
2453	.enwkup_shift	= 26,
2454};
2455
2456static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2457	.sysc_offs	= 0x0038,
2458	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2459	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2460			   SIDLE_SMART_WKUP),
2461	.sysc_fields	= &omap_hwmod_sysc_type_smartreflex,
2462};
2463
2464static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2465	.name	= "smartreflex",
2466	.sysc	= &omap44xx_smartreflex_sysc,
2467	.rev	= 2,
2468};
2469
2470/* smartreflex_core */
2471static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2472	.sensor_voltdm_name   = "core",
2473};
2474
 
 
 
 
 
2475static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2476	.name		= "smartreflex_core",
2477	.class		= &omap44xx_smartreflex_hwmod_class,
2478	.clkdm_name	= "l4_ao_clkdm",
 
2479
2480	.main_clk	= "smartreflex_core_fck",
2481	.prcm = {
2482		.omap4 = {
2483			.clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2484			.context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2485			.modulemode   = MODULEMODE_SWCTRL,
2486		},
2487	},
2488	.dev_attr	= &smartreflex_core_dev_attr,
2489};
2490
2491/* smartreflex_iva */
2492static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2493	.sensor_voltdm_name	= "iva",
2494};
2495
 
 
 
 
 
2496static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2497	.name		= "smartreflex_iva",
2498	.class		= &omap44xx_smartreflex_hwmod_class,
2499	.clkdm_name	= "l4_ao_clkdm",
 
2500	.main_clk	= "smartreflex_iva_fck",
2501	.prcm = {
2502		.omap4 = {
2503			.clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2504			.context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2505			.modulemode   = MODULEMODE_SWCTRL,
2506		},
2507	},
2508	.dev_attr	= &smartreflex_iva_dev_attr,
2509};
2510
2511/* smartreflex_mpu */
2512static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2513	.sensor_voltdm_name	= "mpu",
2514};
2515
 
 
 
 
 
2516static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2517	.name		= "smartreflex_mpu",
2518	.class		= &omap44xx_smartreflex_hwmod_class,
2519	.clkdm_name	= "l4_ao_clkdm",
 
2520	.main_clk	= "smartreflex_mpu_fck",
2521	.prcm = {
2522		.omap4 = {
2523			.clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2524			.context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2525			.modulemode   = MODULEMODE_SWCTRL,
2526		},
2527	},
2528	.dev_attr	= &smartreflex_mpu_dev_attr,
2529};
2530
2531/*
2532 * 'spinlock' class
2533 * spinlock provides hardware assistance for synchronizing the processes
2534 * running on multiple processors
2535 */
2536
2537static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2538	.rev_offs	= 0x0000,
2539	.sysc_offs	= 0x0010,
2540	.syss_offs	= 0x0014,
2541	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2542			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2543			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2544	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 
2545	.sysc_fields	= &omap_hwmod_sysc_type1,
2546};
2547
2548static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2549	.name	= "spinlock",
2550	.sysc	= &omap44xx_spinlock_sysc,
2551};
2552
2553/* spinlock */
2554static struct omap_hwmod omap44xx_spinlock_hwmod = {
2555	.name		= "spinlock",
2556	.class		= &omap44xx_spinlock_hwmod_class,
2557	.clkdm_name	= "l4_cfg_clkdm",
2558	.prcm = {
2559		.omap4 = {
2560			.clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2561			.context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2562		},
2563	},
2564};
2565
2566/*
2567 * 'timer' class
2568 * general purpose timer module with accurate 1ms tick
2569 * This class contains several variants: ['timer_1ms', 'timer']
2570 */
2571
2572static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2573	.rev_offs	= 0x0000,
2574	.sysc_offs	= 0x0010,
2575	.syss_offs	= 0x0014,
2576	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2577			   SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2578			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2579			   SYSS_HAS_RESET_STATUS),
2580	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2581	.clockact	= CLOCKACT_TEST_ICLK,
2582	.sysc_fields	= &omap_hwmod_sysc_type1,
2583};
2584
2585static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2586	.name	= "timer",
2587	.sysc	= &omap44xx_timer_1ms_sysc,
2588};
2589
2590static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2591	.rev_offs	= 0x0000,
2592	.sysc_offs	= 0x0010,
2593	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2594			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2595	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2596			   SIDLE_SMART_WKUP),
2597	.sysc_fields	= &omap_hwmod_sysc_type2,
2598};
2599
2600static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2601	.name	= "timer",
2602	.sysc	= &omap44xx_timer_sysc,
2603};
2604
2605/* always-on timers dev attribute */
2606static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2607	.timer_capability	= OMAP_TIMER_ALWON,
2608};
2609
2610/* pwm timers dev attribute */
2611static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2612	.timer_capability	= OMAP_TIMER_HAS_PWM,
2613};
2614
2615/* timers with DSP interrupt dev attribute */
2616static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
2617	.timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
2618};
2619
2620/* pwm timers with DSP interrupt dev attribute */
2621static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
2622	.timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
2623};
2624
2625/* timer1 */
2626static struct omap_hwmod omap44xx_timer1_hwmod = {
2627	.name		= "timer1",
2628	.class		= &omap44xx_timer_1ms_hwmod_class,
2629	.clkdm_name	= "l4_wkup_clkdm",
2630	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
2631	.main_clk	= "dmt1_clk_mux",
2632	.prcm = {
2633		.omap4 = {
2634			.clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2635			.context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2636			.modulemode   = MODULEMODE_SWCTRL,
2637		},
2638	},
2639	.dev_attr	= &capability_alwon_dev_attr,
2640};
2641
2642/* timer2 */
 
 
 
 
 
2643static struct omap_hwmod omap44xx_timer2_hwmod = {
2644	.name		= "timer2",
2645	.class		= &omap44xx_timer_1ms_hwmod_class,
2646	.clkdm_name	= "l4_per_clkdm",
2647	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
2648	.main_clk	= "cm2_dm2_mux",
2649	.prcm = {
2650		.omap4 = {
2651			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2652			.context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2653			.modulemode   = MODULEMODE_SWCTRL,
2654		},
2655	},
 
2656};
2657
2658/* timer3 */
 
 
 
 
 
2659static struct omap_hwmod omap44xx_timer3_hwmod = {
2660	.name		= "timer3",
2661	.class		= &omap44xx_timer_hwmod_class,
2662	.clkdm_name	= "l4_per_clkdm",
2663	.main_clk	= "cm2_dm3_mux",
 
2664	.prcm = {
2665		.omap4 = {
2666			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2667			.context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2668			.modulemode   = MODULEMODE_SWCTRL,
2669		},
2670	},
 
2671};
2672
2673/* timer4 */
 
 
 
 
 
2674static struct omap_hwmod omap44xx_timer4_hwmod = {
2675	.name		= "timer4",
2676	.class		= &omap44xx_timer_hwmod_class,
2677	.clkdm_name	= "l4_per_clkdm",
2678	.main_clk	= "cm2_dm4_mux",
 
2679	.prcm = {
2680		.omap4 = {
2681			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2682			.context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2683			.modulemode   = MODULEMODE_SWCTRL,
2684		},
2685	},
 
2686};
2687
2688/* timer5 */
 
 
 
 
 
2689static struct omap_hwmod omap44xx_timer5_hwmod = {
2690	.name		= "timer5",
2691	.class		= &omap44xx_timer_hwmod_class,
2692	.clkdm_name	= "abe_clkdm",
2693	.main_clk	= "timer5_sync_mux",
 
2694	.prcm = {
2695		.omap4 = {
2696			.clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2697			.context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2698			.modulemode   = MODULEMODE_SWCTRL,
2699		},
2700	},
2701	.dev_attr	= &capability_dsp_dev_attr,
2702};
2703
2704/* timer6 */
 
 
 
 
 
2705static struct omap_hwmod omap44xx_timer6_hwmod = {
2706	.name		= "timer6",
2707	.class		= &omap44xx_timer_hwmod_class,
2708	.clkdm_name	= "abe_clkdm",
2709	.main_clk	= "timer6_sync_mux",
 
 
2710	.prcm = {
2711		.omap4 = {
2712			.clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2713			.context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2714			.modulemode   = MODULEMODE_SWCTRL,
2715		},
2716	},
2717	.dev_attr	= &capability_dsp_dev_attr,
2718};
2719
2720/* timer7 */
 
 
 
 
 
2721static struct omap_hwmod omap44xx_timer7_hwmod = {
2722	.name		= "timer7",
2723	.class		= &omap44xx_timer_hwmod_class,
2724	.clkdm_name	= "abe_clkdm",
2725	.main_clk	= "timer7_sync_mux",
 
2726	.prcm = {
2727		.omap4 = {
2728			.clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2729			.context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2730			.modulemode   = MODULEMODE_SWCTRL,
2731		},
2732	},
2733	.dev_attr	= &capability_dsp_dev_attr,
2734};
2735
2736/* timer8 */
 
 
 
 
 
2737static struct omap_hwmod omap44xx_timer8_hwmod = {
2738	.name		= "timer8",
2739	.class		= &omap44xx_timer_hwmod_class,
2740	.clkdm_name	= "abe_clkdm",
2741	.main_clk	= "timer8_sync_mux",
 
2742	.prcm = {
2743		.omap4 = {
2744			.clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2745			.context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2746			.modulemode   = MODULEMODE_SWCTRL,
2747		},
2748	},
2749	.dev_attr	= &capability_dsp_pwm_dev_attr,
2750};
2751
2752/* timer9 */
 
 
 
 
 
2753static struct omap_hwmod omap44xx_timer9_hwmod = {
2754	.name		= "timer9",
2755	.class		= &omap44xx_timer_hwmod_class,
2756	.clkdm_name	= "l4_per_clkdm",
2757	.main_clk	= "cm2_dm9_mux",
 
2758	.prcm = {
2759		.omap4 = {
2760			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2761			.context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2762			.modulemode   = MODULEMODE_SWCTRL,
2763		},
2764	},
2765	.dev_attr	= &capability_pwm_dev_attr,
2766};
2767
2768/* timer10 */
 
 
 
 
 
2769static struct omap_hwmod omap44xx_timer10_hwmod = {
2770	.name		= "timer10",
2771	.class		= &omap44xx_timer_1ms_hwmod_class,
2772	.clkdm_name	= "l4_per_clkdm",
2773	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
2774	.main_clk	= "cm2_dm10_mux",
2775	.prcm = {
2776		.omap4 = {
2777			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2778			.context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2779			.modulemode   = MODULEMODE_SWCTRL,
2780		},
2781	},
2782	.dev_attr	= &capability_pwm_dev_attr,
2783};
2784
2785/* timer11 */
 
 
 
 
 
2786static struct omap_hwmod omap44xx_timer11_hwmod = {
2787	.name		= "timer11",
2788	.class		= &omap44xx_timer_hwmod_class,
2789	.clkdm_name	= "l4_per_clkdm",
2790	.main_clk	= "cm2_dm11_mux",
 
2791	.prcm = {
2792		.omap4 = {
2793			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2794			.context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2795			.modulemode   = MODULEMODE_SWCTRL,
2796		},
2797	},
2798	.dev_attr	= &capability_pwm_dev_attr,
2799};
2800
2801/*
2802 * 'uart' class
2803 * universal asynchronous receiver/transmitter (uart)
2804 */
2805
2806static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2807	.rev_offs	= 0x0050,
2808	.sysc_offs	= 0x0054,
2809	.syss_offs	= 0x0058,
2810	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2811			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2812			   SYSS_HAS_RESET_STATUS),
2813	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2814			   SIDLE_SMART_WKUP),
2815	.sysc_fields	= &omap_hwmod_sysc_type1,
2816};
2817
2818static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2819	.name	= "uart",
2820	.sysc	= &omap44xx_uart_sysc,
2821};
2822
2823/* uart1 */
 
 
 
 
 
 
 
 
 
 
 
2824static struct omap_hwmod omap44xx_uart1_hwmod = {
2825	.name		= "uart1",
2826	.class		= &omap44xx_uart_hwmod_class,
2827	.clkdm_name	= "l4_per_clkdm",
2828	.flags		= HWMOD_SWSUP_SIDLE_ACT,
2829	.main_clk	= "func_48m_fclk",
 
2830	.prcm = {
2831		.omap4 = {
2832			.clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2833			.context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2834			.modulemode   = MODULEMODE_SWCTRL,
2835		},
2836	},
2837};
2838
2839/* uart2 */
 
 
 
 
 
 
 
 
 
 
 
2840static struct omap_hwmod omap44xx_uart2_hwmod = {
2841	.name		= "uart2",
2842	.class		= &omap44xx_uart_hwmod_class,
2843	.clkdm_name	= "l4_per_clkdm",
2844	.flags		= HWMOD_SWSUP_SIDLE_ACT,
2845	.main_clk	= "func_48m_fclk",
 
2846	.prcm = {
2847		.omap4 = {
2848			.clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2849			.context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2850			.modulemode   = MODULEMODE_SWCTRL,
2851		},
2852	},
2853};
2854
2855/* uart3 */
 
 
 
 
 
 
 
 
 
 
 
2856static struct omap_hwmod omap44xx_uart3_hwmod = {
2857	.name		= "uart3",
2858	.class		= &omap44xx_uart_hwmod_class,
2859	.clkdm_name	= "l4_per_clkdm",
2860	.flags		= DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2861	.main_clk	= "func_48m_fclk",
 
 
2862	.prcm = {
2863		.omap4 = {
2864			.clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2865			.context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2866			.modulemode   = MODULEMODE_SWCTRL,
2867		},
2868	},
2869};
2870
2871/* uart4 */
 
 
 
 
 
 
 
 
 
 
 
2872static struct omap_hwmod omap44xx_uart4_hwmod = {
2873	.name		= "uart4",
2874	.class		= &omap44xx_uart_hwmod_class,
2875	.clkdm_name	= "l4_per_clkdm",
2876	.flags		= DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2877	.main_clk	= "func_48m_fclk",
 
2878	.prcm = {
2879		.omap4 = {
2880			.clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2881			.context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2882			.modulemode   = MODULEMODE_SWCTRL,
2883		},
2884	},
2885};
2886
2887/*
2888 * 'usb_host_fs' class
2889 * full-speed usb host controller
2890 */
2891
2892/* The IP is not compliant to type1 / type2 scheme */
2893static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
2894	.midle_shift	= 4,
2895	.sidle_shift	= 2,
2896	.srst_shift	= 1,
2897};
2898
2899static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2900	.rev_offs	= 0x0000,
2901	.sysc_offs	= 0x0210,
2902	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2903			   SYSC_HAS_SOFTRESET),
2904	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2905			   SIDLE_SMART_WKUP),
2906	.sysc_fields	= &omap_hwmod_sysc_type_usb_host_fs,
2907};
2908
2909static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2910	.name	= "usb_host_fs",
2911	.sysc	= &omap44xx_usb_host_fs_sysc,
2912};
2913
2914/* usb_host_fs */
 
 
 
 
 
 
2915static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2916	.name		= "usb_host_fs",
2917	.class		= &omap44xx_usb_host_fs_hwmod_class,
2918	.clkdm_name	= "l3_init_clkdm",
 
2919	.main_clk	= "usb_host_fs_fck",
2920	.prcm = {
2921		.omap4 = {
2922			.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2923			.context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2924			.modulemode   = MODULEMODE_SWCTRL,
2925		},
2926	},
2927};
2928
2929/*
2930 * 'usb_host_hs' class
2931 * high-speed multi-port usb host controller
2932 */
2933
2934static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2935	.rev_offs	= 0x0000,
2936	.sysc_offs	= 0x0010,
2937	.syss_offs	= 0x0014,
2938	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2939			   SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2940	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2941			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2942			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2943	.sysc_fields	= &omap_hwmod_sysc_type2,
2944};
2945
2946static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2947	.name	= "usb_host_hs",
2948	.sysc	= &omap44xx_usb_host_hs_sysc,
2949};
2950
2951/* usb_host_hs */
 
 
 
 
 
 
2952static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2953	.name		= "usb_host_hs",
2954	.class		= &omap44xx_usb_host_hs_hwmod_class,
2955	.clkdm_name	= "l3_init_clkdm",
2956	.main_clk	= "usb_host_hs_fck",
2957	.prcm = {
2958		.omap4 = {
2959			.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2960			.context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2961			.modulemode   = MODULEMODE_SWCTRL,
2962		},
2963	},
 
2964
2965	/*
2966	 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2967	 * id: i660
2968	 *
2969	 * Description:
2970	 * In the following configuration :
2971	 * - USBHOST module is set to smart-idle mode
2972	 * - PRCM asserts idle_req to the USBHOST module ( This typically
2973	 *   happens when the system is going to a low power mode : all ports
2974	 *   have been suspended, the master part of the USBHOST module has
2975	 *   entered the standby state, and SW has cut the functional clocks)
2976	 * - an USBHOST interrupt occurs before the module is able to answer
2977	 *   idle_ack, typically a remote wakeup IRQ.
2978	 * Then the USB HOST module will enter a deadlock situation where it
2979	 * is no more accessible nor functional.
2980	 *
2981	 * Workaround:
2982	 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2983	 */
2984
2985	/*
2986	 * Errata: USB host EHCI may stall when entering smart-standby mode
2987	 * Id: i571
2988	 *
2989	 * Description:
2990	 * When the USBHOST module is set to smart-standby mode, and when it is
2991	 * ready to enter the standby state (i.e. all ports are suspended and
2992	 * all attached devices are in suspend mode), then it can wrongly assert
2993	 * the Mstandby signal too early while there are still some residual OCP
2994	 * transactions ongoing. If this condition occurs, the internal state
2995	 * machine may go to an undefined state and the USB link may be stuck
2996	 * upon the next resume.
2997	 *
2998	 * Workaround:
2999	 * Don't use smart standby; use only force standby,
3000	 * hence HWMOD_SWSUP_MSTANDBY
3001	 */
3002
3003	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 
 
 
 
 
 
 
 
3004};
3005
3006/*
3007 * 'usb_otg_hs' class
3008 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3009 */
3010
3011static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3012	.rev_offs	= 0x0400,
3013	.sysc_offs	= 0x0404,
3014	.syss_offs	= 0x0408,
3015	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3016			   SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3017			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3018	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3019			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3020			   MSTANDBY_SMART),
3021	.sysc_fields	= &omap_hwmod_sysc_type1,
3022};
3023
3024static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3025	.name	= "usb_otg_hs",
3026	.sysc	= &omap44xx_usb_otg_hs_sysc,
3027};
3028
3029/* usb_otg_hs */
 
 
 
 
 
 
3030static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3031	{ .role = "xclk", .clk = "usb_otg_hs_xclk" },
3032};
3033
3034static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3035	.name		= "usb_otg_hs",
3036	.class		= &omap44xx_usb_otg_hs_hwmod_class,
3037	.clkdm_name	= "l3_init_clkdm",
3038	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 
3039	.main_clk	= "usb_otg_hs_ick",
3040	.prcm = {
3041		.omap4 = {
3042			.clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3043			.context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3044			.modulemode   = MODULEMODE_HWCTRL,
3045		},
3046	},
3047	.opt_clks	= usb_otg_hs_opt_clks,
3048	.opt_clks_cnt	= ARRAY_SIZE(usb_otg_hs_opt_clks),
3049};
3050
3051/*
3052 * 'usb_tll_hs' class
3053 * usb_tll_hs module is the adapter on the usb_host_hs ports
3054 */
3055
3056static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3057	.rev_offs	= 0x0000,
3058	.sysc_offs	= 0x0010,
3059	.syss_offs	= 0x0014,
3060	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3061			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3062			   SYSC_HAS_AUTOIDLE),
3063	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3064	.sysc_fields	= &omap_hwmod_sysc_type1,
3065};
3066
3067static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3068	.name	= "usb_tll_hs",
3069	.sysc	= &omap44xx_usb_tll_hs_sysc,
3070};
3071
 
 
 
 
 
3072static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3073	.name		= "usb_tll_hs",
3074	.class		= &omap44xx_usb_tll_hs_hwmod_class,
3075	.clkdm_name	= "l3_init_clkdm",
 
3076	.main_clk	= "usb_tll_hs_ick",
3077	.prcm = {
3078		.omap4 = {
3079			.clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3080			.context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3081			.modulemode   = MODULEMODE_HWCTRL,
3082		},
3083	},
3084};
3085
3086/*
3087 * 'wd_timer' class
3088 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3089 * overflow condition
3090 */
3091
3092static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3093	.rev_offs	= 0x0000,
3094	.sysc_offs	= 0x0010,
3095	.syss_offs	= 0x0014,
3096	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3097			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3098	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3099			   SIDLE_SMART_WKUP),
3100	.sysc_fields	= &omap_hwmod_sysc_type1,
3101};
3102
3103static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3104	.name		= "wd_timer",
3105	.sysc		= &omap44xx_wd_timer_sysc,
3106	.pre_shutdown	= &omap2_wd_timer_disable,
3107	.reset		= &omap2_wd_timer_reset,
3108};
3109
3110/* wd_timer2 */
 
 
 
 
 
3111static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3112	.name		= "wd_timer2",
3113	.class		= &omap44xx_wd_timer_hwmod_class,
3114	.clkdm_name	= "l4_wkup_clkdm",
3115	.main_clk	= "sys_32k_ck",
 
3116	.prcm = {
3117		.omap4 = {
3118			.clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3119			.context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3120			.modulemode   = MODULEMODE_SWCTRL,
3121		},
3122	},
3123};
3124
3125/* wd_timer3 */
 
 
 
 
 
3126static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3127	.name		= "wd_timer3",
3128	.class		= &omap44xx_wd_timer_hwmod_class,
3129	.clkdm_name	= "abe_clkdm",
3130	.main_clk	= "sys_32k_ck",
 
3131	.prcm = {
3132		.omap4 = {
3133			.clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3134			.context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3135			.modulemode   = MODULEMODE_SWCTRL,
3136		},
3137	},
3138};
3139
3140
3141/*
3142 * interfaces
3143 */
3144
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3145/* l3_main_1 -> dmm */
3146static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3147	.master		= &omap44xx_l3_main_1_hwmod,
3148	.slave		= &omap44xx_dmm_hwmod,
3149	.clk		= "l3_div_ck",
3150	.user		= OCP_USER_SDMA,
3151};
3152
 
 
 
 
 
 
 
 
 
3153/* mpu -> dmm */
3154static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3155	.master		= &omap44xx_mpu_hwmod,
3156	.slave		= &omap44xx_dmm_hwmod,
3157	.clk		= "l3_div_ck",
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3158	.user		= OCP_USER_MPU,
3159};
3160
3161/* iva -> l3_instr */
3162static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3163	.master		= &omap44xx_iva_hwmod,
3164	.slave		= &omap44xx_l3_instr_hwmod,
3165	.clk		= "l3_div_ck",
3166	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3167};
3168
3169/* l3_main_3 -> l3_instr */
3170static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3171	.master		= &omap44xx_l3_main_3_hwmod,
3172	.slave		= &omap44xx_l3_instr_hwmod,
3173	.clk		= "l3_div_ck",
3174	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3175};
3176
3177/* ocp_wp_noc -> l3_instr */
3178static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3179	.master		= &omap44xx_ocp_wp_noc_hwmod,
3180	.slave		= &omap44xx_l3_instr_hwmod,
3181	.clk		= "l3_div_ck",
3182	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3183};
3184
3185/* dsp -> l3_main_1 */
3186static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3187	.master		= &omap44xx_dsp_hwmod,
3188	.slave		= &omap44xx_l3_main_1_hwmod,
3189	.clk		= "l3_div_ck",
3190	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3191};
3192
3193/* dss -> l3_main_1 */
3194static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3195	.master		= &omap44xx_dss_hwmod,
3196	.slave		= &omap44xx_l3_main_1_hwmod,
3197	.clk		= "l3_div_ck",
3198	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3199};
3200
3201/* l3_main_2 -> l3_main_1 */
3202static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3203	.master		= &omap44xx_l3_main_2_hwmod,
3204	.slave		= &omap44xx_l3_main_1_hwmod,
3205	.clk		= "l3_div_ck",
3206	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3207};
3208
3209/* l4_cfg -> l3_main_1 */
3210static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3211	.master		= &omap44xx_l4_cfg_hwmod,
3212	.slave		= &omap44xx_l3_main_1_hwmod,
3213	.clk		= "l4_div_ck",
3214	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3215};
3216
3217/* mmc1 -> l3_main_1 */
3218static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3219	.master		= &omap44xx_mmc1_hwmod,
3220	.slave		= &omap44xx_l3_main_1_hwmod,
3221	.clk		= "l3_div_ck",
3222	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3223};
3224
3225/* mmc2 -> l3_main_1 */
3226static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3227	.master		= &omap44xx_mmc2_hwmod,
3228	.slave		= &omap44xx_l3_main_1_hwmod,
3229	.clk		= "l3_div_ck",
3230	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3231};
3232
 
 
 
 
 
 
 
 
 
3233/* mpu -> l3_main_1 */
3234static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3235	.master		= &omap44xx_mpu_hwmod,
3236	.slave		= &omap44xx_l3_main_1_hwmod,
3237	.clk		= "l3_div_ck",
 
3238	.user		= OCP_USER_MPU,
3239};
3240
 
 
 
 
 
 
 
 
3241/* debugss -> l3_main_2 */
3242static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3243	.master		= &omap44xx_debugss_hwmod,
3244	.slave		= &omap44xx_l3_main_2_hwmod,
3245	.clk		= "dbgclk_mux_ck",
3246	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3247};
3248
3249/* dma_system -> l3_main_2 */
3250static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3251	.master		= &omap44xx_dma_system_hwmod,
3252	.slave		= &omap44xx_l3_main_2_hwmod,
3253	.clk		= "l3_div_ck",
3254	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3255};
3256
3257/* fdif -> l3_main_2 */
3258static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3259	.master		= &omap44xx_fdif_hwmod,
3260	.slave		= &omap44xx_l3_main_2_hwmod,
3261	.clk		= "l3_div_ck",
3262	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3263};
3264
3265/* gpu -> l3_main_2 */
3266static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3267	.master		= &omap44xx_gpu_hwmod,
3268	.slave		= &omap44xx_l3_main_2_hwmod,
3269	.clk		= "l3_div_ck",
3270	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3271};
3272
3273/* hsi -> l3_main_2 */
3274static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3275	.master		= &omap44xx_hsi_hwmod,
3276	.slave		= &omap44xx_l3_main_2_hwmod,
3277	.clk		= "l3_div_ck",
3278	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3279};
3280
3281/* ipu -> l3_main_2 */
3282static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3283	.master		= &omap44xx_ipu_hwmod,
3284	.slave		= &omap44xx_l3_main_2_hwmod,
3285	.clk		= "l3_div_ck",
3286	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3287};
3288
3289/* iss -> l3_main_2 */
3290static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3291	.master		= &omap44xx_iss_hwmod,
3292	.slave		= &omap44xx_l3_main_2_hwmod,
3293	.clk		= "l3_div_ck",
3294	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3295};
3296
3297/* iva -> l3_main_2 */
3298static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3299	.master		= &omap44xx_iva_hwmod,
3300	.slave		= &omap44xx_l3_main_2_hwmod,
3301	.clk		= "l3_div_ck",
3302	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3303};
3304
 
 
 
 
 
 
 
 
 
3305/* l3_main_1 -> l3_main_2 */
3306static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3307	.master		= &omap44xx_l3_main_1_hwmod,
3308	.slave		= &omap44xx_l3_main_2_hwmod,
3309	.clk		= "l3_div_ck",
 
3310	.user		= OCP_USER_MPU,
3311};
3312
3313/* l4_cfg -> l3_main_2 */
3314static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3315	.master		= &omap44xx_l4_cfg_hwmod,
3316	.slave		= &omap44xx_l3_main_2_hwmod,
3317	.clk		= "l4_div_ck",
3318	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3319};
3320
3321/* usb_host_fs -> l3_main_2 */
3322static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3323	.master		= &omap44xx_usb_host_fs_hwmod,
3324	.slave		= &omap44xx_l3_main_2_hwmod,
3325	.clk		= "l3_div_ck",
3326	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3327};
3328
3329/* usb_host_hs -> l3_main_2 */
3330static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3331	.master		= &omap44xx_usb_host_hs_hwmod,
3332	.slave		= &omap44xx_l3_main_2_hwmod,
3333	.clk		= "l3_div_ck",
3334	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3335};
3336
3337/* usb_otg_hs -> l3_main_2 */
3338static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3339	.master		= &omap44xx_usb_otg_hs_hwmod,
3340	.slave		= &omap44xx_l3_main_2_hwmod,
3341	.clk		= "l3_div_ck",
3342	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3343};
3344
 
 
 
 
 
 
 
 
 
3345/* l3_main_1 -> l3_main_3 */
3346static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3347	.master		= &omap44xx_l3_main_1_hwmod,
3348	.slave		= &omap44xx_l3_main_3_hwmod,
3349	.clk		= "l3_div_ck",
 
3350	.user		= OCP_USER_MPU,
3351};
3352
3353/* l3_main_2 -> l3_main_3 */
3354static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3355	.master		= &omap44xx_l3_main_2_hwmod,
3356	.slave		= &omap44xx_l3_main_3_hwmod,
3357	.clk		= "l3_div_ck",
3358	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3359};
3360
3361/* l4_cfg -> l3_main_3 */
3362static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3363	.master		= &omap44xx_l4_cfg_hwmod,
3364	.slave		= &omap44xx_l3_main_3_hwmod,
3365	.clk		= "l4_div_ck",
3366	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3367};
3368
3369/* aess -> l4_abe */
3370static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3371	.master		= &omap44xx_aess_hwmod,
3372	.slave		= &omap44xx_l4_abe_hwmod,
3373	.clk		= "ocp_abe_iclk",
3374	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3375};
3376
3377/* dsp -> l4_abe */
3378static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3379	.master		= &omap44xx_dsp_hwmod,
3380	.slave		= &omap44xx_l4_abe_hwmod,
3381	.clk		= "ocp_abe_iclk",
3382	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3383};
3384
3385/* l3_main_1 -> l4_abe */
3386static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3387	.master		= &omap44xx_l3_main_1_hwmod,
3388	.slave		= &omap44xx_l4_abe_hwmod,
3389	.clk		= "l3_div_ck",
3390	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3391};
3392
3393/* mpu -> l4_abe */
3394static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3395	.master		= &omap44xx_mpu_hwmod,
3396	.slave		= &omap44xx_l4_abe_hwmod,
3397	.clk		= "ocp_abe_iclk",
3398	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3399};
3400
3401/* l3_main_1 -> l4_cfg */
3402static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3403	.master		= &omap44xx_l3_main_1_hwmod,
3404	.slave		= &omap44xx_l4_cfg_hwmod,
3405	.clk		= "l3_div_ck",
3406	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3407};
3408
3409/* l3_main_2 -> l4_per */
3410static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3411	.master		= &omap44xx_l3_main_2_hwmod,
3412	.slave		= &omap44xx_l4_per_hwmod,
3413	.clk		= "l3_div_ck",
3414	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3415};
3416
3417/* l4_cfg -> l4_wkup */
3418static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3419	.master		= &omap44xx_l4_cfg_hwmod,
3420	.slave		= &omap44xx_l4_wkup_hwmod,
3421	.clk		= "l4_div_ck",
3422	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3423};
3424
3425/* mpu -> mpu_private */
3426static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3427	.master		= &omap44xx_mpu_hwmod,
3428	.slave		= &omap44xx_mpu_private_hwmod,
3429	.clk		= "l3_div_ck",
3430	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3431};
3432
 
 
 
 
 
 
 
 
 
3433/* l4_cfg -> ocp_wp_noc */
3434static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3435	.master		= &omap44xx_l4_cfg_hwmod,
3436	.slave		= &omap44xx_ocp_wp_noc_hwmod,
3437	.clk		= "l4_div_ck",
 
3438	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3439};
3440
3441static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3442	{
3443		.name		= "dmem",
3444		.pa_start	= 0x40180000,
3445		.pa_end		= 0x4018ffff
3446	},
3447	{
3448		.name		= "cmem",
3449		.pa_start	= 0x401a0000,
3450		.pa_end		= 0x401a1fff
3451	},
3452	{
3453		.name		= "smem",
3454		.pa_start	= 0x401c0000,
3455		.pa_end		= 0x401c5fff
3456	},
3457	{
3458		.name		= "pmem",
3459		.pa_start	= 0x401e0000,
3460		.pa_end		= 0x401e1fff
3461	},
3462	{
3463		.name		= "mpu",
3464		.pa_start	= 0x401f1000,
3465		.pa_end		= 0x401f13ff,
3466		.flags		= ADDR_TYPE_RT
3467	},
3468	{ }
3469};
3470
3471/* l4_abe -> aess */
3472static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3473	.master		= &omap44xx_l4_abe_hwmod,
3474	.slave		= &omap44xx_aess_hwmod,
3475	.clk		= "ocp_abe_iclk",
3476	.addr		= omap44xx_aess_addrs,
3477	.user		= OCP_USER_MPU,
3478};
3479
3480static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
3481	{
3482		.name		= "dmem_dma",
3483		.pa_start	= 0x49080000,
3484		.pa_end		= 0x4908ffff
3485	},
3486	{
3487		.name		= "cmem_dma",
3488		.pa_start	= 0x490a0000,
3489		.pa_end		= 0x490a1fff
3490	},
3491	{
3492		.name		= "smem_dma",
3493		.pa_start	= 0x490c0000,
3494		.pa_end		= 0x490c5fff
3495	},
3496	{
3497		.name		= "pmem_dma",
3498		.pa_start	= 0x490e0000,
3499		.pa_end		= 0x490e1fff
3500	},
3501	{
3502		.name		= "dma",
3503		.pa_start	= 0x490f1000,
3504		.pa_end		= 0x490f13ff,
3505		.flags		= ADDR_TYPE_RT
3506	},
3507	{ }
3508};
3509
3510/* l4_abe -> aess (dma) */
3511static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3512	.master		= &omap44xx_l4_abe_hwmod,
3513	.slave		= &omap44xx_aess_hwmod,
3514	.clk		= "ocp_abe_iclk",
3515	.addr		= omap44xx_aess_dma_addrs,
3516	.user		= OCP_USER_SDMA,
3517};
3518
3519/* l3_main_2 -> c2c */
3520static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3521	.master		= &omap44xx_l3_main_2_hwmod,
3522	.slave		= &omap44xx_c2c_hwmod,
3523	.clk		= "l3_div_ck",
3524	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3525};
3526
 
 
 
 
 
 
 
 
 
3527/* l4_wkup -> counter_32k */
3528static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3529	.master		= &omap44xx_l4_wkup_hwmod,
3530	.slave		= &omap44xx_counter_32k_hwmod,
3531	.clk		= "l4_wkup_clk_mux_ck",
 
3532	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3533};
3534
3535static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
3536	{
3537		.pa_start	= 0x4a002000,
3538		.pa_end		= 0x4a0027ff,
3539		.flags		= ADDR_TYPE_RT
3540	},
3541	{ }
3542};
3543
3544/* l4_cfg -> ctrl_module_core */
3545static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3546	.master		= &omap44xx_l4_cfg_hwmod,
3547	.slave		= &omap44xx_ctrl_module_core_hwmod,
3548	.clk		= "l4_div_ck",
3549	.addr		= omap44xx_ctrl_module_core_addrs,
3550	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3551};
3552
3553static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
3554	{
3555		.pa_start	= 0x4a100000,
3556		.pa_end		= 0x4a1007ff,
3557		.flags		= ADDR_TYPE_RT
3558	},
3559	{ }
3560};
3561
3562/* l4_cfg -> ctrl_module_pad_core */
3563static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3564	.master		= &omap44xx_l4_cfg_hwmod,
3565	.slave		= &omap44xx_ctrl_module_pad_core_hwmod,
3566	.clk		= "l4_div_ck",
3567	.addr		= omap44xx_ctrl_module_pad_core_addrs,
3568	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3569};
3570
3571static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
3572	{
3573		.pa_start	= 0x4a30c000,
3574		.pa_end		= 0x4a30c7ff,
3575		.flags		= ADDR_TYPE_RT
3576	},
3577	{ }
3578};
3579
3580/* l4_wkup -> ctrl_module_wkup */
3581static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3582	.master		= &omap44xx_l4_wkup_hwmod,
3583	.slave		= &omap44xx_ctrl_module_wkup_hwmod,
3584	.clk		= "l4_wkup_clk_mux_ck",
3585	.addr		= omap44xx_ctrl_module_wkup_addrs,
3586	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3587};
3588
3589static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
3590	{
3591		.pa_start	= 0x4a31e000,
3592		.pa_end		= 0x4a31e7ff,
3593		.flags		= ADDR_TYPE_RT
3594	},
3595	{ }
3596};
3597
3598/* l4_wkup -> ctrl_module_pad_wkup */
3599static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3600	.master		= &omap44xx_l4_wkup_hwmod,
3601	.slave		= &omap44xx_ctrl_module_pad_wkup_hwmod,
3602	.clk		= "l4_wkup_clk_mux_ck",
3603	.addr		= omap44xx_ctrl_module_pad_wkup_addrs,
3604	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3605};
3606
 
 
 
 
 
 
 
 
 
3607/* l3_instr -> debugss */
3608static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3609	.master		= &omap44xx_l3_instr_hwmod,
3610	.slave		= &omap44xx_debugss_hwmod,
3611	.clk		= "l3_div_ck",
 
3612	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3613};
3614
3615static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
3616	{
3617		.pa_start	= 0x4a056000,
3618		.pa_end		= 0x4a056fff,
3619		.flags		= ADDR_TYPE_RT
3620	},
3621	{ }
3622};
3623
3624/* l4_cfg -> dma_system */
3625static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3626	.master		= &omap44xx_l4_cfg_hwmod,
3627	.slave		= &omap44xx_dma_system_hwmod,
3628	.clk		= "l4_div_ck",
3629	.addr		= omap44xx_dma_system_addrs,
3630	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3631};
3632
 
 
 
 
 
 
 
 
 
 
3633/* l4_abe -> dmic */
3634static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3635	.master		= &omap44xx_l4_abe_hwmod,
3636	.slave		= &omap44xx_dmic_hwmod,
3637	.clk		= "ocp_abe_iclk",
 
3638	.user		= OCP_USER_MPU,
3639};
3640
 
 
 
 
 
 
 
 
 
 
3641/* l4_abe -> dmic (dma) */
3642static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
3643	.master		= &omap44xx_l4_abe_hwmod,
3644	.slave		= &omap44xx_dmic_hwmod,
3645	.clk		= "ocp_abe_iclk",
 
3646	.user		= OCP_USER_SDMA,
3647};
3648
3649/* dsp -> iva */
3650static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3651	.master		= &omap44xx_dsp_hwmod,
3652	.slave		= &omap44xx_iva_hwmod,
3653	.clk		= "dpll_iva_m5x2_ck",
3654	.user		= OCP_USER_DSP,
3655};
3656
3657/* dsp -> sl2if */
3658static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3659	.master		= &omap44xx_dsp_hwmod,
3660	.slave		= &omap44xx_sl2if_hwmod,
3661	.clk		= "dpll_iva_m5x2_ck",
3662	.user		= OCP_USER_DSP,
3663};
3664
3665/* l4_cfg -> dsp */
3666static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3667	.master		= &omap44xx_l4_cfg_hwmod,
3668	.slave		= &omap44xx_dsp_hwmod,
3669	.clk		= "l4_div_ck",
3670	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3671};
3672
3673static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
3674	{
3675		.pa_start	= 0x58000000,
3676		.pa_end		= 0x5800007f,
3677		.flags		= ADDR_TYPE_RT
3678	},
3679	{ }
3680};
3681
3682/* l3_main_2 -> dss */
3683static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3684	.master		= &omap44xx_l3_main_2_hwmod,
3685	.slave		= &omap44xx_dss_hwmod,
3686	.clk		= "dss_fck",
3687	.addr		= omap44xx_dss_dma_addrs,
3688	.user		= OCP_USER_SDMA,
3689};
3690
3691static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
3692	{
3693		.pa_start	= 0x48040000,
3694		.pa_end		= 0x4804007f,
3695		.flags		= ADDR_TYPE_RT
3696	},
3697	{ }
3698};
3699
3700/* l4_per -> dss */
3701static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3702	.master		= &omap44xx_l4_per_hwmod,
3703	.slave		= &omap44xx_dss_hwmod,
3704	.clk		= "l4_div_ck",
3705	.addr		= omap44xx_dss_addrs,
3706	.user		= OCP_USER_MPU,
3707};
3708
3709static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
3710	{
3711		.pa_start	= 0x58001000,
3712		.pa_end		= 0x58001fff,
3713		.flags		= ADDR_TYPE_RT
3714	},
3715	{ }
3716};
3717
3718/* l3_main_2 -> dss_dispc */
3719static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3720	.master		= &omap44xx_l3_main_2_hwmod,
3721	.slave		= &omap44xx_dss_dispc_hwmod,
3722	.clk		= "dss_fck",
3723	.addr		= omap44xx_dss_dispc_dma_addrs,
3724	.user		= OCP_USER_SDMA,
3725};
3726
3727static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
3728	{
3729		.pa_start	= 0x48041000,
3730		.pa_end		= 0x48041fff,
3731		.flags		= ADDR_TYPE_RT
3732	},
3733	{ }
3734};
3735
3736/* l4_per -> dss_dispc */
3737static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3738	.master		= &omap44xx_l4_per_hwmod,
3739	.slave		= &omap44xx_dss_dispc_hwmod,
3740	.clk		= "l4_div_ck",
3741	.addr		= omap44xx_dss_dispc_addrs,
3742	.user		= OCP_USER_MPU,
3743};
3744
3745static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
3746	{
3747		.pa_start	= 0x58004000,
3748		.pa_end		= 0x580041ff,
3749		.flags		= ADDR_TYPE_RT
3750	},
3751	{ }
3752};
3753
3754/* l3_main_2 -> dss_dsi1 */
3755static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3756	.master		= &omap44xx_l3_main_2_hwmod,
3757	.slave		= &omap44xx_dss_dsi1_hwmod,
3758	.clk		= "dss_fck",
3759	.addr		= omap44xx_dss_dsi1_dma_addrs,
3760	.user		= OCP_USER_SDMA,
3761};
3762
3763static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
3764	{
3765		.pa_start	= 0x48044000,
3766		.pa_end		= 0x480441ff,
3767		.flags		= ADDR_TYPE_RT
3768	},
3769	{ }
3770};
3771
3772/* l4_per -> dss_dsi1 */
3773static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3774	.master		= &omap44xx_l4_per_hwmod,
3775	.slave		= &omap44xx_dss_dsi1_hwmod,
3776	.clk		= "l4_div_ck",
3777	.addr		= omap44xx_dss_dsi1_addrs,
3778	.user		= OCP_USER_MPU,
3779};
3780
3781static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
3782	{
3783		.pa_start	= 0x58005000,
3784		.pa_end		= 0x580051ff,
3785		.flags		= ADDR_TYPE_RT
3786	},
3787	{ }
3788};
3789
3790/* l3_main_2 -> dss_dsi2 */
3791static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3792	.master		= &omap44xx_l3_main_2_hwmod,
3793	.slave		= &omap44xx_dss_dsi2_hwmod,
3794	.clk		= "dss_fck",
3795	.addr		= omap44xx_dss_dsi2_dma_addrs,
3796	.user		= OCP_USER_SDMA,
3797};
3798
3799static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
3800	{
3801		.pa_start	= 0x48045000,
3802		.pa_end		= 0x480451ff,
3803		.flags		= ADDR_TYPE_RT
3804	},
3805	{ }
3806};
3807
3808/* l4_per -> dss_dsi2 */
3809static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3810	.master		= &omap44xx_l4_per_hwmod,
3811	.slave		= &omap44xx_dss_dsi2_hwmod,
3812	.clk		= "l4_div_ck",
3813	.addr		= omap44xx_dss_dsi2_addrs,
3814	.user		= OCP_USER_MPU,
3815};
3816
3817static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
3818	{
3819		.pa_start	= 0x58006000,
3820		.pa_end		= 0x58006fff,
3821		.flags		= ADDR_TYPE_RT
3822	},
3823	{ }
3824};
3825
3826/* l3_main_2 -> dss_hdmi */
3827static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3828	.master		= &omap44xx_l3_main_2_hwmod,
3829	.slave		= &omap44xx_dss_hdmi_hwmod,
3830	.clk		= "dss_fck",
3831	.addr		= omap44xx_dss_hdmi_dma_addrs,
3832	.user		= OCP_USER_SDMA,
3833};
3834
3835static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
3836	{
3837		.pa_start	= 0x48046000,
3838		.pa_end		= 0x48046fff,
3839		.flags		= ADDR_TYPE_RT
3840	},
3841	{ }
3842};
3843
3844/* l4_per -> dss_hdmi */
3845static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3846	.master		= &omap44xx_l4_per_hwmod,
3847	.slave		= &omap44xx_dss_hdmi_hwmod,
3848	.clk		= "l4_div_ck",
3849	.addr		= omap44xx_dss_hdmi_addrs,
3850	.user		= OCP_USER_MPU,
3851};
3852
3853static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
3854	{
3855		.pa_start	= 0x58002000,
3856		.pa_end		= 0x580020ff,
3857		.flags		= ADDR_TYPE_RT
3858	},
3859	{ }
3860};
3861
3862/* l3_main_2 -> dss_rfbi */
3863static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3864	.master		= &omap44xx_l3_main_2_hwmod,
3865	.slave		= &omap44xx_dss_rfbi_hwmod,
3866	.clk		= "dss_fck",
3867	.addr		= omap44xx_dss_rfbi_dma_addrs,
3868	.user		= OCP_USER_SDMA,
3869};
3870
3871static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
3872	{
3873		.pa_start	= 0x48042000,
3874		.pa_end		= 0x480420ff,
3875		.flags		= ADDR_TYPE_RT
3876	},
3877	{ }
3878};
3879
3880/* l4_per -> dss_rfbi */
3881static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3882	.master		= &omap44xx_l4_per_hwmod,
3883	.slave		= &omap44xx_dss_rfbi_hwmod,
3884	.clk		= "l4_div_ck",
3885	.addr		= omap44xx_dss_rfbi_addrs,
3886	.user		= OCP_USER_MPU,
3887};
3888
3889static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
3890	{
3891		.pa_start	= 0x58003000,
3892		.pa_end		= 0x580030ff,
3893		.flags		= ADDR_TYPE_RT
3894	},
3895	{ }
3896};
3897
3898/* l3_main_2 -> dss_venc */
3899static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3900	.master		= &omap44xx_l3_main_2_hwmod,
3901	.slave		= &omap44xx_dss_venc_hwmod,
3902	.clk		= "dss_fck",
3903	.addr		= omap44xx_dss_venc_dma_addrs,
3904	.user		= OCP_USER_SDMA,
3905};
3906
3907static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
3908	{
3909		.pa_start	= 0x48043000,
3910		.pa_end		= 0x480430ff,
3911		.flags		= ADDR_TYPE_RT
3912	},
3913	{ }
3914};
3915
3916/* l4_per -> dss_venc */
3917static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3918	.master		= &omap44xx_l4_per_hwmod,
3919	.slave		= &omap44xx_dss_venc_hwmod,
3920	.clk		= "l4_div_ck",
3921	.addr		= omap44xx_dss_venc_addrs,
3922	.user		= OCP_USER_MPU,
3923};
3924
3925static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
3926	{
3927		.pa_start	= 0x48078000,
3928		.pa_end		= 0x48078fff,
3929		.flags		= ADDR_TYPE_RT
3930	},
3931	{ }
3932};
3933
3934/* l4_per -> elm */
3935static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3936	.master		= &omap44xx_l4_per_hwmod,
3937	.slave		= &omap44xx_elm_hwmod,
3938	.clk		= "l4_div_ck",
3939	.addr		= omap44xx_elm_addrs,
3940	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3941};
3942
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3943static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
3944	{
3945		.pa_start	= 0x4a10a000,
3946		.pa_end		= 0x4a10a1ff,
3947		.flags		= ADDR_TYPE_RT
3948	},
3949	{ }
3950};
3951
3952/* l4_cfg -> fdif */
3953static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3954	.master		= &omap44xx_l4_cfg_hwmod,
3955	.slave		= &omap44xx_fdif_hwmod,
3956	.clk		= "l4_div_ck",
3957	.addr		= omap44xx_fdif_addrs,
3958	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3959};
3960
 
 
 
 
 
 
 
 
 
3961/* l4_wkup -> gpio1 */
3962static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3963	.master		= &omap44xx_l4_wkup_hwmod,
3964	.slave		= &omap44xx_gpio1_hwmod,
3965	.clk		= "l4_wkup_clk_mux_ck",
 
3966	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3967};
3968
 
 
 
 
 
 
 
 
 
3969/* l4_per -> gpio2 */
3970static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3971	.master		= &omap44xx_l4_per_hwmod,
3972	.slave		= &omap44xx_gpio2_hwmod,
3973	.clk		= "l4_div_ck",
 
3974	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3975};
3976
 
 
 
 
 
 
 
 
 
3977/* l4_per -> gpio3 */
3978static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3979	.master		= &omap44xx_l4_per_hwmod,
3980	.slave		= &omap44xx_gpio3_hwmod,
3981	.clk		= "l4_div_ck",
 
3982	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3983};
3984
 
 
 
 
 
 
 
 
 
3985/* l4_per -> gpio4 */
3986static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3987	.master		= &omap44xx_l4_per_hwmod,
3988	.slave		= &omap44xx_gpio4_hwmod,
3989	.clk		= "l4_div_ck",
 
3990	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3991};
3992
 
 
 
 
 
 
 
 
 
3993/* l4_per -> gpio5 */
3994static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3995	.master		= &omap44xx_l4_per_hwmod,
3996	.slave		= &omap44xx_gpio5_hwmod,
3997	.clk		= "l4_div_ck",
 
3998	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3999};
4000
 
 
 
 
 
 
 
 
 
4001/* l4_per -> gpio6 */
4002static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4003	.master		= &omap44xx_l4_per_hwmod,
4004	.slave		= &omap44xx_gpio6_hwmod,
4005	.clk		= "l4_div_ck",
 
4006	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4007};
4008
 
 
 
 
 
 
 
 
 
4009/* l3_main_2 -> gpmc */
4010static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4011	.master		= &omap44xx_l3_main_2_hwmod,
4012	.slave		= &omap44xx_gpmc_hwmod,
4013	.clk		= "l3_div_ck",
 
4014	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4015};
4016
4017static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4018	{
4019		.pa_start	= 0x56000000,
4020		.pa_end		= 0x5600ffff,
4021		.flags		= ADDR_TYPE_RT
4022	},
4023	{ }
4024};
4025
4026/* l3_main_2 -> gpu */
4027static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4028	.master		= &omap44xx_l3_main_2_hwmod,
4029	.slave		= &omap44xx_gpu_hwmod,
4030	.clk		= "l3_div_ck",
4031	.addr		= omap44xx_gpu_addrs,
4032	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4033};
4034
4035static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4036	{
4037		.pa_start	= 0x480b2000,
4038		.pa_end		= 0x480b201f,
4039		.flags		= ADDR_TYPE_RT
4040	},
4041	{ }
4042};
4043
4044/* l4_per -> hdq1w */
4045static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4046	.master		= &omap44xx_l4_per_hwmod,
4047	.slave		= &omap44xx_hdq1w_hwmod,
4048	.clk		= "l4_div_ck",
4049	.addr		= omap44xx_hdq1w_addrs,
4050	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4051};
4052
4053static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4054	{
4055		.pa_start	= 0x4a058000,
4056		.pa_end		= 0x4a05bfff,
4057		.flags		= ADDR_TYPE_RT
4058	},
4059	{ }
4060};
4061
4062/* l4_cfg -> hsi */
4063static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4064	.master		= &omap44xx_l4_cfg_hwmod,
4065	.slave		= &omap44xx_hsi_hwmod,
4066	.clk		= "l4_div_ck",
4067	.addr		= omap44xx_hsi_addrs,
4068	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4069};
4070
 
 
 
 
 
 
 
 
 
4071/* l4_per -> i2c1 */
4072static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4073	.master		= &omap44xx_l4_per_hwmod,
4074	.slave		= &omap44xx_i2c1_hwmod,
4075	.clk		= "l4_div_ck",
 
4076	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4077};
4078
 
 
 
 
 
 
 
 
 
4079/* l4_per -> i2c2 */
4080static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4081	.master		= &omap44xx_l4_per_hwmod,
4082	.slave		= &omap44xx_i2c2_hwmod,
4083	.clk		= "l4_div_ck",
 
4084	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4085};
4086
 
 
 
 
 
 
 
 
 
4087/* l4_per -> i2c3 */
4088static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4089	.master		= &omap44xx_l4_per_hwmod,
4090	.slave		= &omap44xx_i2c3_hwmod,
4091	.clk		= "l4_div_ck",
 
4092	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4093};
4094
 
 
 
 
 
 
 
 
 
4095/* l4_per -> i2c4 */
4096static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4097	.master		= &omap44xx_l4_per_hwmod,
4098	.slave		= &omap44xx_i2c4_hwmod,
4099	.clk		= "l4_div_ck",
 
4100	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4101};
4102
4103/* l3_main_2 -> ipu */
4104static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4105	.master		= &omap44xx_l3_main_2_hwmod,
4106	.slave		= &omap44xx_ipu_hwmod,
4107	.clk		= "l3_div_ck",
4108	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4109};
4110
4111static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4112	{
4113		.pa_start	= 0x52000000,
4114		.pa_end		= 0x520000ff,
4115		.flags		= ADDR_TYPE_RT
4116	},
4117	{ }
4118};
4119
4120/* l3_main_2 -> iss */
4121static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4122	.master		= &omap44xx_l3_main_2_hwmod,
4123	.slave		= &omap44xx_iss_hwmod,
4124	.clk		= "l3_div_ck",
4125	.addr		= omap44xx_iss_addrs,
4126	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4127};
4128
4129/* iva -> sl2if */
4130static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4131	.master		= &omap44xx_iva_hwmod,
4132	.slave		= &omap44xx_sl2if_hwmod,
4133	.clk		= "dpll_iva_m5x2_ck",
4134	.user		= OCP_USER_IVA,
4135};
4136
 
 
 
 
 
 
 
 
 
4137/* l3_main_2 -> iva */
4138static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4139	.master		= &omap44xx_l3_main_2_hwmod,
4140	.slave		= &omap44xx_iva_hwmod,
4141	.clk		= "l3_div_ck",
 
4142	.user		= OCP_USER_MPU,
4143};
4144
 
 
 
 
 
 
 
 
 
4145/* l4_wkup -> kbd */
4146static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4147	.master		= &omap44xx_l4_wkup_hwmod,
4148	.slave		= &omap44xx_kbd_hwmod,
4149	.clk		= "l4_wkup_clk_mux_ck",
 
4150	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4151};
4152
4153static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4154	{
4155		.pa_start	= 0x4a0f4000,
4156		.pa_end		= 0x4a0f41ff,
4157		.flags		= ADDR_TYPE_RT
4158	},
4159	{ }
4160};
4161
4162/* l4_cfg -> mailbox */
4163static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4164	.master		= &omap44xx_l4_cfg_hwmod,
4165	.slave		= &omap44xx_mailbox_hwmod,
4166	.clk		= "l4_div_ck",
4167	.addr		= omap44xx_mailbox_addrs,
4168	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4169};
4170
4171static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4172	{
4173		.pa_start	= 0x40128000,
4174		.pa_end		= 0x401283ff,
4175		.flags		= ADDR_TYPE_RT
4176	},
4177	{ }
4178};
4179
4180/* l4_abe -> mcasp */
4181static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4182	.master		= &omap44xx_l4_abe_hwmod,
4183	.slave		= &omap44xx_mcasp_hwmod,
4184	.clk		= "ocp_abe_iclk",
4185	.addr		= omap44xx_mcasp_addrs,
4186	.user		= OCP_USER_MPU,
4187};
4188
4189static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4190	{
4191		.pa_start	= 0x49028000,
4192		.pa_end		= 0x490283ff,
4193		.flags		= ADDR_TYPE_RT
4194	},
4195	{ }
4196};
4197
4198/* l4_abe -> mcasp (dma) */
4199static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4200	.master		= &omap44xx_l4_abe_hwmod,
4201	.slave		= &omap44xx_mcasp_hwmod,
4202	.clk		= "ocp_abe_iclk",
4203	.addr		= omap44xx_mcasp_dma_addrs,
4204	.user		= OCP_USER_SDMA,
4205};
4206
 
 
 
 
 
 
 
 
 
 
4207/* l4_abe -> mcbsp1 */
4208static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4209	.master		= &omap44xx_l4_abe_hwmod,
4210	.slave		= &omap44xx_mcbsp1_hwmod,
4211	.clk		= "ocp_abe_iclk",
 
4212	.user		= OCP_USER_MPU,
4213};
4214
 
 
 
 
 
 
 
 
 
 
4215/* l4_abe -> mcbsp1 (dma) */
4216static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4217	.master		= &omap44xx_l4_abe_hwmod,
4218	.slave		= &omap44xx_mcbsp1_hwmod,
4219	.clk		= "ocp_abe_iclk",
 
4220	.user		= OCP_USER_SDMA,
4221};
4222
 
 
 
 
 
 
 
 
 
 
4223/* l4_abe -> mcbsp2 */
4224static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4225	.master		= &omap44xx_l4_abe_hwmod,
4226	.slave		= &omap44xx_mcbsp2_hwmod,
4227	.clk		= "ocp_abe_iclk",
 
4228	.user		= OCP_USER_MPU,
4229};
4230
 
 
 
 
 
 
 
 
 
 
4231/* l4_abe -> mcbsp2 (dma) */
4232static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
4233	.master		= &omap44xx_l4_abe_hwmod,
4234	.slave		= &omap44xx_mcbsp2_hwmod,
4235	.clk		= "ocp_abe_iclk",
 
4236	.user		= OCP_USER_SDMA,
4237};
4238
 
 
 
 
 
 
 
 
 
 
4239/* l4_abe -> mcbsp3 */
4240static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
4241	.master		= &omap44xx_l4_abe_hwmod,
4242	.slave		= &omap44xx_mcbsp3_hwmod,
4243	.clk		= "ocp_abe_iclk",
 
4244	.user		= OCP_USER_MPU,
4245};
4246
 
 
 
 
 
 
 
 
 
 
4247/* l4_abe -> mcbsp3 (dma) */
4248static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
4249	.master		= &omap44xx_l4_abe_hwmod,
4250	.slave		= &omap44xx_mcbsp3_hwmod,
4251	.clk		= "ocp_abe_iclk",
 
4252	.user		= OCP_USER_SDMA,
4253};
4254
 
 
 
 
 
 
 
 
 
4255/* l4_per -> mcbsp4 */
4256static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
4257	.master		= &omap44xx_l4_per_hwmod,
4258	.slave		= &omap44xx_mcbsp4_hwmod,
4259	.clk		= "l4_div_ck",
 
4260	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4261};
4262
 
 
 
 
 
 
 
 
 
4263/* l4_abe -> mcpdm */
4264static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
4265	.master		= &omap44xx_l4_abe_hwmod,
4266	.slave		= &omap44xx_mcpdm_hwmod,
4267	.clk		= "ocp_abe_iclk",
 
4268	.user		= OCP_USER_MPU,
4269};
4270
 
 
 
 
 
 
 
 
 
4271/* l4_abe -> mcpdm (dma) */
4272static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
4273	.master		= &omap44xx_l4_abe_hwmod,
4274	.slave		= &omap44xx_mcpdm_hwmod,
4275	.clk		= "ocp_abe_iclk",
 
4276	.user		= OCP_USER_SDMA,
4277};
4278
 
 
 
 
 
 
 
 
 
4279/* l4_per -> mcspi1 */
4280static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
4281	.master		= &omap44xx_l4_per_hwmod,
4282	.slave		= &omap44xx_mcspi1_hwmod,
4283	.clk		= "l4_div_ck",
 
4284	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4285};
4286
 
 
 
 
 
 
 
 
 
4287/* l4_per -> mcspi2 */
4288static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
4289	.master		= &omap44xx_l4_per_hwmod,
4290	.slave		= &omap44xx_mcspi2_hwmod,
4291	.clk		= "l4_div_ck",
 
4292	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4293};
4294
 
 
 
 
 
 
 
 
 
4295/* l4_per -> mcspi3 */
4296static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
4297	.master		= &omap44xx_l4_per_hwmod,
4298	.slave		= &omap44xx_mcspi3_hwmod,
4299	.clk		= "l4_div_ck",
 
4300	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4301};
4302
 
 
 
 
 
 
 
 
 
4303/* l4_per -> mcspi4 */
4304static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
4305	.master		= &omap44xx_l4_per_hwmod,
4306	.slave		= &omap44xx_mcspi4_hwmod,
4307	.clk		= "l4_div_ck",
 
4308	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4309};
4310
 
 
 
 
 
 
 
 
 
4311/* l4_per -> mmc1 */
4312static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
4313	.master		= &omap44xx_l4_per_hwmod,
4314	.slave		= &omap44xx_mmc1_hwmod,
4315	.clk		= "l4_div_ck",
 
4316	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4317};
4318
 
 
 
 
 
 
 
 
 
4319/* l4_per -> mmc2 */
4320static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
4321	.master		= &omap44xx_l4_per_hwmod,
4322	.slave		= &omap44xx_mmc2_hwmod,
4323	.clk		= "l4_div_ck",
 
4324	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4325};
4326
 
 
 
 
 
 
 
 
 
4327/* l4_per -> mmc3 */
4328static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
4329	.master		= &omap44xx_l4_per_hwmod,
4330	.slave		= &omap44xx_mmc3_hwmod,
4331	.clk		= "l4_div_ck",
 
4332	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4333};
4334
 
 
 
 
 
 
 
 
 
4335/* l4_per -> mmc4 */
4336static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
4337	.master		= &omap44xx_l4_per_hwmod,
4338	.slave		= &omap44xx_mmc4_hwmod,
4339	.clk		= "l4_div_ck",
 
4340	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4341};
4342
 
 
 
 
 
 
 
 
 
4343/* l4_per -> mmc5 */
4344static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
4345	.master		= &omap44xx_l4_per_hwmod,
4346	.slave		= &omap44xx_mmc5_hwmod,
4347	.clk		= "l4_div_ck",
 
4348	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4349};
4350
4351/* l3_main_2 -> ocmc_ram */
4352static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
4353	.master		= &omap44xx_l3_main_2_hwmod,
4354	.slave		= &omap44xx_ocmc_ram_hwmod,
4355	.clk		= "l3_div_ck",
4356	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4357};
4358
4359/* l4_cfg -> ocp2scp_usb_phy */
4360static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
4361	.master		= &omap44xx_l4_cfg_hwmod,
4362	.slave		= &omap44xx_ocp2scp_usb_phy_hwmod,
4363	.clk		= "l4_div_ck",
4364	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4365};
4366
 
 
 
 
 
 
 
 
 
4367/* mpu_private -> prcm_mpu */
4368static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
4369	.master		= &omap44xx_mpu_private_hwmod,
4370	.slave		= &omap44xx_prcm_mpu_hwmod,
4371	.clk		= "l3_div_ck",
 
4372	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4373};
4374
 
 
 
 
 
 
 
 
 
4375/* l4_wkup -> cm_core_aon */
4376static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
4377	.master		= &omap44xx_l4_wkup_hwmod,
4378	.slave		= &omap44xx_cm_core_aon_hwmod,
4379	.clk		= "l4_wkup_clk_mux_ck",
 
4380	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4381};
4382
 
 
 
 
 
 
 
 
 
4383/* l4_cfg -> cm_core */
4384static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
4385	.master		= &omap44xx_l4_cfg_hwmod,
4386	.slave		= &omap44xx_cm_core_hwmod,
4387	.clk		= "l4_div_ck",
 
4388	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4389};
4390
 
 
 
 
 
 
 
 
 
4391/* l4_wkup -> prm */
4392static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
4393	.master		= &omap44xx_l4_wkup_hwmod,
4394	.slave		= &omap44xx_prm_hwmod,
4395	.clk		= "l4_wkup_clk_mux_ck",
 
4396	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4397};
4398
 
 
 
 
 
 
 
 
 
4399/* l4_wkup -> scrm */
4400static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
4401	.master		= &omap44xx_l4_wkup_hwmod,
4402	.slave		= &omap44xx_scrm_hwmod,
4403	.clk		= "l4_wkup_clk_mux_ck",
 
4404	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4405};
4406
4407/* l3_main_2 -> sl2if */
4408static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
4409	.master		= &omap44xx_l3_main_2_hwmod,
4410	.slave		= &omap44xx_sl2if_hwmod,
4411	.clk		= "l3_div_ck",
4412	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4413};
4414
4415static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
4416	{
4417		.pa_start	= 0x4012c000,
4418		.pa_end		= 0x4012c3ff,
4419		.flags		= ADDR_TYPE_RT
4420	},
4421	{ }
4422};
4423
4424/* l4_abe -> slimbus1 */
4425static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
4426	.master		= &omap44xx_l4_abe_hwmod,
4427	.slave		= &omap44xx_slimbus1_hwmod,
4428	.clk		= "ocp_abe_iclk",
4429	.addr		= omap44xx_slimbus1_addrs,
4430	.user		= OCP_USER_MPU,
4431};
4432
4433static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
4434	{
4435		.pa_start	= 0x4902c000,
4436		.pa_end		= 0x4902c3ff,
4437		.flags		= ADDR_TYPE_RT
4438	},
4439	{ }
4440};
4441
4442/* l4_abe -> slimbus1 (dma) */
4443static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
4444	.master		= &omap44xx_l4_abe_hwmod,
4445	.slave		= &omap44xx_slimbus1_hwmod,
4446	.clk		= "ocp_abe_iclk",
4447	.addr		= omap44xx_slimbus1_dma_addrs,
4448	.user		= OCP_USER_SDMA,
4449};
4450
4451static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
4452	{
4453		.pa_start	= 0x48076000,
4454		.pa_end		= 0x480763ff,
4455		.flags		= ADDR_TYPE_RT
4456	},
4457	{ }
4458};
4459
4460/* l4_per -> slimbus2 */
4461static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
4462	.master		= &omap44xx_l4_per_hwmod,
4463	.slave		= &omap44xx_slimbus2_hwmod,
4464	.clk		= "l4_div_ck",
4465	.addr		= omap44xx_slimbus2_addrs,
4466	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4467};
4468
4469static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4470	{
4471		.pa_start	= 0x4a0dd000,
4472		.pa_end		= 0x4a0dd03f,
4473		.flags		= ADDR_TYPE_RT
4474	},
4475	{ }
4476};
4477
4478/* l4_cfg -> smartreflex_core */
4479static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4480	.master		= &omap44xx_l4_cfg_hwmod,
4481	.slave		= &omap44xx_smartreflex_core_hwmod,
4482	.clk		= "l4_div_ck",
4483	.addr		= omap44xx_smartreflex_core_addrs,
4484	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4485};
4486
4487static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4488	{
4489		.pa_start	= 0x4a0db000,
4490		.pa_end		= 0x4a0db03f,
4491		.flags		= ADDR_TYPE_RT
4492	},
4493	{ }
4494};
4495
4496/* l4_cfg -> smartreflex_iva */
4497static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4498	.master		= &omap44xx_l4_cfg_hwmod,
4499	.slave		= &omap44xx_smartreflex_iva_hwmod,
4500	.clk		= "l4_div_ck",
4501	.addr		= omap44xx_smartreflex_iva_addrs,
4502	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4503};
4504
4505static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4506	{
4507		.pa_start	= 0x4a0d9000,
4508		.pa_end		= 0x4a0d903f,
4509		.flags		= ADDR_TYPE_RT
4510	},
4511	{ }
4512};
4513
4514/* l4_cfg -> smartreflex_mpu */
4515static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4516	.master		= &omap44xx_l4_cfg_hwmod,
4517	.slave		= &omap44xx_smartreflex_mpu_hwmod,
4518	.clk		= "l4_div_ck",
4519	.addr		= omap44xx_smartreflex_mpu_addrs,
4520	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4521};
4522
4523static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4524	{
4525		.pa_start	= 0x4a0f6000,
4526		.pa_end		= 0x4a0f6fff,
4527		.flags		= ADDR_TYPE_RT
4528	},
4529	{ }
4530};
4531
4532/* l4_cfg -> spinlock */
4533static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4534	.master		= &omap44xx_l4_cfg_hwmod,
4535	.slave		= &omap44xx_spinlock_hwmod,
4536	.clk		= "l4_div_ck",
4537	.addr		= omap44xx_spinlock_addrs,
4538	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4539};
4540
 
 
 
 
 
 
 
 
 
4541/* l4_wkup -> timer1 */
4542static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4543	.master		= &omap44xx_l4_wkup_hwmod,
4544	.slave		= &omap44xx_timer1_hwmod,
4545	.clk		= "l4_wkup_clk_mux_ck",
 
4546	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4547};
4548
 
 
 
 
 
 
 
 
 
4549/* l4_per -> timer2 */
4550static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4551	.master		= &omap44xx_l4_per_hwmod,
4552	.slave		= &omap44xx_timer2_hwmod,
4553	.clk		= "l4_div_ck",
 
4554	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4555};
4556
 
 
 
 
 
 
 
 
 
4557/* l4_per -> timer3 */
4558static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4559	.master		= &omap44xx_l4_per_hwmod,
4560	.slave		= &omap44xx_timer3_hwmod,
4561	.clk		= "l4_div_ck",
 
4562	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4563};
4564
 
 
 
 
 
 
 
 
 
4565/* l4_per -> timer4 */
4566static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4567	.master		= &omap44xx_l4_per_hwmod,
4568	.slave		= &omap44xx_timer4_hwmod,
4569	.clk		= "l4_div_ck",
 
4570	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4571};
4572
 
 
 
 
 
 
 
 
 
4573/* l4_abe -> timer5 */
4574static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4575	.master		= &omap44xx_l4_abe_hwmod,
4576	.slave		= &omap44xx_timer5_hwmod,
4577	.clk		= "ocp_abe_iclk",
 
4578	.user		= OCP_USER_MPU,
4579};
4580
 
 
 
 
 
 
 
 
 
4581/* l4_abe -> timer5 (dma) */
4582static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4583	.master		= &omap44xx_l4_abe_hwmod,
4584	.slave		= &omap44xx_timer5_hwmod,
4585	.clk		= "ocp_abe_iclk",
 
4586	.user		= OCP_USER_SDMA,
4587};
4588
 
 
 
 
 
 
 
 
 
4589/* l4_abe -> timer6 */
4590static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4591	.master		= &omap44xx_l4_abe_hwmod,
4592	.slave		= &omap44xx_timer6_hwmod,
4593	.clk		= "ocp_abe_iclk",
 
4594	.user		= OCP_USER_MPU,
4595};
4596
 
 
 
 
 
 
 
 
 
4597/* l4_abe -> timer6 (dma) */
4598static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4599	.master		= &omap44xx_l4_abe_hwmod,
4600	.slave		= &omap44xx_timer6_hwmod,
4601	.clk		= "ocp_abe_iclk",
 
4602	.user		= OCP_USER_SDMA,
4603};
4604
 
 
 
 
 
 
 
 
 
4605/* l4_abe -> timer7 */
4606static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4607	.master		= &omap44xx_l4_abe_hwmod,
4608	.slave		= &omap44xx_timer7_hwmod,
4609	.clk		= "ocp_abe_iclk",
 
4610	.user		= OCP_USER_MPU,
4611};
4612
 
 
 
 
 
 
 
 
 
4613/* l4_abe -> timer7 (dma) */
4614static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4615	.master		= &omap44xx_l4_abe_hwmod,
4616	.slave		= &omap44xx_timer7_hwmod,
4617	.clk		= "ocp_abe_iclk",
 
4618	.user		= OCP_USER_SDMA,
4619};
4620
 
 
 
 
 
 
 
 
 
4621/* l4_abe -> timer8 */
4622static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4623	.master		= &omap44xx_l4_abe_hwmod,
4624	.slave		= &omap44xx_timer8_hwmod,
4625	.clk		= "ocp_abe_iclk",
 
4626	.user		= OCP_USER_MPU,
4627};
4628
 
 
 
 
 
 
 
 
 
4629/* l4_abe -> timer8 (dma) */
4630static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4631	.master		= &omap44xx_l4_abe_hwmod,
4632	.slave		= &omap44xx_timer8_hwmod,
4633	.clk		= "ocp_abe_iclk",
 
4634	.user		= OCP_USER_SDMA,
4635};
4636
 
 
 
 
 
 
 
 
 
4637/* l4_per -> timer9 */
4638static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4639	.master		= &omap44xx_l4_per_hwmod,
4640	.slave		= &omap44xx_timer9_hwmod,
4641	.clk		= "l4_div_ck",
 
4642	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4643};
4644
 
 
 
 
 
 
 
 
 
4645/* l4_per -> timer10 */
4646static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4647	.master		= &omap44xx_l4_per_hwmod,
4648	.slave		= &omap44xx_timer10_hwmod,
4649	.clk		= "l4_div_ck",
 
4650	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4651};
4652
 
 
 
 
 
 
 
 
 
4653/* l4_per -> timer11 */
4654static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4655	.master		= &omap44xx_l4_per_hwmod,
4656	.slave		= &omap44xx_timer11_hwmod,
4657	.clk		= "l4_div_ck",
 
4658	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4659};
4660
 
 
 
 
 
 
 
 
 
4661/* l4_per -> uart1 */
4662static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4663	.master		= &omap44xx_l4_per_hwmod,
4664	.slave		= &omap44xx_uart1_hwmod,
4665	.clk		= "l4_div_ck",
 
4666	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4667};
4668
 
 
 
 
 
 
 
 
 
4669/* l4_per -> uart2 */
4670static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4671	.master		= &omap44xx_l4_per_hwmod,
4672	.slave		= &omap44xx_uart2_hwmod,
4673	.clk		= "l4_div_ck",
 
4674	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4675};
4676
 
 
 
 
 
 
 
 
 
4677/* l4_per -> uart3 */
4678static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4679	.master		= &omap44xx_l4_per_hwmod,
4680	.slave		= &omap44xx_uart3_hwmod,
4681	.clk		= "l4_div_ck",
 
4682	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4683};
4684
 
 
 
 
 
 
 
 
 
4685/* l4_per -> uart4 */
4686static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4687	.master		= &omap44xx_l4_per_hwmod,
4688	.slave		= &omap44xx_uart4_hwmod,
4689	.clk		= "l4_div_ck",
 
4690	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4691};
4692
 
 
 
 
 
 
 
 
 
4693/* l4_cfg -> usb_host_fs */
4694static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4695	.master		= &omap44xx_l4_cfg_hwmod,
4696	.slave		= &omap44xx_usb_host_fs_hwmod,
4697	.clk		= "l4_div_ck",
 
4698	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4699};
4700
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4701/* l4_cfg -> usb_host_hs */
4702static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4703	.master		= &omap44xx_l4_cfg_hwmod,
4704	.slave		= &omap44xx_usb_host_hs_hwmod,
4705	.clk		= "l4_div_ck",
 
4706	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4707};
4708
 
 
 
 
 
 
 
 
 
4709/* l4_cfg -> usb_otg_hs */
4710static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4711	.master		= &omap44xx_l4_cfg_hwmod,
4712	.slave		= &omap44xx_usb_otg_hs_hwmod,
4713	.clk		= "l4_div_ck",
 
4714	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4715};
4716
 
 
 
 
 
 
 
 
 
 
4717/* l4_cfg -> usb_tll_hs */
4718static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4719	.master		= &omap44xx_l4_cfg_hwmod,
4720	.slave		= &omap44xx_usb_tll_hs_hwmod,
4721	.clk		= "l4_div_ck",
 
4722	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4723};
4724
 
 
 
 
 
 
 
 
 
4725/* l4_wkup -> wd_timer2 */
4726static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4727	.master		= &omap44xx_l4_wkup_hwmod,
4728	.slave		= &omap44xx_wd_timer2_hwmod,
4729	.clk		= "l4_wkup_clk_mux_ck",
 
4730	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4731};
4732
4733static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4734	{
4735		.pa_start	= 0x40130000,
4736		.pa_end		= 0x4013007f,
4737		.flags		= ADDR_TYPE_RT
4738	},
4739	{ }
4740};
4741
4742/* l4_abe -> wd_timer3 */
4743static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4744	.master		= &omap44xx_l4_abe_hwmod,
4745	.slave		= &omap44xx_wd_timer3_hwmod,
4746	.clk		= "ocp_abe_iclk",
4747	.addr		= omap44xx_wd_timer3_addrs,
4748	.user		= OCP_USER_MPU,
4749};
4750
4751static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4752	{
4753		.pa_start	= 0x49030000,
4754		.pa_end		= 0x4903007f,
4755		.flags		= ADDR_TYPE_RT
4756	},
4757	{ }
4758};
4759
4760/* l4_abe -> wd_timer3 (dma) */
4761static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4762	.master		= &omap44xx_l4_abe_hwmod,
4763	.slave		= &omap44xx_wd_timer3_hwmod,
4764	.clk		= "ocp_abe_iclk",
4765	.addr		= omap44xx_wd_timer3_dma_addrs,
4766	.user		= OCP_USER_SDMA,
4767};
4768
4769/* mpu -> emif1 */
4770static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4771	.master		= &omap44xx_mpu_hwmod,
4772	.slave		= &omap44xx_emif1_hwmod,
4773	.clk		= "l3_div_ck",
4774	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4775};
4776
4777/* mpu -> emif2 */
4778static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4779	.master		= &omap44xx_mpu_hwmod,
4780	.slave		= &omap44xx_emif2_hwmod,
4781	.clk		= "l3_div_ck",
4782	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4783};
4784
4785static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 
 
4786	&omap44xx_l3_main_1__dmm,
4787	&omap44xx_mpu__dmm,
 
 
 
4788	&omap44xx_iva__l3_instr,
4789	&omap44xx_l3_main_3__l3_instr,
4790	&omap44xx_ocp_wp_noc__l3_instr,
4791	&omap44xx_dsp__l3_main_1,
4792	&omap44xx_dss__l3_main_1,
4793	&omap44xx_l3_main_2__l3_main_1,
4794	&omap44xx_l4_cfg__l3_main_1,
4795	&omap44xx_mmc1__l3_main_1,
4796	&omap44xx_mmc2__l3_main_1,
4797	&omap44xx_mpu__l3_main_1,
 
4798	&omap44xx_debugss__l3_main_2,
4799	&omap44xx_dma_system__l3_main_2,
4800	&omap44xx_fdif__l3_main_2,
4801	&omap44xx_gpu__l3_main_2,
4802	&omap44xx_hsi__l3_main_2,
4803	&omap44xx_ipu__l3_main_2,
4804	&omap44xx_iss__l3_main_2,
4805	&omap44xx_iva__l3_main_2,
4806	&omap44xx_l3_main_1__l3_main_2,
4807	&omap44xx_l4_cfg__l3_main_2,
4808	/* &omap44xx_usb_host_fs__l3_main_2, */
4809	&omap44xx_usb_host_hs__l3_main_2,
4810	&omap44xx_usb_otg_hs__l3_main_2,
4811	&omap44xx_l3_main_1__l3_main_3,
4812	&omap44xx_l3_main_2__l3_main_3,
4813	&omap44xx_l4_cfg__l3_main_3,
4814	&omap44xx_aess__l4_abe,
4815	&omap44xx_dsp__l4_abe,
4816	&omap44xx_l3_main_1__l4_abe,
4817	&omap44xx_mpu__l4_abe,
4818	&omap44xx_l3_main_1__l4_cfg,
4819	&omap44xx_l3_main_2__l4_per,
4820	&omap44xx_l4_cfg__l4_wkup,
4821	&omap44xx_mpu__mpu_private,
4822	&omap44xx_l4_cfg__ocp_wp_noc,
4823	&omap44xx_l4_abe__aess,
4824	&omap44xx_l4_abe__aess_dma,
4825	&omap44xx_l3_main_2__c2c,
4826	&omap44xx_l4_wkup__counter_32k,
4827	&omap44xx_l4_cfg__ctrl_module_core,
4828	&omap44xx_l4_cfg__ctrl_module_pad_core,
4829	&omap44xx_l4_wkup__ctrl_module_wkup,
4830	&omap44xx_l4_wkup__ctrl_module_pad_wkup,
4831	&omap44xx_l3_instr__debugss,
4832	&omap44xx_l4_cfg__dma_system,
4833	&omap44xx_l4_abe__dmic,
4834	&omap44xx_l4_abe__dmic_dma,
4835	&omap44xx_dsp__iva,
4836	/* &omap44xx_dsp__sl2if, */
4837	&omap44xx_l4_cfg__dsp,
4838	&omap44xx_l3_main_2__dss,
4839	&omap44xx_l4_per__dss,
4840	&omap44xx_l3_main_2__dss_dispc,
4841	&omap44xx_l4_per__dss_dispc,
4842	&omap44xx_l3_main_2__dss_dsi1,
4843	&omap44xx_l4_per__dss_dsi1,
4844	&omap44xx_l3_main_2__dss_dsi2,
4845	&omap44xx_l4_per__dss_dsi2,
4846	&omap44xx_l3_main_2__dss_hdmi,
4847	&omap44xx_l4_per__dss_hdmi,
4848	&omap44xx_l3_main_2__dss_rfbi,
4849	&omap44xx_l4_per__dss_rfbi,
4850	&omap44xx_l3_main_2__dss_venc,
4851	&omap44xx_l4_per__dss_venc,
4852	&omap44xx_l4_per__elm,
 
 
4853	&omap44xx_l4_cfg__fdif,
4854	&omap44xx_l4_wkup__gpio1,
4855	&omap44xx_l4_per__gpio2,
4856	&omap44xx_l4_per__gpio3,
4857	&omap44xx_l4_per__gpio4,
4858	&omap44xx_l4_per__gpio5,
4859	&omap44xx_l4_per__gpio6,
4860	&omap44xx_l3_main_2__gpmc,
4861	&omap44xx_l3_main_2__gpu,
4862	&omap44xx_l4_per__hdq1w,
4863	&omap44xx_l4_cfg__hsi,
4864	&omap44xx_l4_per__i2c1,
4865	&omap44xx_l4_per__i2c2,
4866	&omap44xx_l4_per__i2c3,
4867	&omap44xx_l4_per__i2c4,
4868	&omap44xx_l3_main_2__ipu,
4869	&omap44xx_l3_main_2__iss,
4870	/* &omap44xx_iva__sl2if, */
4871	&omap44xx_l3_main_2__iva,
4872	&omap44xx_l4_wkup__kbd,
4873	&omap44xx_l4_cfg__mailbox,
4874	&omap44xx_l4_abe__mcasp,
4875	&omap44xx_l4_abe__mcasp_dma,
4876	&omap44xx_l4_abe__mcbsp1,
4877	&omap44xx_l4_abe__mcbsp1_dma,
4878	&omap44xx_l4_abe__mcbsp2,
4879	&omap44xx_l4_abe__mcbsp2_dma,
4880	&omap44xx_l4_abe__mcbsp3,
4881	&omap44xx_l4_abe__mcbsp3_dma,
4882	&omap44xx_l4_per__mcbsp4,
4883	&omap44xx_l4_abe__mcpdm,
4884	&omap44xx_l4_abe__mcpdm_dma,
4885	&omap44xx_l4_per__mcspi1,
4886	&omap44xx_l4_per__mcspi2,
4887	&omap44xx_l4_per__mcspi3,
4888	&omap44xx_l4_per__mcspi4,
4889	&omap44xx_l4_per__mmc1,
4890	&omap44xx_l4_per__mmc2,
4891	&omap44xx_l4_per__mmc3,
4892	&omap44xx_l4_per__mmc4,
4893	&omap44xx_l4_per__mmc5,
4894	&omap44xx_l3_main_2__mmu_ipu,
4895	&omap44xx_l4_cfg__mmu_dsp,
4896	&omap44xx_l3_main_2__ocmc_ram,
4897	&omap44xx_l4_cfg__ocp2scp_usb_phy,
4898	&omap44xx_mpu_private__prcm_mpu,
4899	&omap44xx_l4_wkup__cm_core_aon,
4900	&omap44xx_l4_cfg__cm_core,
4901	&omap44xx_l4_wkup__prm,
4902	&omap44xx_l4_wkup__scrm,
4903	/* &omap44xx_l3_main_2__sl2if, */
4904	&omap44xx_l4_abe__slimbus1,
4905	&omap44xx_l4_abe__slimbus1_dma,
4906	&omap44xx_l4_per__slimbus2,
4907	&omap44xx_l4_cfg__smartreflex_core,
4908	&omap44xx_l4_cfg__smartreflex_iva,
4909	&omap44xx_l4_cfg__smartreflex_mpu,
4910	&omap44xx_l4_cfg__spinlock,
4911	&omap44xx_l4_wkup__timer1,
4912	&omap44xx_l4_per__timer2,
4913	&omap44xx_l4_per__timer3,
4914	&omap44xx_l4_per__timer4,
4915	&omap44xx_l4_abe__timer5,
4916	&omap44xx_l4_abe__timer5_dma,
4917	&omap44xx_l4_abe__timer6,
4918	&omap44xx_l4_abe__timer6_dma,
4919	&omap44xx_l4_abe__timer7,
4920	&omap44xx_l4_abe__timer7_dma,
4921	&omap44xx_l4_abe__timer8,
4922	&omap44xx_l4_abe__timer8_dma,
4923	&omap44xx_l4_per__timer9,
4924	&omap44xx_l4_per__timer10,
4925	&omap44xx_l4_per__timer11,
4926	&omap44xx_l4_per__uart1,
4927	&omap44xx_l4_per__uart2,
4928	&omap44xx_l4_per__uart3,
4929	&omap44xx_l4_per__uart4,
4930	/* &omap44xx_l4_cfg__usb_host_fs, */
4931	&omap44xx_l4_cfg__usb_host_hs,
4932	&omap44xx_l4_cfg__usb_otg_hs,
4933	&omap44xx_l4_cfg__usb_tll_hs,
4934	&omap44xx_l4_wkup__wd_timer2,
4935	&omap44xx_l4_abe__wd_timer3,
4936	&omap44xx_l4_abe__wd_timer3_dma,
4937	&omap44xx_mpu__emif1,
4938	&omap44xx_mpu__emif2,
4939	NULL,
4940};
4941
4942int __init omap44xx_hwmod_init(void)
4943{
4944	omap_hwmod_init();
4945	return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
4946}
4947