Loading...
1/*
2 * linux/arch/arm/kernel/bios32.c
3 *
4 * PCI bios-type initialisation for PCI machines
5 *
6 * Bits taken from various places.
7 */
8#include <linux/export.h>
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/slab.h>
12#include <linux/init.h>
13#include <linux/io.h>
14
15#include <asm/mach-types.h>
16#include <asm/mach/map.h>
17#include <asm/mach/pci.h>
18
19static int debug_pci;
20
21/*
22 * We can't use pci_get_device() here since we are
23 * called from interrupt context.
24 */
25static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
26{
27 struct pci_dev *dev;
28
29 list_for_each_entry(dev, &bus->devices, bus_list) {
30 u16 status;
31
32 /*
33 * ignore host bridge - we handle
34 * that separately
35 */
36 if (dev->bus->number == 0 && dev->devfn == 0)
37 continue;
38
39 pci_read_config_word(dev, PCI_STATUS, &status);
40 if (status == 0xffff)
41 continue;
42
43 if ((status & status_mask) == 0)
44 continue;
45
46 /* clear the status errors */
47 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
48
49 if (warn)
50 printk("(%s: %04X) ", pci_name(dev), status);
51 }
52
53 list_for_each_entry(dev, &bus->devices, bus_list)
54 if (dev->subordinate)
55 pcibios_bus_report_status(dev->subordinate, status_mask, warn);
56}
57
58void pcibios_report_status(u_int status_mask, int warn)
59{
60 struct pci_bus *bus;
61
62 list_for_each_entry(bus, &pci_root_buses, node)
63 pcibios_bus_report_status(bus, status_mask, warn);
64}
65
66/*
67 * We don't use this to fix the device, but initialisation of it.
68 * It's not the correct use for this, but it works.
69 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
70 * the following area:
71 * 1. park on CPU
72 * 2. ISA bridge ping-pong
73 * 3. ISA bridge master handling of target RETRY
74 *
75 * Bug 3 is responsible for the sound DMA grinding to a halt. We now
76 * live with bug 2.
77 */
78static void pci_fixup_83c553(struct pci_dev *dev)
79{
80 /*
81 * Set memory region to start at address 0, and enable IO
82 */
83 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
84 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
85
86 dev->resource[0].end -= dev->resource[0].start;
87 dev->resource[0].start = 0;
88
89 /*
90 * All memory requests from ISA to be channelled to PCI
91 */
92 pci_write_config_byte(dev, 0x48, 0xff);
93
94 /*
95 * Enable ping-pong on bus master to ISA bridge transactions.
96 * This improves the sound DMA substantially. The fixed
97 * priority arbiter also helps (see below).
98 */
99 pci_write_config_byte(dev, 0x42, 0x01);
100
101 /*
102 * Enable PCI retry
103 */
104 pci_write_config_byte(dev, 0x40, 0x22);
105
106 /*
107 * We used to set the arbiter to "park on last master" (bit
108 * 1 set), but unfortunately the CyberPro does not park the
109 * bus. We must therefore park on CPU. Unfortunately, this
110 * may trigger yet another bug in the 553.
111 */
112 pci_write_config_byte(dev, 0x83, 0x02);
113
114 /*
115 * Make the ISA DMA request lowest priority, and disable
116 * rotating priorities completely.
117 */
118 pci_write_config_byte(dev, 0x80, 0x11);
119 pci_write_config_byte(dev, 0x81, 0x00);
120
121 /*
122 * Route INTA input to IRQ 11, and set IRQ11 to be level
123 * sensitive.
124 */
125 pci_write_config_word(dev, 0x44, 0xb000);
126 outb(0x08, 0x4d1);
127}
128DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
129
130static void pci_fixup_unassign(struct pci_dev *dev)
131{
132 dev->resource[0].end -= dev->resource[0].start;
133 dev->resource[0].start = 0;
134}
135DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
136
137/*
138 * Prevent the PCI layer from seeing the resources allocated to this device
139 * if it is the host bridge by marking it as such. These resources are of
140 * no consequence to the PCI layer (they are handled elsewhere).
141 */
142static void pci_fixup_dec21285(struct pci_dev *dev)
143{
144 int i;
145
146 if (dev->devfn == 0) {
147 dev->class &= 0xff;
148 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
149 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
150 dev->resource[i].start = 0;
151 dev->resource[i].end = 0;
152 dev->resource[i].flags = 0;
153 }
154 }
155}
156DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
157
158/*
159 * PCI IDE controllers use non-standard I/O port decoding, respect it.
160 */
161static void pci_fixup_ide_bases(struct pci_dev *dev)
162{
163 struct resource *r;
164 int i;
165
166 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
167 return;
168
169 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
170 r = dev->resource + i;
171 if ((r->start & ~0x80) == 0x374) {
172 r->start |= 2;
173 r->end = r->start;
174 }
175 }
176}
177DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
178
179/*
180 * Put the DEC21142 to sleep
181 */
182static void pci_fixup_dec21142(struct pci_dev *dev)
183{
184 pci_write_config_dword(dev, 0x40, 0x80000000);
185}
186DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
187
188/*
189 * The CY82C693 needs some rather major fixups to ensure that it does
190 * the right thing. Idea from the Alpha people, with a few additions.
191 *
192 * We ensure that the IDE base registers are set to 1f0/3f4 for the
193 * primary bus, and 170/374 for the secondary bus. Also, hide them
194 * from the PCI subsystem view as well so we won't try to perform
195 * our own auto-configuration on them.
196 *
197 * In addition, we ensure that the PCI IDE interrupts are routed to
198 * IRQ 14 and IRQ 15 respectively.
199 *
200 * The above gets us to a point where the IDE on this device is
201 * functional. However, The CY82C693U _does not work_ in bus
202 * master mode without locking the PCI bus solid.
203 */
204static void pci_fixup_cy82c693(struct pci_dev *dev)
205{
206 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
207 u32 base0, base1;
208
209 if (dev->class & 0x80) { /* primary */
210 base0 = 0x1f0;
211 base1 = 0x3f4;
212 } else { /* secondary */
213 base0 = 0x170;
214 base1 = 0x374;
215 }
216
217 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
218 base0 | PCI_BASE_ADDRESS_SPACE_IO);
219 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
220 base1 | PCI_BASE_ADDRESS_SPACE_IO);
221
222 dev->resource[0].start = 0;
223 dev->resource[0].end = 0;
224 dev->resource[0].flags = 0;
225
226 dev->resource[1].start = 0;
227 dev->resource[1].end = 0;
228 dev->resource[1].flags = 0;
229 } else if (PCI_FUNC(dev->devfn) == 0) {
230 /*
231 * Setup IDE IRQ routing.
232 */
233 pci_write_config_byte(dev, 0x4b, 14);
234 pci_write_config_byte(dev, 0x4c, 15);
235
236 /*
237 * Disable FREQACK handshake, enable USB.
238 */
239 pci_write_config_byte(dev, 0x4d, 0x41);
240
241 /*
242 * Enable PCI retry, and PCI post-write buffer.
243 */
244 pci_write_config_byte(dev, 0x44, 0x17);
245
246 /*
247 * Enable ISA master and DMA post write buffering.
248 */
249 pci_write_config_byte(dev, 0x45, 0x03);
250 }
251}
252DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
253
254static void pci_fixup_it8152(struct pci_dev *dev)
255{
256 int i;
257 /* fixup for ITE 8152 devices */
258 /* FIXME: add defines for class 0x68000 and 0x80103 */
259 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
260 dev->class == 0x68000 ||
261 dev->class == 0x80103) {
262 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
263 dev->resource[i].start = 0;
264 dev->resource[i].end = 0;
265 dev->resource[i].flags = 0;
266 }
267 }
268}
269DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
270
271/*
272 * If the bus contains any of these devices, then we must not turn on
273 * parity checking of any kind. Currently this is CyberPro 20x0 only.
274 */
275static inline int pdev_bad_for_parity(struct pci_dev *dev)
276{
277 return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
278 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
279 dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
280 (dev->vendor == PCI_VENDOR_ID_ITE &&
281 dev->device == PCI_DEVICE_ID_ITE_8152));
282
283}
284
285/*
286 * pcibios_fixup_bus - Called after each bus is probed,
287 * but before its children are examined.
288 */
289void pcibios_fixup_bus(struct pci_bus *bus)
290{
291 struct pci_dev *dev;
292 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
293
294 /*
295 * Walk the devices on this bus, working out what we can
296 * and can't support.
297 */
298 list_for_each_entry(dev, &bus->devices, bus_list) {
299 u16 status;
300
301 pci_read_config_word(dev, PCI_STATUS, &status);
302
303 /*
304 * If any device on this bus does not support fast back
305 * to back transfers, then the bus as a whole is not able
306 * to support them. Having fast back to back transfers
307 * on saves us one PCI cycle per transaction.
308 */
309 if (!(status & PCI_STATUS_FAST_BACK))
310 features &= ~PCI_COMMAND_FAST_BACK;
311
312 if (pdev_bad_for_parity(dev))
313 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
314
315 switch (dev->class >> 8) {
316 case PCI_CLASS_BRIDGE_PCI:
317 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
318 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
319 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
320 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
321 break;
322
323 case PCI_CLASS_BRIDGE_CARDBUS:
324 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
325 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
326 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
327 break;
328 }
329 }
330
331 /*
332 * Now walk the devices again, this time setting them up.
333 */
334 list_for_each_entry(dev, &bus->devices, bus_list) {
335 u16 cmd;
336
337 pci_read_config_word(dev, PCI_COMMAND, &cmd);
338 cmd |= features;
339 pci_write_config_word(dev, PCI_COMMAND, cmd);
340
341 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
342 L1_CACHE_BYTES >> 2);
343 }
344
345 /*
346 * Propagate the flags to the PCI bridge.
347 */
348 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
349 if (features & PCI_COMMAND_FAST_BACK)
350 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
351 if (features & PCI_COMMAND_PARITY)
352 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
353 }
354
355 /*
356 * Report what we did for this bus
357 */
358 printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
359 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
360}
361EXPORT_SYMBOL(pcibios_fixup_bus);
362
363void pcibios_add_bus(struct pci_bus *bus)
364{
365 struct pci_sys_data *sys = bus->sysdata;
366 if (sys->add_bus)
367 sys->add_bus(bus);
368}
369
370void pcibios_remove_bus(struct pci_bus *bus)
371{
372 struct pci_sys_data *sys = bus->sysdata;
373 if (sys->remove_bus)
374 sys->remove_bus(bus);
375}
376
377/*
378 * Swizzle the device pin each time we cross a bridge. If a platform does
379 * not provide a swizzle function, we perform the standard PCI swizzling.
380 *
381 * The default swizzling walks up the bus tree one level at a time, applying
382 * the standard swizzle function at each step, stopping when it finds the PCI
383 * root bus. This will return the slot number of the bridge device on the
384 * root bus and the interrupt pin on that device which should correspond
385 * with the downstream device interrupt.
386 *
387 * Platforms may override this, in which case the slot and pin returned
388 * depend entirely on the platform code. However, please note that the
389 * PCI standard swizzle is implemented on plug-in cards and Cardbus based
390 * PCI extenders, so it can not be ignored.
391 */
392static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin)
393{
394 struct pci_sys_data *sys = dev->sysdata;
395 int slot, oldpin = *pin;
396
397 if (sys->swizzle)
398 slot = sys->swizzle(dev, pin);
399 else
400 slot = pci_common_swizzle(dev, pin);
401
402 if (debug_pci)
403 printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
404 pci_name(dev), oldpin, *pin, slot);
405
406 return slot;
407}
408
409/*
410 * Map a slot/pin to an IRQ.
411 */
412static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
413{
414 struct pci_sys_data *sys = dev->sysdata;
415 int irq = -1;
416
417 if (sys->map_irq)
418 irq = sys->map_irq(dev, slot, pin);
419
420 if (debug_pci)
421 printk("PCI: %s mapping slot %d pin %d => irq %d\n",
422 pci_name(dev), slot, pin, irq);
423
424 return irq;
425}
426
427static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
428{
429 int ret;
430 struct pci_host_bridge_window *window;
431
432 if (list_empty(&sys->resources)) {
433 pci_add_resource_offset(&sys->resources,
434 &iomem_resource, sys->mem_offset);
435 }
436
437 list_for_each_entry(window, &sys->resources, list) {
438 if (resource_type(window->res) == IORESOURCE_IO)
439 return 0;
440 }
441
442 sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
443 sys->io_res.end = (busnr + 1) * SZ_64K - 1;
444 sys->io_res.flags = IORESOURCE_IO;
445 sys->io_res.name = sys->io_res_name;
446 sprintf(sys->io_res_name, "PCI%d I/O", busnr);
447
448 ret = request_resource(&ioport_resource, &sys->io_res);
449 if (ret) {
450 pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
451 return ret;
452 }
453 pci_add_resource_offset(&sys->resources, &sys->io_res,
454 sys->io_offset);
455
456 return 0;
457}
458
459static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
460 struct list_head *head)
461{
462 struct pci_sys_data *sys = NULL;
463 int ret;
464 int nr, busnr;
465
466 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
467 sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
468 if (!sys)
469 panic("PCI: unable to allocate sys data!");
470
471#ifdef CONFIG_PCI_DOMAINS
472 sys->domain = hw->domain;
473#endif
474 sys->busnr = busnr;
475 sys->swizzle = hw->swizzle;
476 sys->map_irq = hw->map_irq;
477 sys->align_resource = hw->align_resource;
478 sys->add_bus = hw->add_bus;
479 sys->remove_bus = hw->remove_bus;
480 INIT_LIST_HEAD(&sys->resources);
481
482 if (hw->private_data)
483 sys->private_data = hw->private_data[nr];
484
485 ret = hw->setup(nr, sys);
486
487 if (ret > 0) {
488 ret = pcibios_init_resources(nr, sys);
489 if (ret) {
490 kfree(sys);
491 break;
492 }
493
494 if (hw->scan)
495 sys->bus = hw->scan(nr, sys);
496 else
497 sys->bus = pci_scan_root_bus(parent, sys->busnr,
498 hw->ops, sys, &sys->resources);
499
500 if (!sys->bus)
501 panic("PCI: unable to scan bus!");
502
503 busnr = sys->bus->busn_res.end + 1;
504
505 list_add(&sys->node, head);
506 } else {
507 kfree(sys);
508 if (ret < 0)
509 break;
510 }
511 }
512}
513
514void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
515{
516 struct pci_sys_data *sys;
517 LIST_HEAD(head);
518
519 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
520 if (hw->preinit)
521 hw->preinit();
522 pcibios_init_hw(parent, hw, &head);
523 if (hw->postinit)
524 hw->postinit();
525
526 pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
527
528 list_for_each_entry(sys, &head, node) {
529 struct pci_bus *bus = sys->bus;
530
531 if (!pci_has_flag(PCI_PROBE_ONLY)) {
532 /*
533 * Size the bridge windows.
534 */
535 pci_bus_size_bridges(bus);
536
537 /*
538 * Assign resources.
539 */
540 pci_bus_assign_resources(bus);
541 }
542
543 /*
544 * Tell drivers about devices found.
545 */
546 pci_bus_add_devices(bus);
547 }
548}
549
550#ifndef CONFIG_PCI_HOST_ITE8152
551void pcibios_set_master(struct pci_dev *dev)
552{
553 /* No special bus mastering setup handling */
554}
555#endif
556
557char * __init pcibios_setup(char *str)
558{
559 if (!strcmp(str, "debug")) {
560 debug_pci = 1;
561 return NULL;
562 } else if (!strcmp(str, "firmware")) {
563 pci_add_flags(PCI_PROBE_ONLY);
564 return NULL;
565 }
566 return str;
567}
568
569/*
570 * From arch/i386/kernel/pci-i386.c:
571 *
572 * We need to avoid collisions with `mirrored' VGA ports
573 * and other strange ISA hardware, so we always want the
574 * addresses to be allocated in the 0x000-0x0ff region
575 * modulo 0x400.
576 *
577 * Why? Because some silly external IO cards only decode
578 * the low 10 bits of the IO address. The 0x00-0xff region
579 * is reserved for motherboard devices that decode all 16
580 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
581 * but we want to try to avoid allocating at 0x2900-0x2bff
582 * which might be mirrored at 0x0100-0x03ff..
583 */
584resource_size_t pcibios_align_resource(void *data, const struct resource *res,
585 resource_size_t size, resource_size_t align)
586{
587 struct pci_dev *dev = data;
588 struct pci_sys_data *sys = dev->sysdata;
589 resource_size_t start = res->start;
590
591 if (res->flags & IORESOURCE_IO && start & 0x300)
592 start = (start + 0x3ff) & ~0x3ff;
593
594 start = (start + align - 1) & ~(align - 1);
595
596 if (sys->align_resource)
597 return sys->align_resource(dev, res, start, size, align);
598
599 return start;
600}
601
602/**
603 * pcibios_enable_device - Enable I/O and memory.
604 * @dev: PCI device to be enabled
605 */
606int pcibios_enable_device(struct pci_dev *dev, int mask)
607{
608 if (pci_has_flag(PCI_PROBE_ONLY))
609 return 0;
610
611 return pci_enable_resources(dev, mask);
612}
613
614int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
615 enum pci_mmap_state mmap_state, int write_combine)
616{
617 struct pci_sys_data *root = dev->sysdata;
618 unsigned long phys;
619
620 if (mmap_state == pci_mmap_io) {
621 return -EINVAL;
622 } else {
623 phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
624 }
625
626 /*
627 * Mark this as IO
628 */
629 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
630
631 if (remap_pfn_range(vma, vma->vm_start, phys,
632 vma->vm_end - vma->vm_start,
633 vma->vm_page_prot))
634 return -EAGAIN;
635
636 return 0;
637}
638
639void __init pci_map_io_early(unsigned long pfn)
640{
641 struct map_desc pci_io_desc = {
642 .virtual = PCI_IO_VIRT_BASE,
643 .type = MT_DEVICE,
644 .length = SZ_64K,
645 };
646
647 pci_io_desc.pfn = pfn;
648 iotable_init(&pci_io_desc, 1);
649}
1/*
2 * linux/arch/arm/kernel/bios32.c
3 *
4 * PCI bios-type initialisation for PCI machines
5 *
6 * Bits taken from various places.
7 */
8#include <linux/export.h>
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/slab.h>
12#include <linux/init.h>
13#include <linux/io.h>
14
15#include <asm/mach-types.h>
16#include <asm/mach/pci.h>
17
18static int debug_pci;
19
20/*
21 * We can't use pci_find_device() here since we are
22 * called from interrupt context.
23 */
24static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
25{
26 struct pci_dev *dev;
27
28 list_for_each_entry(dev, &bus->devices, bus_list) {
29 u16 status;
30
31 /*
32 * ignore host bridge - we handle
33 * that separately
34 */
35 if (dev->bus->number == 0 && dev->devfn == 0)
36 continue;
37
38 pci_read_config_word(dev, PCI_STATUS, &status);
39 if (status == 0xffff)
40 continue;
41
42 if ((status & status_mask) == 0)
43 continue;
44
45 /* clear the status errors */
46 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
47
48 if (warn)
49 printk("(%s: %04X) ", pci_name(dev), status);
50 }
51
52 list_for_each_entry(dev, &bus->devices, bus_list)
53 if (dev->subordinate)
54 pcibios_bus_report_status(dev->subordinate, status_mask, warn);
55}
56
57void pcibios_report_status(u_int status_mask, int warn)
58{
59 struct list_head *l;
60
61 list_for_each(l, &pci_root_buses) {
62 struct pci_bus *bus = pci_bus_b(l);
63
64 pcibios_bus_report_status(bus, status_mask, warn);
65 }
66}
67
68/*
69 * We don't use this to fix the device, but initialisation of it.
70 * It's not the correct use for this, but it works.
71 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
72 * the following area:
73 * 1. park on CPU
74 * 2. ISA bridge ping-pong
75 * 3. ISA bridge master handling of target RETRY
76 *
77 * Bug 3 is responsible for the sound DMA grinding to a halt. We now
78 * live with bug 2.
79 */
80static void __devinit pci_fixup_83c553(struct pci_dev *dev)
81{
82 /*
83 * Set memory region to start at address 0, and enable IO
84 */
85 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
86 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
87
88 dev->resource[0].end -= dev->resource[0].start;
89 dev->resource[0].start = 0;
90
91 /*
92 * All memory requests from ISA to be channelled to PCI
93 */
94 pci_write_config_byte(dev, 0x48, 0xff);
95
96 /*
97 * Enable ping-pong on bus master to ISA bridge transactions.
98 * This improves the sound DMA substantially. The fixed
99 * priority arbiter also helps (see below).
100 */
101 pci_write_config_byte(dev, 0x42, 0x01);
102
103 /*
104 * Enable PCI retry
105 */
106 pci_write_config_byte(dev, 0x40, 0x22);
107
108 /*
109 * We used to set the arbiter to "park on last master" (bit
110 * 1 set), but unfortunately the CyberPro does not park the
111 * bus. We must therefore park on CPU. Unfortunately, this
112 * may trigger yet another bug in the 553.
113 */
114 pci_write_config_byte(dev, 0x83, 0x02);
115
116 /*
117 * Make the ISA DMA request lowest priority, and disable
118 * rotating priorities completely.
119 */
120 pci_write_config_byte(dev, 0x80, 0x11);
121 pci_write_config_byte(dev, 0x81, 0x00);
122
123 /*
124 * Route INTA input to IRQ 11, and set IRQ11 to be level
125 * sensitive.
126 */
127 pci_write_config_word(dev, 0x44, 0xb000);
128 outb(0x08, 0x4d1);
129}
130DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
131
132static void __devinit pci_fixup_unassign(struct pci_dev *dev)
133{
134 dev->resource[0].end -= dev->resource[0].start;
135 dev->resource[0].start = 0;
136}
137DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
138
139/*
140 * Prevent the PCI layer from seeing the resources allocated to this device
141 * if it is the host bridge by marking it as such. These resources are of
142 * no consequence to the PCI layer (they are handled elsewhere).
143 */
144static void __devinit pci_fixup_dec21285(struct pci_dev *dev)
145{
146 int i;
147
148 if (dev->devfn == 0) {
149 dev->class &= 0xff;
150 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
151 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
152 dev->resource[i].start = 0;
153 dev->resource[i].end = 0;
154 dev->resource[i].flags = 0;
155 }
156 }
157}
158DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
159
160/*
161 * PCI IDE controllers use non-standard I/O port decoding, respect it.
162 */
163static void __devinit pci_fixup_ide_bases(struct pci_dev *dev)
164{
165 struct resource *r;
166 int i;
167
168 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
169 return;
170
171 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
172 r = dev->resource + i;
173 if ((r->start & ~0x80) == 0x374) {
174 r->start |= 2;
175 r->end = r->start;
176 }
177 }
178}
179DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
180
181/*
182 * Put the DEC21142 to sleep
183 */
184static void __devinit pci_fixup_dec21142(struct pci_dev *dev)
185{
186 pci_write_config_dword(dev, 0x40, 0x80000000);
187}
188DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
189
190/*
191 * The CY82C693 needs some rather major fixups to ensure that it does
192 * the right thing. Idea from the Alpha people, with a few additions.
193 *
194 * We ensure that the IDE base registers are set to 1f0/3f4 for the
195 * primary bus, and 170/374 for the secondary bus. Also, hide them
196 * from the PCI subsystem view as well so we won't try to perform
197 * our own auto-configuration on them.
198 *
199 * In addition, we ensure that the PCI IDE interrupts are routed to
200 * IRQ 14 and IRQ 15 respectively.
201 *
202 * The above gets us to a point where the IDE on this device is
203 * functional. However, The CY82C693U _does not work_ in bus
204 * master mode without locking the PCI bus solid.
205 */
206static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
207{
208 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
209 u32 base0, base1;
210
211 if (dev->class & 0x80) { /* primary */
212 base0 = 0x1f0;
213 base1 = 0x3f4;
214 } else { /* secondary */
215 base0 = 0x170;
216 base1 = 0x374;
217 }
218
219 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
220 base0 | PCI_BASE_ADDRESS_SPACE_IO);
221 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
222 base1 | PCI_BASE_ADDRESS_SPACE_IO);
223
224 dev->resource[0].start = 0;
225 dev->resource[0].end = 0;
226 dev->resource[0].flags = 0;
227
228 dev->resource[1].start = 0;
229 dev->resource[1].end = 0;
230 dev->resource[1].flags = 0;
231 } else if (PCI_FUNC(dev->devfn) == 0) {
232 /*
233 * Setup IDE IRQ routing.
234 */
235 pci_write_config_byte(dev, 0x4b, 14);
236 pci_write_config_byte(dev, 0x4c, 15);
237
238 /*
239 * Disable FREQACK handshake, enable USB.
240 */
241 pci_write_config_byte(dev, 0x4d, 0x41);
242
243 /*
244 * Enable PCI retry, and PCI post-write buffer.
245 */
246 pci_write_config_byte(dev, 0x44, 0x17);
247
248 /*
249 * Enable ISA master and DMA post write buffering.
250 */
251 pci_write_config_byte(dev, 0x45, 0x03);
252 }
253}
254DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
255
256static void __init pci_fixup_it8152(struct pci_dev *dev)
257{
258 int i;
259 /* fixup for ITE 8152 devices */
260 /* FIXME: add defines for class 0x68000 and 0x80103 */
261 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
262 dev->class == 0x68000 ||
263 dev->class == 0x80103) {
264 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
265 dev->resource[i].start = 0;
266 dev->resource[i].end = 0;
267 dev->resource[i].flags = 0;
268 }
269 }
270}
271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
272
273
274
275void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
276{
277 if (debug_pci)
278 printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev));
279 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
280}
281
282/*
283 * If the bus contains any of these devices, then we must not turn on
284 * parity checking of any kind. Currently this is CyberPro 20x0 only.
285 */
286static inline int pdev_bad_for_parity(struct pci_dev *dev)
287{
288 return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
289 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
290 dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
291 (dev->vendor == PCI_VENDOR_ID_ITE &&
292 dev->device == PCI_DEVICE_ID_ITE_8152));
293
294}
295
296/*
297 * pcibios_fixup_bus - Called after each bus is probed,
298 * but before its children are examined.
299 */
300void pcibios_fixup_bus(struct pci_bus *bus)
301{
302 struct pci_dev *dev;
303 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
304
305 /*
306 * Walk the devices on this bus, working out what we can
307 * and can't support.
308 */
309 list_for_each_entry(dev, &bus->devices, bus_list) {
310 u16 status;
311
312 pci_read_config_word(dev, PCI_STATUS, &status);
313
314 /*
315 * If any device on this bus does not support fast back
316 * to back transfers, then the bus as a whole is not able
317 * to support them. Having fast back to back transfers
318 * on saves us one PCI cycle per transaction.
319 */
320 if (!(status & PCI_STATUS_FAST_BACK))
321 features &= ~PCI_COMMAND_FAST_BACK;
322
323 if (pdev_bad_for_parity(dev))
324 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
325
326 switch (dev->class >> 8) {
327 case PCI_CLASS_BRIDGE_PCI:
328 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
329 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
330 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
331 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
332 break;
333
334 case PCI_CLASS_BRIDGE_CARDBUS:
335 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
336 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
337 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
338 break;
339 }
340 }
341
342 /*
343 * Now walk the devices again, this time setting them up.
344 */
345 list_for_each_entry(dev, &bus->devices, bus_list) {
346 u16 cmd;
347
348 pci_read_config_word(dev, PCI_COMMAND, &cmd);
349 cmd |= features;
350 pci_write_config_word(dev, PCI_COMMAND, cmd);
351
352 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
353 L1_CACHE_BYTES >> 2);
354 }
355
356 /*
357 * Propagate the flags to the PCI bridge.
358 */
359 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
360 if (features & PCI_COMMAND_FAST_BACK)
361 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
362 if (features & PCI_COMMAND_PARITY)
363 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
364 }
365
366 /*
367 * Report what we did for this bus
368 */
369 printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
370 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
371}
372#ifdef CONFIG_HOTPLUG
373EXPORT_SYMBOL(pcibios_fixup_bus);
374#endif
375
376/*
377 * Swizzle the device pin each time we cross a bridge. If a platform does
378 * not provide a swizzle function, we perform the standard PCI swizzling.
379 *
380 * The default swizzling walks up the bus tree one level at a time, applying
381 * the standard swizzle function at each step, stopping when it finds the PCI
382 * root bus. This will return the slot number of the bridge device on the
383 * root bus and the interrupt pin on that device which should correspond
384 * with the downstream device interrupt.
385 *
386 * Platforms may override this, in which case the slot and pin returned
387 * depend entirely on the platform code. However, please note that the
388 * PCI standard swizzle is implemented on plug-in cards and Cardbus based
389 * PCI extenders, so it can not be ignored.
390 */
391static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin)
392{
393 struct pci_sys_data *sys = dev->sysdata;
394 int slot, oldpin = *pin;
395
396 if (sys->swizzle)
397 slot = sys->swizzle(dev, pin);
398 else
399 slot = pci_common_swizzle(dev, pin);
400
401 if (debug_pci)
402 printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
403 pci_name(dev), oldpin, *pin, slot);
404
405 return slot;
406}
407
408/*
409 * Map a slot/pin to an IRQ.
410 */
411static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
412{
413 struct pci_sys_data *sys = dev->sysdata;
414 int irq = -1;
415
416 if (sys->map_irq)
417 irq = sys->map_irq(dev, slot, pin);
418
419 if (debug_pci)
420 printk("PCI: %s mapping slot %d pin %d => irq %d\n",
421 pci_name(dev), slot, pin, irq);
422
423 return irq;
424}
425
426static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
427{
428 struct pci_sys_data *sys = NULL;
429 int ret;
430 int nr, busnr;
431
432 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
433 sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
434 if (!sys)
435 panic("PCI: unable to allocate sys data!");
436
437#ifdef CONFIG_PCI_DOMAINS
438 sys->domain = hw->domain;
439#endif
440 sys->busnr = busnr;
441 sys->swizzle = hw->swizzle;
442 sys->map_irq = hw->map_irq;
443 INIT_LIST_HEAD(&sys->resources);
444
445 ret = hw->setup(nr, sys);
446
447 if (ret > 0) {
448 if (list_empty(&sys->resources)) {
449 pci_add_resource_offset(&sys->resources,
450 &ioport_resource, sys->io_offset);
451 pci_add_resource_offset(&sys->resources,
452 &iomem_resource, sys->mem_offset);
453 }
454
455 if (hw->scan)
456 sys->bus = hw->scan(nr, sys);
457 else
458 sys->bus = pci_scan_root_bus(NULL, sys->busnr,
459 hw->ops, sys, &sys->resources);
460
461 if (!sys->bus)
462 panic("PCI: unable to scan bus!");
463
464 busnr = sys->bus->subordinate + 1;
465
466 list_add(&sys->node, head);
467 } else {
468 kfree(sys);
469 if (ret < 0)
470 break;
471 }
472 }
473}
474
475void __init pci_common_init(struct hw_pci *hw)
476{
477 struct pci_sys_data *sys;
478 LIST_HEAD(head);
479
480 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
481 if (hw->preinit)
482 hw->preinit();
483 pcibios_init_hw(hw, &head);
484 if (hw->postinit)
485 hw->postinit();
486
487 pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
488
489 list_for_each_entry(sys, &head, node) {
490 struct pci_bus *bus = sys->bus;
491
492 if (!pci_has_flag(PCI_PROBE_ONLY)) {
493 /*
494 * Size the bridge windows.
495 */
496 pci_bus_size_bridges(bus);
497
498 /*
499 * Assign resources.
500 */
501 pci_bus_assign_resources(bus);
502
503 /*
504 * Enable bridges
505 */
506 pci_enable_bridges(bus);
507 }
508
509 /*
510 * Tell drivers about devices found.
511 */
512 pci_bus_add_devices(bus);
513 }
514}
515
516#ifndef CONFIG_PCI_HOST_ITE8152
517void pcibios_set_master(struct pci_dev *dev)
518{
519 /* No special bus mastering setup handling */
520}
521#endif
522
523char * __init pcibios_setup(char *str)
524{
525 if (!strcmp(str, "debug")) {
526 debug_pci = 1;
527 return NULL;
528 } else if (!strcmp(str, "firmware")) {
529 pci_add_flags(PCI_PROBE_ONLY);
530 return NULL;
531 }
532 return str;
533}
534
535/*
536 * From arch/i386/kernel/pci-i386.c:
537 *
538 * We need to avoid collisions with `mirrored' VGA ports
539 * and other strange ISA hardware, so we always want the
540 * addresses to be allocated in the 0x000-0x0ff region
541 * modulo 0x400.
542 *
543 * Why? Because some silly external IO cards only decode
544 * the low 10 bits of the IO address. The 0x00-0xff region
545 * is reserved for motherboard devices that decode all 16
546 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
547 * but we want to try to avoid allocating at 0x2900-0x2bff
548 * which might be mirrored at 0x0100-0x03ff..
549 */
550resource_size_t pcibios_align_resource(void *data, const struct resource *res,
551 resource_size_t size, resource_size_t align)
552{
553 resource_size_t start = res->start;
554
555 if (res->flags & IORESOURCE_IO && start & 0x300)
556 start = (start + 0x3ff) & ~0x3ff;
557
558 start = (start + align - 1) & ~(align - 1);
559
560 return start;
561}
562
563/**
564 * pcibios_enable_device - Enable I/O and memory.
565 * @dev: PCI device to be enabled
566 */
567int pcibios_enable_device(struct pci_dev *dev, int mask)
568{
569 u16 cmd, old_cmd;
570 int idx;
571 struct resource *r;
572
573 pci_read_config_word(dev, PCI_COMMAND, &cmd);
574 old_cmd = cmd;
575 for (idx = 0; idx < 6; idx++) {
576 /* Only set up the requested stuff */
577 if (!(mask & (1 << idx)))
578 continue;
579
580 r = dev->resource + idx;
581 if (!r->start && r->end) {
582 printk(KERN_ERR "PCI: Device %s not available because"
583 " of resource collisions\n", pci_name(dev));
584 return -EINVAL;
585 }
586 if (r->flags & IORESOURCE_IO)
587 cmd |= PCI_COMMAND_IO;
588 if (r->flags & IORESOURCE_MEM)
589 cmd |= PCI_COMMAND_MEMORY;
590 }
591
592 /*
593 * Bridges (eg, cardbus bridges) need to be fully enabled
594 */
595 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
596 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
597
598 if (cmd != old_cmd) {
599 printk("PCI: enabling device %s (%04x -> %04x)\n",
600 pci_name(dev), old_cmd, cmd);
601 pci_write_config_word(dev, PCI_COMMAND, cmd);
602 }
603 return 0;
604}
605
606int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
607 enum pci_mmap_state mmap_state, int write_combine)
608{
609 struct pci_sys_data *root = dev->sysdata;
610 unsigned long phys;
611
612 if (mmap_state == pci_mmap_io) {
613 return -EINVAL;
614 } else {
615 phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
616 }
617
618 /*
619 * Mark this as IO
620 */
621 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
622
623 if (remap_pfn_range(vma, vma->vm_start, phys,
624 vma->vm_end - vma->vm_start,
625 vma->vm_page_prot))
626 return -EAGAIN;
627
628 return 0;
629}