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1/*
2 * arch/arm/include/asm/ptrace.h
3 *
4 * Copyright (C) 1996-2003 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_ARM_PTRACE_H
11#define __ASM_ARM_PTRACE_H
12
13#include <uapi/asm/ptrace.h>
14
15#ifndef __ASSEMBLY__
16struct pt_regs {
17 unsigned long uregs[18];
18};
19
20#define user_mode(regs) \
21 (((regs)->ARM_cpsr & 0xf) == 0)
22
23#ifdef CONFIG_ARM_THUMB
24#define thumb_mode(regs) \
25 (((regs)->ARM_cpsr & PSR_T_BIT))
26#else
27#define thumb_mode(regs) (0)
28#endif
29
30#ifndef CONFIG_CPU_V7M
31#define isa_mode(regs) \
32 ((((regs)->ARM_cpsr & PSR_J_BIT) >> (__ffs(PSR_J_BIT) - 1)) | \
33 (((regs)->ARM_cpsr & PSR_T_BIT) >> (__ffs(PSR_T_BIT))))
34#else
35#define isa_mode(regs) 1 /* Thumb */
36#endif
37
38#define processor_mode(regs) \
39 ((regs)->ARM_cpsr & MODE_MASK)
40
41#define interrupts_enabled(regs) \
42 (!((regs)->ARM_cpsr & PSR_I_BIT))
43
44#define fast_interrupts_enabled(regs) \
45 (!((regs)->ARM_cpsr & PSR_F_BIT))
46
47/* Are the current registers suitable for user mode?
48 * (used to maintain security in signal handlers)
49 */
50static inline int valid_user_regs(struct pt_regs *regs)
51{
52#ifndef CONFIG_CPU_V7M
53 unsigned long mode = regs->ARM_cpsr & MODE_MASK;
54
55 /*
56 * Always clear the F (FIQ) and A (delayed abort) bits
57 */
58 regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
59
60 if ((regs->ARM_cpsr & PSR_I_BIT) == 0) {
61 if (mode == USR_MODE)
62 return 1;
63 if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE)
64 return 1;
65 }
66
67 /*
68 * Force CPSR to something logical...
69 */
70 regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
71 if (!(elf_hwcap & HWCAP_26BIT))
72 regs->ARM_cpsr |= USR_MODE;
73
74 return 0;
75#else /* ifndef CONFIG_CPU_V7M */
76 return 1;
77#endif
78}
79
80static inline long regs_return_value(struct pt_regs *regs)
81{
82 return regs->ARM_r0;
83}
84
85#define instruction_pointer(regs) (regs)->ARM_pc
86
87static inline void instruction_pointer_set(struct pt_regs *regs,
88 unsigned long val)
89{
90 instruction_pointer(regs) = val;
91}
92
93#ifdef CONFIG_SMP
94extern unsigned long profile_pc(struct pt_regs *regs);
95#else
96#define profile_pc(regs) instruction_pointer(regs)
97#endif
98
99#define predicate(x) ((x) & 0xf0000000)
100#define PREDICATE_ALWAYS 0xe0000000
101
102/*
103 * True if instr is a 32-bit thumb instruction. This works if instr
104 * is the first or only half-word of a thumb instruction. It also works
105 * when instr holds all 32-bits of a wide thumb instruction if stored
106 * in the form (first_half<<16)|(second_half)
107 */
108#define is_wide_instruction(instr) ((unsigned)(instr) >= 0xe800)
109
110/*
111 * kprobe-based event tracer support
112 */
113#include <linux/stddef.h>
114#include <linux/types.h>
115#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
116
117extern int regs_query_register_offset(const char *name);
118extern const char *regs_query_register_name(unsigned int offset);
119extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
120extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
121 unsigned int n);
122
123/**
124 * regs_get_register() - get register value from its offset
125 * @regs: pt_regs from which register value is gotten
126 * @offset: offset number of the register.
127 *
128 * regs_get_register returns the value of a register whose offset from @regs.
129 * The @offset is the offset of the register in struct pt_regs.
130 * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
131 */
132static inline unsigned long regs_get_register(struct pt_regs *regs,
133 unsigned int offset)
134{
135 if (unlikely(offset > MAX_REG_OFFSET))
136 return 0;
137 return *(unsigned long *)((unsigned long)regs + offset);
138}
139
140/* Valid only for Kernel mode traps. */
141static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
142{
143 return regs->ARM_sp;
144}
145
146static inline unsigned long user_stack_pointer(struct pt_regs *regs)
147{
148 return regs->ARM_sp;
149}
150
151#define current_pt_regs(void) ({ \
152 register unsigned long sp asm ("sp"); \
153 (struct pt_regs *)((sp | (THREAD_SIZE - 1)) - 7) - 1; \
154})
155
156#endif /* __ASSEMBLY__ */
157#endif
1/*
2 * arch/arm/include/asm/ptrace.h
3 *
4 * Copyright (C) 1996-2003 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_ARM_PTRACE_H
11#define __ASM_ARM_PTRACE_H
12
13#include <asm/hwcap.h>
14
15#define PTRACE_GETREGS 12
16#define PTRACE_SETREGS 13
17#define PTRACE_GETFPREGS 14
18#define PTRACE_SETFPREGS 15
19/* PTRACE_ATTACH is 16 */
20/* PTRACE_DETACH is 17 */
21#define PTRACE_GETWMMXREGS 18
22#define PTRACE_SETWMMXREGS 19
23/* 20 is unused */
24#define PTRACE_OLDSETOPTIONS 21
25#define PTRACE_GET_THREAD_AREA 22
26#define PTRACE_SET_SYSCALL 23
27/* PTRACE_SYSCALL is 24 */
28#define PTRACE_GETCRUNCHREGS 25
29#define PTRACE_SETCRUNCHREGS 26
30#define PTRACE_GETVFPREGS 27
31#define PTRACE_SETVFPREGS 28
32#define PTRACE_GETHBPREGS 29
33#define PTRACE_SETHBPREGS 30
34
35/*
36 * PSR bits
37 */
38#define USR26_MODE 0x00000000
39#define FIQ26_MODE 0x00000001
40#define IRQ26_MODE 0x00000002
41#define SVC26_MODE 0x00000003
42#define USR_MODE 0x00000010
43#define FIQ_MODE 0x00000011
44#define IRQ_MODE 0x00000012
45#define SVC_MODE 0x00000013
46#define ABT_MODE 0x00000017
47#define UND_MODE 0x0000001b
48#define SYSTEM_MODE 0x0000001f
49#define MODE32_BIT 0x00000010
50#define MODE_MASK 0x0000001f
51#define PSR_T_BIT 0x00000020
52#define PSR_F_BIT 0x00000040
53#define PSR_I_BIT 0x00000080
54#define PSR_A_BIT 0x00000100
55#define PSR_E_BIT 0x00000200
56#define PSR_J_BIT 0x01000000
57#define PSR_Q_BIT 0x08000000
58#define PSR_V_BIT 0x10000000
59#define PSR_C_BIT 0x20000000
60#define PSR_Z_BIT 0x40000000
61#define PSR_N_BIT 0x80000000
62
63/*
64 * Groups of PSR bits
65 */
66#define PSR_f 0xff000000 /* Flags */
67#define PSR_s 0x00ff0000 /* Status */
68#define PSR_x 0x0000ff00 /* Extension */
69#define PSR_c 0x000000ff /* Control */
70
71/*
72 * ARMv7 groups of PSR bits
73 */
74#define APSR_MASK 0xf80f0000 /* N, Z, C, V, Q and GE flags */
75#define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */
76#define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
77#define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */
78
79/*
80 * Default endianness state
81 */
82#ifdef CONFIG_CPU_ENDIAN_BE8
83#define PSR_ENDSTATE PSR_E_BIT
84#else
85#define PSR_ENDSTATE 0
86#endif
87
88/*
89 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
90 * process is located in memory.
91 */
92#define PT_TEXT_ADDR 0x10000
93#define PT_DATA_ADDR 0x10004
94#define PT_TEXT_END_ADDR 0x10008
95
96#ifndef __ASSEMBLY__
97
98/*
99 * This struct defines the way the registers are stored on the
100 * stack during a system call. Note that sizeof(struct pt_regs)
101 * has to be a multiple of 8.
102 */
103#ifndef __KERNEL__
104struct pt_regs {
105 long uregs[18];
106};
107#else /* __KERNEL__ */
108struct pt_regs {
109 unsigned long uregs[18];
110};
111#endif /* __KERNEL__ */
112
113#define ARM_cpsr uregs[16]
114#define ARM_pc uregs[15]
115#define ARM_lr uregs[14]
116#define ARM_sp uregs[13]
117#define ARM_ip uregs[12]
118#define ARM_fp uregs[11]
119#define ARM_r10 uregs[10]
120#define ARM_r9 uregs[9]
121#define ARM_r8 uregs[8]
122#define ARM_r7 uregs[7]
123#define ARM_r6 uregs[6]
124#define ARM_r5 uregs[5]
125#define ARM_r4 uregs[4]
126#define ARM_r3 uregs[3]
127#define ARM_r2 uregs[2]
128#define ARM_r1 uregs[1]
129#define ARM_r0 uregs[0]
130#define ARM_ORIG_r0 uregs[17]
131
132/*
133 * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS
134 * and core dumps.
135 */
136#define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ )
137
138#ifdef __KERNEL__
139
140#define user_mode(regs) \
141 (((regs)->ARM_cpsr & 0xf) == 0)
142
143#ifdef CONFIG_ARM_THUMB
144#define thumb_mode(regs) \
145 (((regs)->ARM_cpsr & PSR_T_BIT))
146#else
147#define thumb_mode(regs) (0)
148#endif
149
150#define isa_mode(regs) \
151 ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
152 (((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
153
154#define processor_mode(regs) \
155 ((regs)->ARM_cpsr & MODE_MASK)
156
157#define interrupts_enabled(regs) \
158 (!((regs)->ARM_cpsr & PSR_I_BIT))
159
160#define fast_interrupts_enabled(regs) \
161 (!((regs)->ARM_cpsr & PSR_F_BIT))
162
163/* Are the current registers suitable for user mode?
164 * (used to maintain security in signal handlers)
165 */
166static inline int valid_user_regs(struct pt_regs *regs)
167{
168 unsigned long mode = regs->ARM_cpsr & MODE_MASK;
169
170 /*
171 * Always clear the F (FIQ) and A (delayed abort) bits
172 */
173 regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
174
175 if ((regs->ARM_cpsr & PSR_I_BIT) == 0) {
176 if (mode == USR_MODE)
177 return 1;
178 if (elf_hwcap & HWCAP_26BIT && mode == USR26_MODE)
179 return 1;
180 }
181
182 /*
183 * Force CPSR to something logical...
184 */
185 regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
186 if (!(elf_hwcap & HWCAP_26BIT))
187 regs->ARM_cpsr |= USR_MODE;
188
189 return 0;
190}
191
192static inline long regs_return_value(struct pt_regs *regs)
193{
194 return regs->ARM_r0;
195}
196
197#define instruction_pointer(regs) (regs)->ARM_pc
198
199#ifdef CONFIG_SMP
200extern unsigned long profile_pc(struct pt_regs *regs);
201#else
202#define profile_pc(regs) instruction_pointer(regs)
203#endif
204
205#define predicate(x) ((x) & 0xf0000000)
206#define PREDICATE_ALWAYS 0xe0000000
207
208/*
209 * True if instr is a 32-bit thumb instruction. This works if instr
210 * is the first or only half-word of a thumb instruction. It also works
211 * when instr holds all 32-bits of a wide thumb instruction if stored
212 * in the form (first_half<<16)|(second_half)
213 */
214#define is_wide_instruction(instr) ((unsigned)(instr) >= 0xe800)
215
216/*
217 * kprobe-based event tracer support
218 */
219#include <linux/stddef.h>
220#include <linux/types.h>
221#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
222
223extern int regs_query_register_offset(const char *name);
224extern const char *regs_query_register_name(unsigned int offset);
225extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
226extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
227 unsigned int n);
228
229/**
230 * regs_get_register() - get register value from its offset
231 * @regs: pt_regs from which register value is gotten
232 * @offset: offset number of the register.
233 *
234 * regs_get_register returns the value of a register whose offset from @regs.
235 * The @offset is the offset of the register in struct pt_regs.
236 * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
237 */
238static inline unsigned long regs_get_register(struct pt_regs *regs,
239 unsigned int offset)
240{
241 if (unlikely(offset > MAX_REG_OFFSET))
242 return 0;
243 return *(unsigned long *)((unsigned long)regs + offset);
244}
245
246/* Valid only for Kernel mode traps. */
247static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
248{
249 return regs->ARM_sp;
250}
251
252static inline unsigned long user_stack_pointer(struct pt_regs *regs)
253{
254 return regs->ARM_sp;
255}
256
257#endif /* __KERNEL__ */
258
259#endif /* __ASSEMBLY__ */
260
261#endif
262