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1/*
2 * R8A66597 UDC
3 *
4 * Copyright (C) 2007-2009 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 */
12
13#ifndef __R8A66597_H__
14#define __R8A66597_H__
15
16#include <linux/clk.h>
17#include <linux/usb/r8a66597.h>
18
19#define R8A66597_MAX_SAMPLING 10
20
21#define R8A66597_MAX_NUM_PIPE 8
22#define R8A66597_MAX_NUM_BULK 3
23#define R8A66597_MAX_NUM_ISOC 2
24#define R8A66597_MAX_NUM_INT 2
25
26#define R8A66597_BASE_PIPENUM_BULK 3
27#define R8A66597_BASE_PIPENUM_ISOC 1
28#define R8A66597_BASE_PIPENUM_INT 6
29
30#define R8A66597_BASE_BUFNUM 6
31#define R8A66597_MAX_BUFNUM 0x4F
32
33#define is_bulk_pipe(pipenum) \
34 ((pipenum >= R8A66597_BASE_PIPENUM_BULK) && \
35 (pipenum < (R8A66597_BASE_PIPENUM_BULK + R8A66597_MAX_NUM_BULK)))
36#define is_interrupt_pipe(pipenum) \
37 ((pipenum >= R8A66597_BASE_PIPENUM_INT) && \
38 (pipenum < (R8A66597_BASE_PIPENUM_INT + R8A66597_MAX_NUM_INT)))
39#define is_isoc_pipe(pipenum) \
40 ((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \
41 (pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC)))
42
43#define r8a66597_is_sudmac(r8a66597) (r8a66597->pdata->sudmac)
44struct r8a66597_pipe_info {
45 u16 pipe;
46 u16 epnum;
47 u16 maxpacket;
48 u16 type;
49 u16 interval;
50 u16 dir_in;
51};
52
53struct r8a66597_request {
54 struct usb_request req;
55 struct list_head queue;
56};
57
58struct r8a66597_ep {
59 struct usb_ep ep;
60 struct r8a66597 *r8a66597;
61 struct r8a66597_dma *dma;
62
63 struct list_head queue;
64 unsigned busy:1;
65 unsigned wedge:1;
66 unsigned internal_ccpl:1; /* use only control */
67
68 /* this member can able to after r8a66597_enable */
69 unsigned use_dma:1;
70 u16 pipenum;
71 u16 type;
72
73 /* register address */
74 unsigned char fifoaddr;
75 unsigned char fifosel;
76 unsigned char fifoctr;
77 unsigned char pipectr;
78 unsigned char pipetre;
79 unsigned char pipetrn;
80};
81
82struct r8a66597_dma {
83 unsigned used:1;
84 unsigned dir:1; /* 1 = IN(write), 0 = OUT(read) */
85};
86
87struct r8a66597 {
88 spinlock_t lock;
89 void __iomem *reg;
90 void __iomem *sudmac_reg;
91
92 struct clk *clk;
93 struct r8a66597_platdata *pdata;
94
95 struct usb_gadget gadget;
96 struct usb_gadget_driver *driver;
97
98 struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE];
99 struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE];
100 struct r8a66597_ep *epaddr2ep[16];
101 struct r8a66597_dma dma;
102
103 struct timer_list timer;
104 struct usb_request *ep0_req; /* for internal request */
105 u16 ep0_data; /* for internal request */
106 u16 old_vbus;
107 u16 scount;
108 u16 old_dvsq;
109 u16 device_status; /* for GET_STATUS */
110
111 /* pipe config */
112 unsigned char bulk;
113 unsigned char interrupt;
114 unsigned char isochronous;
115 unsigned char num_dma;
116
117 unsigned irq_sense_low:1;
118};
119
120#define gadget_to_r8a66597(_gadget) \
121 container_of(_gadget, struct r8a66597, gadget)
122#define r8a66597_to_gadget(r8a66597) (&r8a66597->gadget)
123#define r8a66597_to_dev(r8a66597) (r8a66597->gadget.dev.parent)
124
125static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
126{
127 return ioread16(r8a66597->reg + offset);
128}
129
130static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
131 unsigned long offset,
132 unsigned char *buf,
133 int len)
134{
135 void __iomem *fifoaddr = r8a66597->reg + offset;
136 unsigned int data = 0;
137 int i;
138
139 if (r8a66597->pdata->on_chip) {
140 /* 32-bit accesses for on_chip controllers */
141
142 /* aligned buf case */
143 if (len >= 4 && !((unsigned long)buf & 0x03)) {
144 ioread32_rep(fifoaddr, buf, len / 4);
145 buf += len & ~0x03;
146 len &= 0x03;
147 }
148
149 /* unaligned buf case */
150 for (i = 0; i < len; i++) {
151 if (!(i & 0x03))
152 data = ioread32(fifoaddr);
153
154 buf[i] = (data >> ((i & 0x03) * 8)) & 0xff;
155 }
156 } else {
157 /* 16-bit accesses for external controllers */
158
159 /* aligned buf case */
160 if (len >= 2 && !((unsigned long)buf & 0x01)) {
161 ioread16_rep(fifoaddr, buf, len / 2);
162 buf += len & ~0x01;
163 len &= 0x01;
164 }
165
166 /* unaligned buf case */
167 for (i = 0; i < len; i++) {
168 if (!(i & 0x01))
169 data = ioread16(fifoaddr);
170
171 buf[i] = (data >> ((i & 0x01) * 8)) & 0xff;
172 }
173 }
174}
175
176static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
177 unsigned long offset)
178{
179 iowrite16(val, r8a66597->reg + offset);
180}
181
182static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
183 u16 val, u16 pat, unsigned long offset)
184{
185 u16 tmp;
186 tmp = r8a66597_read(r8a66597, offset);
187 tmp = tmp & (~pat);
188 tmp = tmp | val;
189 r8a66597_write(r8a66597, tmp, offset);
190}
191
192#define r8a66597_bclr(r8a66597, val, offset) \
193 r8a66597_mdfy(r8a66597, 0, val, offset)
194#define r8a66597_bset(r8a66597, val, offset) \
195 r8a66597_mdfy(r8a66597, val, 0, offset)
196
197static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
198 struct r8a66597_ep *ep,
199 unsigned char *buf,
200 int len)
201{
202 void __iomem *fifoaddr = r8a66597->reg + ep->fifoaddr;
203 int adj = 0;
204 int i;
205
206 if (r8a66597->pdata->on_chip) {
207 /* 32-bit access only if buf is 32-bit aligned */
208 if (len >= 4 && !((unsigned long)buf & 0x03)) {
209 iowrite32_rep(fifoaddr, buf, len / 4);
210 buf += len & ~0x03;
211 len &= 0x03;
212 }
213 } else {
214 /* 16-bit access only if buf is 16-bit aligned */
215 if (len >= 2 && !((unsigned long)buf & 0x01)) {
216 iowrite16_rep(fifoaddr, buf, len / 2);
217 buf += len & ~0x01;
218 len &= 0x01;
219 }
220 }
221
222 /* adjust fifo address in the little endian case */
223 if (!(r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)) {
224 if (r8a66597->pdata->on_chip)
225 adj = 0x03; /* 32-bit wide */
226 else
227 adj = 0x01; /* 16-bit wide */
228 }
229
230 if (r8a66597->pdata->wr0_shorted_to_wr1)
231 r8a66597_bclr(r8a66597, MBW_16, ep->fifosel);
232 for (i = 0; i < len; i++)
233 iowrite8(buf[i], fifoaddr + adj - (i & adj));
234 if (r8a66597->pdata->wr0_shorted_to_wr1)
235 r8a66597_bclr(r8a66597, MBW_16, ep->fifosel);
236}
237
238static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
239{
240 u16 clock = 0;
241
242 switch (pdata->xtal) {
243 case R8A66597_PLATDATA_XTAL_12MHZ:
244 clock = XTAL12;
245 break;
246 case R8A66597_PLATDATA_XTAL_24MHZ:
247 clock = XTAL24;
248 break;
249 case R8A66597_PLATDATA_XTAL_48MHZ:
250 clock = XTAL48;
251 break;
252 default:
253 printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
254 break;
255 }
256
257 return clock;
258}
259
260static inline u32 r8a66597_sudmac_read(struct r8a66597 *r8a66597,
261 unsigned long offset)
262{
263 return ioread32(r8a66597->sudmac_reg + offset);
264}
265
266static inline void r8a66597_sudmac_write(struct r8a66597 *r8a66597, u32 val,
267 unsigned long offset)
268{
269 iowrite32(val, r8a66597->sudmac_reg + offset);
270}
271
272#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
273#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
274#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
275
276#define enable_irq_ready(r8a66597, pipenum) \
277 enable_pipe_irq(r8a66597, pipenum, BRDYENB)
278#define disable_irq_ready(r8a66597, pipenum) \
279 disable_pipe_irq(r8a66597, pipenum, BRDYENB)
280#define enable_irq_empty(r8a66597, pipenum) \
281 enable_pipe_irq(r8a66597, pipenum, BEMPENB)
282#define disable_irq_empty(r8a66597, pipenum) \
283 disable_pipe_irq(r8a66597, pipenum, BEMPENB)
284#define enable_irq_nrdy(r8a66597, pipenum) \
285 enable_pipe_irq(r8a66597, pipenum, NRDYENB)
286#define disable_irq_nrdy(r8a66597, pipenum) \
287 disable_pipe_irq(r8a66597, pipenum, NRDYENB)
288
289#endif /* __R8A66597_H__ */
290
1/*
2 * R8A66597 UDC
3 *
4 * Copyright (C) 2007-2009 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 */
12
13#ifndef __R8A66597_H__
14#define __R8A66597_H__
15
16#ifdef CONFIG_HAVE_CLK
17#include <linux/clk.h>
18#endif
19
20#include <linux/usb/r8a66597.h>
21
22#define R8A66597_MAX_SAMPLING 10
23
24#define R8A66597_MAX_NUM_PIPE 8
25#define R8A66597_MAX_NUM_BULK 3
26#define R8A66597_MAX_NUM_ISOC 2
27#define R8A66597_MAX_NUM_INT 2
28
29#define R8A66597_BASE_PIPENUM_BULK 3
30#define R8A66597_BASE_PIPENUM_ISOC 1
31#define R8A66597_BASE_PIPENUM_INT 6
32
33#define R8A66597_BASE_BUFNUM 6
34#define R8A66597_MAX_BUFNUM 0x4F
35
36#define is_bulk_pipe(pipenum) \
37 ((pipenum >= R8A66597_BASE_PIPENUM_BULK) && \
38 (pipenum < (R8A66597_BASE_PIPENUM_BULK + R8A66597_MAX_NUM_BULK)))
39#define is_interrupt_pipe(pipenum) \
40 ((pipenum >= R8A66597_BASE_PIPENUM_INT) && \
41 (pipenum < (R8A66597_BASE_PIPENUM_INT + R8A66597_MAX_NUM_INT)))
42#define is_isoc_pipe(pipenum) \
43 ((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \
44 (pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC)))
45
46#define r8a66597_is_sudmac(r8a66597) (r8a66597->pdata->sudmac)
47struct r8a66597_pipe_info {
48 u16 pipe;
49 u16 epnum;
50 u16 maxpacket;
51 u16 type;
52 u16 interval;
53 u16 dir_in;
54};
55
56struct r8a66597_request {
57 struct usb_request req;
58 struct list_head queue;
59};
60
61struct r8a66597_ep {
62 struct usb_ep ep;
63 struct r8a66597 *r8a66597;
64 struct r8a66597_dma *dma;
65
66 struct list_head queue;
67 unsigned busy:1;
68 unsigned wedge:1;
69 unsigned internal_ccpl:1; /* use only control */
70
71 /* this member can able to after r8a66597_enable */
72 unsigned use_dma:1;
73 u16 pipenum;
74 u16 type;
75
76 /* register address */
77 unsigned char fifoaddr;
78 unsigned char fifosel;
79 unsigned char fifoctr;
80 unsigned char pipectr;
81 unsigned char pipetre;
82 unsigned char pipetrn;
83};
84
85struct r8a66597_dma {
86 unsigned used:1;
87 unsigned dir:1; /* 1 = IN(write), 0 = OUT(read) */
88};
89
90struct r8a66597 {
91 spinlock_t lock;
92 void __iomem *reg;
93 void __iomem *sudmac_reg;
94
95#ifdef CONFIG_HAVE_CLK
96 struct clk *clk;
97#endif
98 struct r8a66597_platdata *pdata;
99
100 struct usb_gadget gadget;
101 struct usb_gadget_driver *driver;
102
103 struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE];
104 struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE];
105 struct r8a66597_ep *epaddr2ep[16];
106 struct r8a66597_dma dma;
107
108 struct timer_list timer;
109 struct usb_request *ep0_req; /* for internal request */
110 u16 ep0_data; /* for internal request */
111 u16 old_vbus;
112 u16 scount;
113 u16 old_dvsq;
114 u16 device_status; /* for GET_STATUS */
115
116 /* pipe config */
117 unsigned char bulk;
118 unsigned char interrupt;
119 unsigned char isochronous;
120 unsigned char num_dma;
121
122 unsigned irq_sense_low:1;
123};
124
125#define gadget_to_r8a66597(_gadget) \
126 container_of(_gadget, struct r8a66597, gadget)
127#define r8a66597_to_gadget(r8a66597) (&r8a66597->gadget)
128#define r8a66597_to_dev(r8a66597) (r8a66597->gadget.dev.parent)
129
130static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
131{
132 return ioread16(r8a66597->reg + offset);
133}
134
135static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
136 unsigned long offset,
137 unsigned char *buf,
138 int len)
139{
140 void __iomem *fifoaddr = r8a66597->reg + offset;
141 unsigned int data = 0;
142 int i;
143
144 if (r8a66597->pdata->on_chip) {
145 /* 32-bit accesses for on_chip controllers */
146
147 /* aligned buf case */
148 if (len >= 4 && !((unsigned long)buf & 0x03)) {
149 ioread32_rep(fifoaddr, buf, len / 4);
150 buf += len & ~0x03;
151 len &= 0x03;
152 }
153
154 /* unaligned buf case */
155 for (i = 0; i < len; i++) {
156 if (!(i & 0x03))
157 data = ioread32(fifoaddr);
158
159 buf[i] = (data >> ((i & 0x03) * 8)) & 0xff;
160 }
161 } else {
162 /* 16-bit accesses for external controllers */
163
164 /* aligned buf case */
165 if (len >= 2 && !((unsigned long)buf & 0x01)) {
166 ioread16_rep(fifoaddr, buf, len / 2);
167 buf += len & ~0x01;
168 len &= 0x01;
169 }
170
171 /* unaligned buf case */
172 for (i = 0; i < len; i++) {
173 if (!(i & 0x01))
174 data = ioread16(fifoaddr);
175
176 buf[i] = (data >> ((i & 0x01) * 8)) & 0xff;
177 }
178 }
179}
180
181static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
182 unsigned long offset)
183{
184 iowrite16(val, r8a66597->reg + offset);
185}
186
187static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
188 u16 val, u16 pat, unsigned long offset)
189{
190 u16 tmp;
191 tmp = r8a66597_read(r8a66597, offset);
192 tmp = tmp & (~pat);
193 tmp = tmp | val;
194 r8a66597_write(r8a66597, tmp, offset);
195}
196
197#define r8a66597_bclr(r8a66597, val, offset) \
198 r8a66597_mdfy(r8a66597, 0, val, offset)
199#define r8a66597_bset(r8a66597, val, offset) \
200 r8a66597_mdfy(r8a66597, val, 0, offset)
201
202static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
203 struct r8a66597_ep *ep,
204 unsigned char *buf,
205 int len)
206{
207 void __iomem *fifoaddr = r8a66597->reg + ep->fifoaddr;
208 int adj = 0;
209 int i;
210
211 if (r8a66597->pdata->on_chip) {
212 /* 32-bit access only if buf is 32-bit aligned */
213 if (len >= 4 && !((unsigned long)buf & 0x03)) {
214 iowrite32_rep(fifoaddr, buf, len / 4);
215 buf += len & ~0x03;
216 len &= 0x03;
217 }
218 } else {
219 /* 16-bit access only if buf is 16-bit aligned */
220 if (len >= 2 && !((unsigned long)buf & 0x01)) {
221 iowrite16_rep(fifoaddr, buf, len / 2);
222 buf += len & ~0x01;
223 len &= 0x01;
224 }
225 }
226
227 /* adjust fifo address in the little endian case */
228 if (!(r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)) {
229 if (r8a66597->pdata->on_chip)
230 adj = 0x03; /* 32-bit wide */
231 else
232 adj = 0x01; /* 16-bit wide */
233 }
234
235 if (r8a66597->pdata->wr0_shorted_to_wr1)
236 r8a66597_bclr(r8a66597, MBW_16, ep->fifosel);
237 for (i = 0; i < len; i++)
238 iowrite8(buf[i], fifoaddr + adj - (i & adj));
239 if (r8a66597->pdata->wr0_shorted_to_wr1)
240 r8a66597_bclr(r8a66597, MBW_16, ep->fifosel);
241}
242
243static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
244{
245 u16 clock = 0;
246
247 switch (pdata->xtal) {
248 case R8A66597_PLATDATA_XTAL_12MHZ:
249 clock = XTAL12;
250 break;
251 case R8A66597_PLATDATA_XTAL_24MHZ:
252 clock = XTAL24;
253 break;
254 case R8A66597_PLATDATA_XTAL_48MHZ:
255 clock = XTAL48;
256 break;
257 default:
258 printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
259 break;
260 }
261
262 return clock;
263}
264
265static inline u32 r8a66597_sudmac_read(struct r8a66597 *r8a66597,
266 unsigned long offset)
267{
268 return ioread32(r8a66597->sudmac_reg + offset);
269}
270
271static inline void r8a66597_sudmac_write(struct r8a66597 *r8a66597, u32 val,
272 unsigned long offset)
273{
274 iowrite32(val, r8a66597->sudmac_reg + offset);
275}
276
277#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
278#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
279#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
280
281#define enable_irq_ready(r8a66597, pipenum) \
282 enable_pipe_irq(r8a66597, pipenum, BRDYENB)
283#define disable_irq_ready(r8a66597, pipenum) \
284 disable_pipe_irq(r8a66597, pipenum, BRDYENB)
285#define enable_irq_empty(r8a66597, pipenum) \
286 enable_pipe_irq(r8a66597, pipenum, BEMPENB)
287#define disable_irq_empty(r8a66597, pipenum) \
288 disable_pipe_irq(r8a66597, pipenum, BEMPENB)
289#define enable_irq_nrdy(r8a66597, pipenum) \
290 enable_pipe_irq(r8a66597, pipenum, NRDYENB)
291#define disable_irq_nrdy(r8a66597, pipenum) \
292 disable_pipe_irq(r8a66597, pipenum, NRDYENB)
293
294#endif /* __R8A66597_H__ */
295