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1/*
2 * Copyright (c) 2000-2013 LSI Corporation.
3 *
4 *
5 * Name: mpi2.h
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
10 *
11 * mpi2.h Version: 02.00.29
12 *
13 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
14 * prefix are for use only on MPI v2.5 products, and must not be used
15 * with MPI v2.0 products. Unless otherwise noted, names beginning with
16 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
17 *
18 * Version History
19 * ---------------
20 *
21 * Date Version Description
22 * -------- -------- ------------------------------------------------------
23 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
24 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
25 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
26 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
27 * Moved ReplyPostHostIndex register to offset 0x6C of the
28 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
29 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
30 * Added union of request descriptors.
31 * Added union of reply descriptors.
32 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
33 * Added define for MPI2_VERSION_02_00.
34 * Fixed the size of the FunctionDependent5 field in the
35 * MPI2_DEFAULT_REPLY structure.
36 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
37 * Removed the MPI-defined Fault Codes and extended the
38 * product specific codes up to 0xEFFF.
39 * Added a sixth key value for the WriteSequence register
40 * and changed the flush value to 0x0.
41 * Added message function codes for Diagnostic Buffer Post
42 * and Diagnsotic Release.
43 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
44 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
45 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
46 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
47 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
48 * Added #defines for marking a reply descriptor as unused.
49 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
50 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
51 * Moved LUN field defines from mpi2_init.h.
52 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
53 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
54 * In all request and reply descriptors, replaced VF_ID
55 * field with MSIxIndex field.
56 * Removed DevHandle field from
57 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
58 * bytes reserved.
59 * Added RAID Accelerator functionality.
60 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
61 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
62 * Added MSI-x index mask and shift for Reply Post Host
63 * Index register.
64 * Added function code for Host Based Discovery Action.
65 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
66 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
67 * Added defines for product-specific range of message
68 * function codes, 0xF0 to 0xFF.
69 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
70 * Added alternative defines for the SGE Direction bit.
71 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
72 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
73 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
74 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
75 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
76 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
77 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
78 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
80 * Incorporating additions for MPI v2.5.
81 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
82 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
83 * Added Hard Reset delay timings.
84 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
85 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
86 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
87 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
88 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
89 * --------------------------------------------------------------------------
90 */
91
92#ifndef MPI2_H
93#define MPI2_H
94
95/*****************************************************************************
96*
97* MPI Version Definitions
98*
99*****************************************************************************/
100
101#define MPI2_VERSION_MAJOR_MASK (0xFF00)
102#define MPI2_VERSION_MAJOR_SHIFT (8)
103#define MPI2_VERSION_MINOR_MASK (0x00FF)
104#define MPI2_VERSION_MINOR_SHIFT (0)
105
106/*major version for all MPI v2.x */
107#define MPI2_VERSION_MAJOR (0x02)
108
109/*minor version for MPI v2.0 compatible products */
110#define MPI2_VERSION_MINOR (0x00)
111#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
112 MPI2_VERSION_MINOR)
113#define MPI2_VERSION_02_00 (0x0200)
114
115/*minor version for MPI v2.5 compatible products */
116#define MPI25_VERSION_MINOR (0x05)
117#define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
118 MPI25_VERSION_MINOR)
119#define MPI2_VERSION_02_05 (0x0205)
120
121/*Unit and Dev versioning for this MPI header set */
122#define MPI2_HEADER_VERSION_UNIT (0x1D)
123#define MPI2_HEADER_VERSION_DEV (0x00)
124#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
125#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
126#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
127#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
128#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
129 MPI2_HEADER_VERSION_DEV)
130
131/*****************************************************************************
132*
133* IOC State Definitions
134*
135*****************************************************************************/
136
137#define MPI2_IOC_STATE_RESET (0x00000000)
138#define MPI2_IOC_STATE_READY (0x10000000)
139#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
140#define MPI2_IOC_STATE_FAULT (0x40000000)
141
142#define MPI2_IOC_STATE_MASK (0xF0000000)
143#define MPI2_IOC_STATE_SHIFT (28)
144
145/*Fault state range for prodcut specific codes */
146#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
147#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
148
149/*****************************************************************************
150*
151* System Interface Register Definitions
152*
153*****************************************************************************/
154
155typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
156 U32 Doorbell; /*0x00 */
157 U32 WriteSequence; /*0x04 */
158 U32 HostDiagnostic; /*0x08 */
159 U32 Reserved1; /*0x0C */
160 U32 DiagRWData; /*0x10 */
161 U32 DiagRWAddressLow; /*0x14 */
162 U32 DiagRWAddressHigh; /*0x18 */
163 U32 Reserved2[5]; /*0x1C */
164 U32 HostInterruptStatus; /*0x30 */
165 U32 HostInterruptMask; /*0x34 */
166 U32 DCRData; /*0x38 */
167 U32 DCRAddress; /*0x3C */
168 U32 Reserved3[2]; /*0x40 */
169 U32 ReplyFreeHostIndex; /*0x48 */
170 U32 Reserved4[8]; /*0x4C */
171 U32 ReplyPostHostIndex; /*0x6C */
172 U32 Reserved5; /*0x70 */
173 U32 HCBSize; /*0x74 */
174 U32 HCBAddressLow; /*0x78 */
175 U32 HCBAddressHigh; /*0x7C */
176 U32 Reserved6[16]; /*0x80 */
177 U32 RequestDescriptorPostLow; /*0xC0 */
178 U32 RequestDescriptorPostHigh; /*0xC4 */
179 U32 Reserved7[14]; /*0xC8 */
180} MPI2_SYSTEM_INTERFACE_REGS,
181 *PTR_MPI2_SYSTEM_INTERFACE_REGS,
182 Mpi2SystemInterfaceRegs_t,
183 *pMpi2SystemInterfaceRegs_t;
184
185/*
186 *Defines for working with the Doorbell register.
187 */
188#define MPI2_DOORBELL_OFFSET (0x00000000)
189
190/*IOC --> System values */
191#define MPI2_DOORBELL_USED (0x08000000)
192#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
193#define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
194#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
195#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
196
197/*System --> IOC values */
198#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
199#define MPI2_DOORBELL_FUNCTION_SHIFT (24)
200#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
201#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
202
203/*
204 *Defines for the WriteSequence register
205 */
206#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
207#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
208#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
209#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
210#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
211#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
212#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
213#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
214#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
215
216/*
217 *Defines for the HostDiagnostic register
218 */
219#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
220
221#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
222#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
223#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
224
225#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
226#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
227#define MPI2_DIAG_HCB_MODE (0x00000100)
228#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
229#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
230#define MPI2_DIAG_RESET_HISTORY (0x00000020)
231#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
232#define MPI2_DIAG_RESET_ADAPTER (0x00000004)
233#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
234
235/*
236 *Offsets for DiagRWData and address
237 */
238#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
239#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
240#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
241
242/*
243 *Defines for the HostInterruptStatus register
244 */
245#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
246#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
247#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
248#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
249#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
250#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
251#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
252
253/*
254 *Defines for the HostInterruptMask register
255 */
256#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
257#define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
258#define MPI2_HIM_REPLY_INT_MASK (0x00000008)
259#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
260#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
261#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
262
263/*
264 *Offsets for DCRData and address
265 */
266#define MPI2_DCR_DATA_OFFSET (0x00000038)
267#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
268
269/*
270 *Offset for the Reply Free Queue
271 */
272#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
273
274/*
275 *Defines for the Reply Descriptor Post Queue
276 */
277#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
278#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
279#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
280#define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
281#define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/
282
283
284/*
285 *Defines for the HCBSize and address
286 */
287#define MPI2_HCB_SIZE_OFFSET (0x00000074)
288#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
289#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
290
291#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
292#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
293
294/*
295 *Offsets for the Request Queue
296 */
297#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
298#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
299
300/*Hard Reset delay timings */
301#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
302#define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
303#define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
304
305/*****************************************************************************
306*
307* Message Descriptors
308*
309*****************************************************************************/
310
311/*Request Descriptors */
312
313/*Default Request Descriptor */
314typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
315 U8 RequestFlags; /*0x00 */
316 U8 MSIxIndex; /*0x01 */
317 U16 SMID; /*0x02 */
318 U16 LMID; /*0x04 */
319 U16 DescriptorTypeDependent; /*0x06 */
320} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
321 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
322 Mpi2DefaultRequestDescriptor_t,
323 *pMpi2DefaultRequestDescriptor_t;
324
325/*defines for the RequestFlags field */
326#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
327#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
328#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
329#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
330#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
331#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
332#define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
333
334#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
335
336/*High Priority Request Descriptor */
337typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
338 U8 RequestFlags; /*0x00 */
339 U8 MSIxIndex; /*0x01 */
340 U16 SMID; /*0x02 */
341 U16 LMID; /*0x04 */
342 U16 Reserved1; /*0x06 */
343} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
344 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
345 Mpi2HighPriorityRequestDescriptor_t,
346 *pMpi2HighPriorityRequestDescriptor_t;
347
348/*SCSI IO Request Descriptor */
349typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
350 U8 RequestFlags; /*0x00 */
351 U8 MSIxIndex; /*0x01 */
352 U16 SMID; /*0x02 */
353 U16 LMID; /*0x04 */
354 U16 DevHandle; /*0x06 */
355} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
356 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
357 Mpi2SCSIIORequestDescriptor_t,
358 *pMpi2SCSIIORequestDescriptor_t;
359
360/*SCSI Target Request Descriptor */
361typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
362 U8 RequestFlags; /*0x00 */
363 U8 MSIxIndex; /*0x01 */
364 U16 SMID; /*0x02 */
365 U16 LMID; /*0x04 */
366 U16 IoIndex; /*0x06 */
367} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
368 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
369 Mpi2SCSITargetRequestDescriptor_t,
370 *pMpi2SCSITargetRequestDescriptor_t;
371
372/*RAID Accelerator Request Descriptor */
373typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
374 U8 RequestFlags; /*0x00 */
375 U8 MSIxIndex; /*0x01 */
376 U16 SMID; /*0x02 */
377 U16 LMID; /*0x04 */
378 U16 Reserved; /*0x06 */
379} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
380 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
381 Mpi2RAIDAcceleratorRequestDescriptor_t,
382 *pMpi2RAIDAcceleratorRequestDescriptor_t;
383
384/*Fast Path SCSI IO Request Descriptor */
385typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
386 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
387 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
388 Mpi25FastPathSCSIIORequestDescriptor_t,
389 *pMpi25FastPathSCSIIORequestDescriptor_t;
390
391/*union of Request Descriptors */
392typedef union _MPI2_REQUEST_DESCRIPTOR_UNION {
393 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
394 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
395 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
396 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
397 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
398 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
399 U64 Words;
400} MPI2_REQUEST_DESCRIPTOR_UNION,
401 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
402 Mpi2RequestDescriptorUnion_t,
403 *pMpi2RequestDescriptorUnion_t;
404
405/*Reply Descriptors */
406
407/*Default Reply Descriptor */
408typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
409 U8 ReplyFlags; /*0x00 */
410 U8 MSIxIndex; /*0x01 */
411 U16 DescriptorTypeDependent1; /*0x02 */
412 U32 DescriptorTypeDependent2; /*0x04 */
413} MPI2_DEFAULT_REPLY_DESCRIPTOR,
414 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
415 Mpi2DefaultReplyDescriptor_t,
416 *pMpi2DefaultReplyDescriptor_t;
417
418/*defines for the ReplyFlags field */
419#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
420#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
421#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
422#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
423#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
424#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
425#define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
426#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
427
428/*values for marking a reply descriptor as unused */
429#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
430#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
431
432/*Address Reply Descriptor */
433typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
434 U8 ReplyFlags; /*0x00 */
435 U8 MSIxIndex; /*0x01 */
436 U16 SMID; /*0x02 */
437 U32 ReplyFrameAddress; /*0x04 */
438} MPI2_ADDRESS_REPLY_DESCRIPTOR,
439 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
440 Mpi2AddressReplyDescriptor_t,
441 *pMpi2AddressReplyDescriptor_t;
442
443#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
444
445/*SCSI IO Success Reply Descriptor */
446typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
447 U8 ReplyFlags; /*0x00 */
448 U8 MSIxIndex; /*0x01 */
449 U16 SMID; /*0x02 */
450 U16 TaskTag; /*0x04 */
451 U16 Reserved1; /*0x06 */
452} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
453 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
454 Mpi2SCSIIOSuccessReplyDescriptor_t,
455 *pMpi2SCSIIOSuccessReplyDescriptor_t;
456
457/*TargetAssist Success Reply Descriptor */
458typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
459 U8 ReplyFlags; /*0x00 */
460 U8 MSIxIndex; /*0x01 */
461 U16 SMID; /*0x02 */
462 U8 SequenceNumber; /*0x04 */
463 U8 Reserved1; /*0x05 */
464 U16 IoIndex; /*0x06 */
465} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
466 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
467 Mpi2TargetAssistSuccessReplyDescriptor_t,
468 *pMpi2TargetAssistSuccessReplyDescriptor_t;
469
470/*Target Command Buffer Reply Descriptor */
471typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
472 U8 ReplyFlags; /*0x00 */
473 U8 MSIxIndex; /*0x01 */
474 U8 VP_ID; /*0x02 */
475 U8 Flags; /*0x03 */
476 U16 InitiatorDevHandle; /*0x04 */
477 U16 IoIndex; /*0x06 */
478} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
479 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
480 Mpi2TargetCommandBufferReplyDescriptor_t,
481 *pMpi2TargetCommandBufferReplyDescriptor_t;
482
483/*defines for Flags field */
484#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
485
486/*RAID Accelerator Success Reply Descriptor */
487typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
488 U8 ReplyFlags; /*0x00 */
489 U8 MSIxIndex; /*0x01 */
490 U16 SMID; /*0x02 */
491 U32 Reserved; /*0x04 */
492} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
493 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
494 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
495 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
496
497/*Fast Path SCSI IO Success Reply Descriptor */
498typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
499 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
500 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
501 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
502 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
503
504/*union of Reply Descriptors */
505typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
506 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
507 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
508 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
509 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
510 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
511 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
512 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
513 U64 Words;
514} MPI2_REPLY_DESCRIPTORS_UNION,
515 *PTR_MPI2_REPLY_DESCRIPTORS_UNION,
516 Mpi2ReplyDescriptorsUnion_t,
517 *pMpi2ReplyDescriptorsUnion_t;
518
519/*****************************************************************************
520*
521* Message Functions
522*
523*****************************************************************************/
524
525#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00)
526#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
527#define MPI2_FUNCTION_IOC_INIT (0x02)
528#define MPI2_FUNCTION_IOC_FACTS (0x03)
529#define MPI2_FUNCTION_CONFIG (0x04)
530#define MPI2_FUNCTION_PORT_FACTS (0x05)
531#define MPI2_FUNCTION_PORT_ENABLE (0x06)
532#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07)
533#define MPI2_FUNCTION_EVENT_ACK (0x08)
534#define MPI2_FUNCTION_FW_DOWNLOAD (0x09)
535#define MPI2_FUNCTION_TARGET_ASSIST (0x0B)
536#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C)
537#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D)
538#define MPI2_FUNCTION_FW_UPLOAD (0x12)
539#define MPI2_FUNCTION_RAID_ACTION (0x15)
540#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16)
541#define MPI2_FUNCTION_TOOLBOX (0x17)
542#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18)
543#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A)
544#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B)
545#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C)
546#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D)
547#define MPI2_FUNCTION_DIAG_RELEASE (0x1E)
548#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24)
549#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25)
550#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C)
551#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
552#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
553#define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
554#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
555#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
556
557/*Doorbell functions */
558#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
559#define MPI2_FUNCTION_HANDSHAKE (0x42)
560
561/*****************************************************************************
562*
563* IOC Status Values
564*
565*****************************************************************************/
566
567/*mask for IOCStatus status value */
568#define MPI2_IOCSTATUS_MASK (0x7FFF)
569
570/****************************************************************************
571* Common IOCStatus values for all replies
572****************************************************************************/
573
574#define MPI2_IOCSTATUS_SUCCESS (0x0000)
575#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
576#define MPI2_IOCSTATUS_BUSY (0x0002)
577#define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
578#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
579#define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
580#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
581#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
582#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
583#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
584
585/****************************************************************************
586* Config IOCStatus values
587****************************************************************************/
588
589#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
590#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
591#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
592#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
593#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
594#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
595
596/****************************************************************************
597* SCSI IO Reply
598****************************************************************************/
599
600#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
601#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
602#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
603#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
604#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
605#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
606#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
607#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
608#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
609#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
610#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
611#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
612
613/****************************************************************************
614* For use by SCSI Initiator and SCSI Target end-to-end data protection
615****************************************************************************/
616
617#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
618#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
619#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
620
621/****************************************************************************
622* SCSI Target values
623****************************************************************************/
624
625#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
626#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
627#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
628#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
629#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
630#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
631#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
632#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
633#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
634#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
635
636/****************************************************************************
637* Serial Attached SCSI values
638****************************************************************************/
639
640#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
641#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
642
643/****************************************************************************
644* Diagnostic Buffer Post / Diagnostic Release values
645****************************************************************************/
646
647#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
648
649/****************************************************************************
650* RAID Accelerator values
651****************************************************************************/
652
653#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
654
655/****************************************************************************
656* IOCStatus flag to indicate that log info is available
657****************************************************************************/
658
659#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
660
661/****************************************************************************
662* IOCLogInfo Types
663****************************************************************************/
664
665#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
666#define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
667#define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
668#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
669#define MPI2_IOCLOGINFO_TYPE_FC (0x2)
670#define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
671#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
672#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
673
674/*****************************************************************************
675*
676* Standard Message Structures
677*
678*****************************************************************************/
679
680/****************************************************************************
681*Request Message Header for all request messages
682****************************************************************************/
683
684typedef struct _MPI2_REQUEST_HEADER {
685 U16 FunctionDependent1; /*0x00 */
686 U8 ChainOffset; /*0x02 */
687 U8 Function; /*0x03 */
688 U16 FunctionDependent2; /*0x04 */
689 U8 FunctionDependent3; /*0x06 */
690 U8 MsgFlags; /*0x07 */
691 U8 VP_ID; /*0x08 */
692 U8 VF_ID; /*0x09 */
693 U16 Reserved1; /*0x0A */
694} MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER,
695 MPI2RequestHeader_t, *pMPI2RequestHeader_t;
696
697/****************************************************************************
698* Default Reply
699****************************************************************************/
700
701typedef struct _MPI2_DEFAULT_REPLY {
702 U16 FunctionDependent1; /*0x00 */
703 U8 MsgLength; /*0x02 */
704 U8 Function; /*0x03 */
705 U16 FunctionDependent2; /*0x04 */
706 U8 FunctionDependent3; /*0x06 */
707 U8 MsgFlags; /*0x07 */
708 U8 VP_ID; /*0x08 */
709 U8 VF_ID; /*0x09 */
710 U16 Reserved1; /*0x0A */
711 U16 FunctionDependent5; /*0x0C */
712 U16 IOCStatus; /*0x0E */
713 U32 IOCLogInfo; /*0x10 */
714} MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY,
715 MPI2DefaultReply_t, *pMPI2DefaultReply_t;
716
717/*common version structure/union used in messages and configuration pages */
718
719typedef struct _MPI2_VERSION_STRUCT {
720 U8 Dev; /*0x00 */
721 U8 Unit; /*0x01 */
722 U8 Minor; /*0x02 */
723 U8 Major; /*0x03 */
724} MPI2_VERSION_STRUCT;
725
726typedef union _MPI2_VERSION_UNION {
727 MPI2_VERSION_STRUCT Struct;
728 U32 Word;
729} MPI2_VERSION_UNION;
730
731/*LUN field defines, common to many structures */
732#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
733#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
734#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
735#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
736#define MPI2_LUN_LEVEL_1_WORD (0xFF00)
737#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
738
739/*****************************************************************************
740*
741* Fusion-MPT MPI Scatter Gather Elements
742*
743*****************************************************************************/
744
745/****************************************************************************
746* MPI Simple Element structures
747****************************************************************************/
748
749typedef struct _MPI2_SGE_SIMPLE32 {
750 U32 FlagsLength;
751 U32 Address;
752} MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32,
753 Mpi2SGESimple32_t, *pMpi2SGESimple32_t;
754
755typedef struct _MPI2_SGE_SIMPLE64 {
756 U32 FlagsLength;
757 U64 Address;
758} MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64,
759 Mpi2SGESimple64_t, *pMpi2SGESimple64_t;
760
761typedef struct _MPI2_SGE_SIMPLE_UNION {
762 U32 FlagsLength;
763 union {
764 U32 Address32;
765 U64 Address64;
766 } u;
767} MPI2_SGE_SIMPLE_UNION,
768 *PTR_MPI2_SGE_SIMPLE_UNION,
769 Mpi2SGESimpleUnion_t,
770 *pMpi2SGESimpleUnion_t;
771
772/****************************************************************************
773* MPI Chain Element structures - for MPI v2.0 products only
774****************************************************************************/
775
776typedef struct _MPI2_SGE_CHAIN32 {
777 U16 Length;
778 U8 NextChainOffset;
779 U8 Flags;
780 U32 Address;
781} MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32,
782 Mpi2SGEChain32_t, *pMpi2SGEChain32_t;
783
784typedef struct _MPI2_SGE_CHAIN64 {
785 U16 Length;
786 U8 NextChainOffset;
787 U8 Flags;
788 U64 Address;
789} MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64,
790 Mpi2SGEChain64_t, *pMpi2SGEChain64_t;
791
792typedef struct _MPI2_SGE_CHAIN_UNION {
793 U16 Length;
794 U8 NextChainOffset;
795 U8 Flags;
796 union {
797 U32 Address32;
798 U64 Address64;
799 } u;
800} MPI2_SGE_CHAIN_UNION,
801 *PTR_MPI2_SGE_CHAIN_UNION,
802 Mpi2SGEChainUnion_t,
803 *pMpi2SGEChainUnion_t;
804
805/****************************************************************************
806* MPI Transaction Context Element structures - for MPI v2.0 products only
807****************************************************************************/
808
809typedef struct _MPI2_SGE_TRANSACTION32 {
810 U8 Reserved;
811 U8 ContextSize;
812 U8 DetailsLength;
813 U8 Flags;
814 U32 TransactionContext[1];
815 U32 TransactionDetails[1];
816} MPI2_SGE_TRANSACTION32,
817 *PTR_MPI2_SGE_TRANSACTION32,
818 Mpi2SGETransaction32_t,
819 *pMpi2SGETransaction32_t;
820
821typedef struct _MPI2_SGE_TRANSACTION64 {
822 U8 Reserved;
823 U8 ContextSize;
824 U8 DetailsLength;
825 U8 Flags;
826 U32 TransactionContext[2];
827 U32 TransactionDetails[1];
828} MPI2_SGE_TRANSACTION64,
829 *PTR_MPI2_SGE_TRANSACTION64,
830 Mpi2SGETransaction64_t,
831 *pMpi2SGETransaction64_t;
832
833typedef struct _MPI2_SGE_TRANSACTION96 {
834 U8 Reserved;
835 U8 ContextSize;
836 U8 DetailsLength;
837 U8 Flags;
838 U32 TransactionContext[3];
839 U32 TransactionDetails[1];
840} MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96,
841 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t;
842
843typedef struct _MPI2_SGE_TRANSACTION128 {
844 U8 Reserved;
845 U8 ContextSize;
846 U8 DetailsLength;
847 U8 Flags;
848 U32 TransactionContext[4];
849 U32 TransactionDetails[1];
850} MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128,
851 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128;
852
853typedef struct _MPI2_SGE_TRANSACTION_UNION {
854 U8 Reserved;
855 U8 ContextSize;
856 U8 DetailsLength;
857 U8 Flags;
858 union {
859 U32 TransactionContext32[1];
860 U32 TransactionContext64[2];
861 U32 TransactionContext96[3];
862 U32 TransactionContext128[4];
863 } u;
864 U32 TransactionDetails[1];
865} MPI2_SGE_TRANSACTION_UNION,
866 *PTR_MPI2_SGE_TRANSACTION_UNION,
867 Mpi2SGETransactionUnion_t,
868 *pMpi2SGETransactionUnion_t;
869
870/****************************************************************************
871* MPI SGE union for IO SGL's - for MPI v2.0 products only
872****************************************************************************/
873
874typedef struct _MPI2_MPI_SGE_IO_UNION {
875 union {
876 MPI2_SGE_SIMPLE_UNION Simple;
877 MPI2_SGE_CHAIN_UNION Chain;
878 } u;
879} MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION,
880 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t;
881
882/****************************************************************************
883* MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
884****************************************************************************/
885
886typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION {
887 union {
888 MPI2_SGE_SIMPLE_UNION Simple;
889 MPI2_SGE_TRANSACTION_UNION Transaction;
890 } u;
891} MPI2_SGE_TRANS_SIMPLE_UNION,
892 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
893 Mpi2SGETransSimpleUnion_t,
894 *pMpi2SGETransSimpleUnion_t;
895
896/****************************************************************************
897* All MPI SGE types union
898****************************************************************************/
899
900typedef struct _MPI2_MPI_SGE_UNION {
901 union {
902 MPI2_SGE_SIMPLE_UNION Simple;
903 MPI2_SGE_CHAIN_UNION Chain;
904 MPI2_SGE_TRANSACTION_UNION Transaction;
905 } u;
906} MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION,
907 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t;
908
909/****************************************************************************
910* MPI SGE field definition and masks
911****************************************************************************/
912
913/*Flags field bit definitions */
914
915#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
916#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
917#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
918#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
919#define MPI2_SGE_FLAGS_DIRECTION (0x04)
920#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
921#define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
922
923#define MPI2_SGE_FLAGS_SHIFT (24)
924
925#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
926#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
927
928/*Element Type */
929
930#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
931#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
932#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
933#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
934
935/*Address location */
936
937#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
938
939/*Direction */
940
941#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
942#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
943
944#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
945#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
946
947/*Address Size */
948
949#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
950#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
951
952/*Context Size */
953
954#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
955#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
956#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
957#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
958
959#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
960#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
961
962/****************************************************************************
963* MPI SGE operation Macros
964****************************************************************************/
965
966/*SIMPLE FlagsLength manipulations... */
967#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
968#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \
969 MPI2_SGE_FLAGS_SHIFT)
970#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
971#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
972
973#define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \
974 MPI2_SGE_LENGTH(l))
975
976#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
977#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
978#define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
979 MPI2_SGE_SET_FLAGS_LENGTH(f, l))
980
981/*CAUTION - The following are READ-MODIFY-WRITE! */
982#define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
983 MPI2_SGE_SET_FLAGS(f))
984#define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
985 MPI2_SGE_LENGTH(l))
986
987#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \
988 MPI2_SGE_CHAIN_OFFSET_SHIFT)
989
990/*****************************************************************************
991*
992* Fusion-MPT IEEE Scatter Gather Elements
993*
994*****************************************************************************/
995
996/****************************************************************************
997* IEEE Simple Element structures
998****************************************************************************/
999
1000/*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1001typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
1002 U32 Address;
1003 U32 FlagsLength;
1004} MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32,
1005 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t;
1006
1007typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
1008 U64 Address;
1009 U32 Length;
1010 U16 Reserved1;
1011 U8 Reserved2;
1012 U8 Flags;
1013} MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64,
1014 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t;
1015
1016typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
1017 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1018 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1019} MPI2_IEEE_SGE_SIMPLE_UNION,
1020 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1021 Mpi2IeeeSgeSimpleUnion_t,
1022 *pMpi2IeeeSgeSimpleUnion_t;
1023
1024/****************************************************************************
1025* IEEE Chain Element structures
1026****************************************************************************/
1027
1028/*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1029typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1030
1031/*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1032typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1033
1034typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
1035 MPI2_IEEE_SGE_CHAIN32 Chain32;
1036 MPI2_IEEE_SGE_CHAIN64 Chain64;
1037} MPI2_IEEE_SGE_CHAIN_UNION,
1038 *PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1039 Mpi2IeeeSgeChainUnion_t,
1040 *pMpi2IeeeSgeChainUnion_t;
1041
1042/*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 products only */
1043typedef struct _MPI25_IEEE_SGE_CHAIN64 {
1044 U64 Address;
1045 U32 Length;
1046 U16 Reserved1;
1047 U8 NextChainOffset;
1048 U8 Flags;
1049} MPI25_IEEE_SGE_CHAIN64,
1050 *PTR_MPI25_IEEE_SGE_CHAIN64,
1051 Mpi25IeeeSgeChain64_t,
1052 *pMpi25IeeeSgeChain64_t;
1053
1054/****************************************************************************
1055* All IEEE SGE types union
1056****************************************************************************/
1057
1058/*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1059typedef struct _MPI2_IEEE_SGE_UNION {
1060 union {
1061 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1062 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1063 } u;
1064} MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION,
1065 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t;
1066
1067/****************************************************************************
1068* IEEE SGE union for IO SGL's
1069****************************************************************************/
1070
1071typedef union _MPI25_SGE_IO_UNION {
1072 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1073 MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1074} MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION,
1075 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t;
1076
1077/****************************************************************************
1078* IEEE SGE field definitions and masks
1079****************************************************************************/
1080
1081/*Flags field bit definitions */
1082
1083#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1084#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1085
1086#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1087
1088#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1089
1090/*Element Type */
1091
1092#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1093#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1094
1095/*Data Location Address Space */
1096
1097#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1098#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1099#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1100#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1101#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1102#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1103#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1104 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR)
1105
1106/****************************************************************************
1107* IEEE SGE operation Macros
1108****************************************************************************/
1109
1110/*SIMPLE FlagsLength manipulations... */
1111#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1112#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \
1113 >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1114#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1115
1116#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\
1117 MPI2_IEEE32_SGE_LENGTH(l))
1118
1119#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \
1120 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1121#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \
1122 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1123#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1124 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l))
1125
1126/*CAUTION - The following are READ-MODIFY-WRITE! */
1127#define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1128 MPI2_IEEE32_SGE_SET_FLAGS(f))
1129#define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1130 MPI2_IEEE32_SGE_LENGTH(l))
1131
1132/*****************************************************************************
1133*
1134* Fusion-MPT MPI/IEEE Scatter Gather Unions
1135*
1136*****************************************************************************/
1137
1138typedef union _MPI2_SIMPLE_SGE_UNION {
1139 MPI2_SGE_SIMPLE_UNION MpiSimple;
1140 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1141} MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION,
1142 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t;
1143
1144typedef union _MPI2_SGE_IO_UNION {
1145 MPI2_SGE_SIMPLE_UNION MpiSimple;
1146 MPI2_SGE_CHAIN_UNION MpiChain;
1147 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1148 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1149} MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION,
1150 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t;
1151
1152/****************************************************************************
1153*
1154* Values for SGLFlags field, used in many request messages with an SGL
1155*
1156****************************************************************************/
1157
1158/*values for MPI SGL Data Location Address Space subfield */
1159#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1160#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1161#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1162#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1163#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1164/*values for SGL Type subfield */
1165#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1166#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1167#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1168#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1169
1170#endif