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1/*
2 * Renesas R0P7757LC0012RL Support.
3 *
4 * Copyright (C) 2009 - 2010 Renesas Solutions Corp.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/init.h>
12#include <linux/platform_device.h>
13#include <linux/gpio.h>
14#include <linux/irq.h>
15#include <linux/regulator/fixed.h>
16#include <linux/regulator/machine.h>
17#include <linux/spi/spi.h>
18#include <linux/spi/flash.h>
19#include <linux/io.h>
20#include <linux/mmc/host.h>
21#include <linux/mmc/sh_mmcif.h>
22#include <linux/mmc/sh_mobile_sdhi.h>
23#include <linux/sh_eth.h>
24#include <linux/sh_intc.h>
25#include <linux/usb/renesas_usbhs.h>
26#include <cpu/sh7757.h>
27#include <asm/heartbeat.h>
28
29static struct resource heartbeat_resource = {
30 .start = 0xffec005c, /* PUDR */
31 .end = 0xffec005c,
32 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
33};
34
35static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
36
37static struct heartbeat_data heartbeat_data = {
38 .bit_pos = heartbeat_bit_pos,
39 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
40 .flags = HEARTBEAT_INVERTED,
41};
42
43static struct platform_device heartbeat_device = {
44 .name = "heartbeat",
45 .id = -1,
46 .dev = {
47 .platform_data = &heartbeat_data,
48 },
49 .num_resources = 1,
50 .resource = &heartbeat_resource,
51};
52
53/* Fast Ethernet */
54#define GBECONT 0xffc10100
55#define GBECONT_RMII1 BIT(17)
56#define GBECONT_RMII0 BIT(16)
57static void sh7757_eth_set_mdio_gate(void *addr)
58{
59 if (((unsigned long)addr & 0x00000fff) < 0x0800)
60 writel(readl(GBECONT) | GBECONT_RMII0, GBECONT);
61 else
62 writel(readl(GBECONT) | GBECONT_RMII1, GBECONT);
63}
64
65static struct resource sh_eth0_resources[] = {
66 {
67 .start = 0xfef00000,
68 .end = 0xfef001ff,
69 .flags = IORESOURCE_MEM,
70 }, {
71 .start = evt2irq(0xc80),
72 .end = evt2irq(0xc80),
73 .flags = IORESOURCE_IRQ,
74 },
75};
76
77static struct sh_eth_plat_data sh7757_eth0_pdata = {
78 .phy = 1,
79 .edmac_endian = EDMAC_LITTLE_ENDIAN,
80 .set_mdio_gate = sh7757_eth_set_mdio_gate,
81};
82
83static struct platform_device sh7757_eth0_device = {
84 .name = "sh7757-ether",
85 .resource = sh_eth0_resources,
86 .id = 0,
87 .num_resources = ARRAY_SIZE(sh_eth0_resources),
88 .dev = {
89 .platform_data = &sh7757_eth0_pdata,
90 },
91};
92
93static struct resource sh_eth1_resources[] = {
94 {
95 .start = 0xfef00800,
96 .end = 0xfef009ff,
97 .flags = IORESOURCE_MEM,
98 }, {
99 .start = evt2irq(0xc80),
100 .end = evt2irq(0xc80),
101 .flags = IORESOURCE_IRQ,
102 },
103};
104
105static struct sh_eth_plat_data sh7757_eth1_pdata = {
106 .phy = 1,
107 .edmac_endian = EDMAC_LITTLE_ENDIAN,
108 .set_mdio_gate = sh7757_eth_set_mdio_gate,
109};
110
111static struct platform_device sh7757_eth1_device = {
112 .name = "sh7757-ether",
113 .resource = sh_eth1_resources,
114 .id = 1,
115 .num_resources = ARRAY_SIZE(sh_eth1_resources),
116 .dev = {
117 .platform_data = &sh7757_eth1_pdata,
118 },
119};
120
121static void sh7757_eth_giga_set_mdio_gate(void *addr)
122{
123 if (((unsigned long)addr & 0x00000fff) < 0x0800) {
124 gpio_set_value(GPIO_PTT4, 1);
125 writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT);
126 } else {
127 gpio_set_value(GPIO_PTT4, 0);
128 writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT);
129 }
130}
131
132static struct resource sh_eth_giga0_resources[] = {
133 {
134 .start = 0xfee00000,
135 .end = 0xfee007ff,
136 .flags = IORESOURCE_MEM,
137 }, {
138 /* TSU */
139 .start = 0xfee01800,
140 .end = 0xfee01fff,
141 .flags = IORESOURCE_MEM,
142 }, {
143 .start = evt2irq(0x2960),
144 .end = evt2irq(0x2960),
145 .flags = IORESOURCE_IRQ,
146 },
147};
148
149static struct sh_eth_plat_data sh7757_eth_giga0_pdata = {
150 .phy = 18,
151 .edmac_endian = EDMAC_LITTLE_ENDIAN,
152 .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
153 .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
154};
155
156static struct platform_device sh7757_eth_giga0_device = {
157 .name = "sh7757-gether",
158 .resource = sh_eth_giga0_resources,
159 .id = 2,
160 .num_resources = ARRAY_SIZE(sh_eth_giga0_resources),
161 .dev = {
162 .platform_data = &sh7757_eth_giga0_pdata,
163 },
164};
165
166static struct resource sh_eth_giga1_resources[] = {
167 {
168 .start = 0xfee00800,
169 .end = 0xfee00fff,
170 .flags = IORESOURCE_MEM,
171 }, {
172 /* TSU */
173 .start = 0xfee01800,
174 .end = 0xfee01fff,
175 .flags = IORESOURCE_MEM,
176 }, {
177 .start = evt2irq(0x2980),
178 .end = evt2irq(0x2980),
179 .flags = IORESOURCE_IRQ,
180 },
181};
182
183static struct sh_eth_plat_data sh7757_eth_giga1_pdata = {
184 .phy = 19,
185 .edmac_endian = EDMAC_LITTLE_ENDIAN,
186 .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
187 .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
188};
189
190static struct platform_device sh7757_eth_giga1_device = {
191 .name = "sh7757-gether",
192 .resource = sh_eth_giga1_resources,
193 .id = 3,
194 .num_resources = ARRAY_SIZE(sh_eth_giga1_resources),
195 .dev = {
196 .platform_data = &sh7757_eth_giga1_pdata,
197 },
198};
199
200/* Fixed 3.3V regulator to be used by SDHI0, MMCIF */
201static struct regulator_consumer_supply fixed3v3_power_consumers[] =
202{
203 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
204 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
205 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
206 REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
207};
208
209/* SH_MMCIF */
210static struct resource sh_mmcif_resources[] = {
211 [0] = {
212 .start = 0xffcb0000,
213 .end = 0xffcb00ff,
214 .flags = IORESOURCE_MEM,
215 },
216 [1] = {
217 .start = evt2irq(0x1c60),
218 .flags = IORESOURCE_IRQ,
219 },
220 [2] = {
221 .start = evt2irq(0x1c80),
222 .flags = IORESOURCE_IRQ,
223 },
224};
225
226static struct sh_mmcif_plat_data sh_mmcif_plat = {
227 .sup_pclk = 0x0f,
228 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
229 MMC_CAP_NONREMOVABLE,
230 .ocr = MMC_VDD_32_33 | MMC_VDD_33_34,
231 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
232 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
233};
234
235static struct platform_device sh_mmcif_device = {
236 .name = "sh_mmcif",
237 .id = 0,
238 .dev = {
239 .platform_data = &sh_mmcif_plat,
240 },
241 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
242 .resource = sh_mmcif_resources,
243};
244
245/* SDHI0 */
246static struct sh_mobile_sdhi_info sdhi_info = {
247 .dma_slave_tx = SHDMA_SLAVE_SDHI_TX,
248 .dma_slave_rx = SHDMA_SLAVE_SDHI_RX,
249 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
250};
251
252static struct resource sdhi_resources[] = {
253 [0] = {
254 .start = 0xffe50000,
255 .end = 0xffe500ff,
256 .flags = IORESOURCE_MEM,
257 },
258 [1] = {
259 .start = evt2irq(0x480),
260 .flags = IORESOURCE_IRQ,
261 },
262};
263
264static struct platform_device sdhi_device = {
265 .name = "sh_mobile_sdhi",
266 .num_resources = ARRAY_SIZE(sdhi_resources),
267 .resource = sdhi_resources,
268 .id = 0,
269 .dev = {
270 .platform_data = &sdhi_info,
271 },
272};
273
274static int usbhs0_get_id(struct platform_device *pdev)
275{
276 return USBHS_GADGET;
277}
278
279static struct renesas_usbhs_platform_info usb0_data = {
280 .platform_callback = {
281 .get_id = usbhs0_get_id,
282 },
283 .driver_param = {
284 .buswait_bwait = 5,
285 }
286};
287
288static struct resource usb0_resources[] = {
289 [0] = {
290 .start = 0xfe450000,
291 .end = 0xfe4501ff,
292 .flags = IORESOURCE_MEM,
293 },
294 [1] = {
295 .start = evt2irq(0x840),
296 .end = evt2irq(0x840),
297 .flags = IORESOURCE_IRQ,
298 },
299};
300
301static struct platform_device usb0_device = {
302 .name = "renesas_usbhs",
303 .id = 0,
304 .dev = {
305 .platform_data = &usb0_data,
306 },
307 .num_resources = ARRAY_SIZE(usb0_resources),
308 .resource = usb0_resources,
309};
310
311static struct platform_device *sh7757lcr_devices[] __initdata = {
312 &heartbeat_device,
313 &sh7757_eth0_device,
314 &sh7757_eth1_device,
315 &sh7757_eth_giga0_device,
316 &sh7757_eth_giga1_device,
317 &sh_mmcif_device,
318 &sdhi_device,
319 &usb0_device,
320};
321
322static struct flash_platform_data spi_flash_data = {
323 .name = "m25p80",
324 .type = "m25px64",
325};
326
327static struct spi_board_info spi_board_info[] = {
328 {
329 .modalias = "m25p80",
330 .max_speed_hz = 25000000,
331 .bus_num = 0,
332 .chip_select = 1,
333 .platform_data = &spi_flash_data,
334 },
335};
336
337static int __init sh7757lcr_devices_setup(void)
338{
339 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
340 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
341
342 /* RGMII (PTA) */
343 gpio_request(GPIO_FN_ET0_MDC, NULL);
344 gpio_request(GPIO_FN_ET0_MDIO, NULL);
345 gpio_request(GPIO_FN_ET1_MDC, NULL);
346 gpio_request(GPIO_FN_ET1_MDIO, NULL);
347
348 /* ONFI (PTB, PTZ) */
349 gpio_request(GPIO_FN_ON_NRE, NULL);
350 gpio_request(GPIO_FN_ON_NWE, NULL);
351 gpio_request(GPIO_FN_ON_NWP, NULL);
352 gpio_request(GPIO_FN_ON_NCE0, NULL);
353 gpio_request(GPIO_FN_ON_R_B0, NULL);
354 gpio_request(GPIO_FN_ON_ALE, NULL);
355 gpio_request(GPIO_FN_ON_CLE, NULL);
356
357 gpio_request(GPIO_FN_ON_DQ7, NULL);
358 gpio_request(GPIO_FN_ON_DQ6, NULL);
359 gpio_request(GPIO_FN_ON_DQ5, NULL);
360 gpio_request(GPIO_FN_ON_DQ4, NULL);
361 gpio_request(GPIO_FN_ON_DQ3, NULL);
362 gpio_request(GPIO_FN_ON_DQ2, NULL);
363 gpio_request(GPIO_FN_ON_DQ1, NULL);
364 gpio_request(GPIO_FN_ON_DQ0, NULL);
365
366 /* IRQ8 to 0 (PTB, PTC) */
367 gpio_request(GPIO_FN_IRQ8, NULL);
368 gpio_request(GPIO_FN_IRQ7, NULL);
369 gpio_request(GPIO_FN_IRQ6, NULL);
370 gpio_request(GPIO_FN_IRQ5, NULL);
371 gpio_request(GPIO_FN_IRQ4, NULL);
372 gpio_request(GPIO_FN_IRQ3, NULL);
373 gpio_request(GPIO_FN_IRQ2, NULL);
374 gpio_request(GPIO_FN_IRQ1, NULL);
375 gpio_request(GPIO_FN_IRQ0, NULL);
376
377 /* SPI0 (PTD) */
378 gpio_request(GPIO_FN_SP0_MOSI, NULL);
379 gpio_request(GPIO_FN_SP0_MISO, NULL);
380 gpio_request(GPIO_FN_SP0_SCK, NULL);
381 gpio_request(GPIO_FN_SP0_SCK_FB, NULL);
382 gpio_request(GPIO_FN_SP0_SS0, NULL);
383 gpio_request(GPIO_FN_SP0_SS1, NULL);
384 gpio_request(GPIO_FN_SP0_SS2, NULL);
385 gpio_request(GPIO_FN_SP0_SS3, NULL);
386
387 /* RMII 0/1 (PTE, PTF) */
388 gpio_request(GPIO_FN_RMII0_CRS_DV, NULL);
389 gpio_request(GPIO_FN_RMII0_TXD1, NULL);
390 gpio_request(GPIO_FN_RMII0_TXD0, NULL);
391 gpio_request(GPIO_FN_RMII0_TXEN, NULL);
392 gpio_request(GPIO_FN_RMII0_REFCLK, NULL);
393 gpio_request(GPIO_FN_RMII0_RXD1, NULL);
394 gpio_request(GPIO_FN_RMII0_RXD0, NULL);
395 gpio_request(GPIO_FN_RMII0_RX_ER, NULL);
396 gpio_request(GPIO_FN_RMII1_CRS_DV, NULL);
397 gpio_request(GPIO_FN_RMII1_TXD1, NULL);
398 gpio_request(GPIO_FN_RMII1_TXD0, NULL);
399 gpio_request(GPIO_FN_RMII1_TXEN, NULL);
400 gpio_request(GPIO_FN_RMII1_REFCLK, NULL);
401 gpio_request(GPIO_FN_RMII1_RXD1, NULL);
402 gpio_request(GPIO_FN_RMII1_RXD0, NULL);
403 gpio_request(GPIO_FN_RMII1_RX_ER, NULL);
404
405 /* eMMC (PTG) */
406 gpio_request(GPIO_FN_MMCCLK, NULL);
407 gpio_request(GPIO_FN_MMCCMD, NULL);
408 gpio_request(GPIO_FN_MMCDAT7, NULL);
409 gpio_request(GPIO_FN_MMCDAT6, NULL);
410 gpio_request(GPIO_FN_MMCDAT5, NULL);
411 gpio_request(GPIO_FN_MMCDAT4, NULL);
412 gpio_request(GPIO_FN_MMCDAT3, NULL);
413 gpio_request(GPIO_FN_MMCDAT2, NULL);
414 gpio_request(GPIO_FN_MMCDAT1, NULL);
415 gpio_request(GPIO_FN_MMCDAT0, NULL);
416
417 /* LPC (PTG, PTH, PTQ, PTU) */
418 gpio_request(GPIO_FN_SERIRQ, NULL);
419 gpio_request(GPIO_FN_LPCPD, NULL);
420 gpio_request(GPIO_FN_LDRQ, NULL);
421 gpio_request(GPIO_FN_WP, NULL);
422 gpio_request(GPIO_FN_FMS0, NULL);
423 gpio_request(GPIO_FN_LAD3, NULL);
424 gpio_request(GPIO_FN_LAD2, NULL);
425 gpio_request(GPIO_FN_LAD1, NULL);
426 gpio_request(GPIO_FN_LAD0, NULL);
427 gpio_request(GPIO_FN_LFRAME, NULL);
428 gpio_request(GPIO_FN_LRESET, NULL);
429 gpio_request(GPIO_FN_LCLK, NULL);
430 gpio_request(GPIO_FN_LGPIO7, NULL);
431 gpio_request(GPIO_FN_LGPIO6, NULL);
432 gpio_request(GPIO_FN_LGPIO5, NULL);
433 gpio_request(GPIO_FN_LGPIO4, NULL);
434
435 /* SPI1 (PTH) */
436 gpio_request(GPIO_FN_SP1_MOSI, NULL);
437 gpio_request(GPIO_FN_SP1_MISO, NULL);
438 gpio_request(GPIO_FN_SP1_SCK, NULL);
439 gpio_request(GPIO_FN_SP1_SCK_FB, NULL);
440 gpio_request(GPIO_FN_SP1_SS0, NULL);
441 gpio_request(GPIO_FN_SP1_SS1, NULL);
442
443 /* SDHI (PTI) */
444 gpio_request(GPIO_FN_SD_WP, NULL);
445 gpio_request(GPIO_FN_SD_CD, NULL);
446 gpio_request(GPIO_FN_SD_CLK, NULL);
447 gpio_request(GPIO_FN_SD_CMD, NULL);
448 gpio_request(GPIO_FN_SD_D3, NULL);
449 gpio_request(GPIO_FN_SD_D2, NULL);
450 gpio_request(GPIO_FN_SD_D1, NULL);
451 gpio_request(GPIO_FN_SD_D0, NULL);
452
453 /* SCIF3/4 (PTJ, PTW) */
454 gpio_request(GPIO_FN_RTS3, NULL);
455 gpio_request(GPIO_FN_CTS3, NULL);
456 gpio_request(GPIO_FN_TXD3, NULL);
457 gpio_request(GPIO_FN_RXD3, NULL);
458 gpio_request(GPIO_FN_RTS4, NULL);
459 gpio_request(GPIO_FN_RXD4, NULL);
460 gpio_request(GPIO_FN_TXD4, NULL);
461 gpio_request(GPIO_FN_CTS4, NULL);
462
463 /* SERMUX (PTK, PTL, PTO, PTV) */
464 gpio_request(GPIO_FN_COM2_TXD, NULL);
465 gpio_request(GPIO_FN_COM2_RXD, NULL);
466 gpio_request(GPIO_FN_COM2_RTS, NULL);
467 gpio_request(GPIO_FN_COM2_CTS, NULL);
468 gpio_request(GPIO_FN_COM2_DTR, NULL);
469 gpio_request(GPIO_FN_COM2_DSR, NULL);
470 gpio_request(GPIO_FN_COM2_DCD, NULL);
471 gpio_request(GPIO_FN_COM2_RI, NULL);
472 gpio_request(GPIO_FN_RAC_RXD, NULL);
473 gpio_request(GPIO_FN_RAC_RTS, NULL);
474 gpio_request(GPIO_FN_RAC_CTS, NULL);
475 gpio_request(GPIO_FN_RAC_DTR, NULL);
476 gpio_request(GPIO_FN_RAC_DSR, NULL);
477 gpio_request(GPIO_FN_RAC_DCD, NULL);
478 gpio_request(GPIO_FN_RAC_TXD, NULL);
479 gpio_request(GPIO_FN_COM1_TXD, NULL);
480 gpio_request(GPIO_FN_COM1_RXD, NULL);
481 gpio_request(GPIO_FN_COM1_RTS, NULL);
482 gpio_request(GPIO_FN_COM1_CTS, NULL);
483
484 writeb(0x10, 0xfe470000); /* SMR0: SerMux mode 0 */
485
486 /* IIC (PTM, PTR, PTS) */
487 gpio_request(GPIO_FN_SDA7, NULL);
488 gpio_request(GPIO_FN_SCL7, NULL);
489 gpio_request(GPIO_FN_SDA6, NULL);
490 gpio_request(GPIO_FN_SCL6, NULL);
491 gpio_request(GPIO_FN_SDA5, NULL);
492 gpio_request(GPIO_FN_SCL5, NULL);
493 gpio_request(GPIO_FN_SDA4, NULL);
494 gpio_request(GPIO_FN_SCL4, NULL);
495 gpio_request(GPIO_FN_SDA3, NULL);
496 gpio_request(GPIO_FN_SCL3, NULL);
497 gpio_request(GPIO_FN_SDA2, NULL);
498 gpio_request(GPIO_FN_SCL2, NULL);
499 gpio_request(GPIO_FN_SDA1, NULL);
500 gpio_request(GPIO_FN_SCL1, NULL);
501 gpio_request(GPIO_FN_SDA0, NULL);
502 gpio_request(GPIO_FN_SCL0, NULL);
503
504 /* USB (PTN) */
505 gpio_request(GPIO_FN_VBUS_EN, NULL);
506 gpio_request(GPIO_FN_VBUS_OC, NULL);
507
508 /* SGPIO1/0 (PTN, PTO) */
509 gpio_request(GPIO_FN_SGPIO1_CLK, NULL);
510 gpio_request(GPIO_FN_SGPIO1_LOAD, NULL);
511 gpio_request(GPIO_FN_SGPIO1_DI, NULL);
512 gpio_request(GPIO_FN_SGPIO1_DO, NULL);
513 gpio_request(GPIO_FN_SGPIO0_CLK, NULL);
514 gpio_request(GPIO_FN_SGPIO0_LOAD, NULL);
515 gpio_request(GPIO_FN_SGPIO0_DI, NULL);
516 gpio_request(GPIO_FN_SGPIO0_DO, NULL);
517
518 /* WDT (PTN) */
519 gpio_request(GPIO_FN_SUB_CLKIN, NULL);
520
521 /* System (PTT) */
522 gpio_request(GPIO_FN_STATUS1, NULL);
523 gpio_request(GPIO_FN_STATUS0, NULL);
524
525 /* PWMX (PTT) */
526 gpio_request(GPIO_FN_PWMX1, NULL);
527 gpio_request(GPIO_FN_PWMX0, NULL);
528
529 /* R-SPI (PTV) */
530 gpio_request(GPIO_FN_R_SPI_MOSI, NULL);
531 gpio_request(GPIO_FN_R_SPI_MISO, NULL);
532 gpio_request(GPIO_FN_R_SPI_RSPCK, NULL);
533 gpio_request(GPIO_FN_R_SPI_SSL0, NULL);
534 gpio_request(GPIO_FN_R_SPI_SSL1, NULL);
535
536 /* EVC (PTV, PTW) */
537 gpio_request(GPIO_FN_EVENT7, NULL);
538 gpio_request(GPIO_FN_EVENT6, NULL);
539 gpio_request(GPIO_FN_EVENT5, NULL);
540 gpio_request(GPIO_FN_EVENT4, NULL);
541 gpio_request(GPIO_FN_EVENT3, NULL);
542 gpio_request(GPIO_FN_EVENT2, NULL);
543 gpio_request(GPIO_FN_EVENT1, NULL);
544 gpio_request(GPIO_FN_EVENT0, NULL);
545
546 /* LED for heartbeat */
547 gpio_request(GPIO_PTU3, NULL);
548 gpio_direction_output(GPIO_PTU3, 1);
549 gpio_request(GPIO_PTU2, NULL);
550 gpio_direction_output(GPIO_PTU2, 1);
551 gpio_request(GPIO_PTU1, NULL);
552 gpio_direction_output(GPIO_PTU1, 1);
553 gpio_request(GPIO_PTU0, NULL);
554 gpio_direction_output(GPIO_PTU0, 1);
555
556 /* control for MDIO of Gigabit Ethernet */
557 gpio_request(GPIO_PTT4, NULL);
558 gpio_direction_output(GPIO_PTT4, 1);
559
560 /* control for eMMC */
561 gpio_request(GPIO_PTT7, NULL); /* eMMC_RST# */
562 gpio_direction_output(GPIO_PTT7, 0);
563 gpio_request(GPIO_PTT6, NULL); /* eMMC_INDEX# */
564 gpio_direction_output(GPIO_PTT6, 0);
565 gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */
566 gpio_direction_output(GPIO_PTT5, 1);
567
568 /* register SPI device information */
569 spi_register_board_info(spi_board_info,
570 ARRAY_SIZE(spi_board_info));
571
572 /* General platform */
573 return platform_add_devices(sh7757lcr_devices,
574 ARRAY_SIZE(sh7757lcr_devices));
575}
576arch_initcall(sh7757lcr_devices_setup);
577
578/* Initialize IRQ setting */
579void __init init_sh7757lcr_IRQ(void)
580{
581 plat_irq_setup_pins(IRQ_MODE_IRQ7654);
582 plat_irq_setup_pins(IRQ_MODE_IRQ3210);
583}
584
585/* Initialize the board */
586static void __init sh7757lcr_setup(char **cmdline_p)
587{
588 printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n");
589}
590
591static int sh7757lcr_mode_pins(void)
592{
593 int value = 0;
594
595 /* These are the factory default settings of S3 (Low active).
596 * If you change these dip switches then you will need to
597 * adjust the values below as well.
598 */
599 value |= MODE_PIN0; /* Clock Mode: 1 */
600
601 return value;
602}
603
604/* The Machine Vector */
605static struct sh_machine_vector mv_sh7757lcr __initmv = {
606 .mv_name = "SH7757LCR",
607 .mv_setup = sh7757lcr_setup,
608 .mv_init_irq = init_sh7757lcr_IRQ,
609 .mv_mode_pins = sh7757lcr_mode_pins,
610};
611
1/*
2 * Renesas R0P7757LC0012RL Support.
3 *
4 * Copyright (C) 2009 - 2010 Renesas Solutions Corp.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/init.h>
12#include <linux/platform_device.h>
13#include <linux/gpio.h>
14#include <linux/irq.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h>
17#include <linux/io.h>
18#include <linux/mmc/host.h>
19#include <linux/mmc/sh_mmcif.h>
20#include <linux/mmc/sh_mobile_sdhi.h>
21#include <linux/sh_eth.h>
22#include <linux/sh_intc.h>
23#include <linux/usb/renesas_usbhs.h>
24#include <cpu/sh7757.h>
25#include <asm/heartbeat.h>
26
27static struct resource heartbeat_resource = {
28 .start = 0xffec005c, /* PUDR */
29 .end = 0xffec005c,
30 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
31};
32
33static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
34
35static struct heartbeat_data heartbeat_data = {
36 .bit_pos = heartbeat_bit_pos,
37 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
38 .flags = HEARTBEAT_INVERTED,
39};
40
41static struct platform_device heartbeat_device = {
42 .name = "heartbeat",
43 .id = -1,
44 .dev = {
45 .platform_data = &heartbeat_data,
46 },
47 .num_resources = 1,
48 .resource = &heartbeat_resource,
49};
50
51/* Fast Ethernet */
52#define GBECONT 0xffc10100
53#define GBECONT_RMII1 BIT(17)
54#define GBECONT_RMII0 BIT(16)
55static void sh7757_eth_set_mdio_gate(void *addr)
56{
57 if (((unsigned long)addr & 0x00000fff) < 0x0800)
58 writel(readl(GBECONT) | GBECONT_RMII0, GBECONT);
59 else
60 writel(readl(GBECONT) | GBECONT_RMII1, GBECONT);
61}
62
63static struct resource sh_eth0_resources[] = {
64 {
65 .start = 0xfef00000,
66 .end = 0xfef001ff,
67 .flags = IORESOURCE_MEM,
68 }, {
69 .start = evt2irq(0xc80),
70 .end = evt2irq(0xc80),
71 .flags = IORESOURCE_IRQ,
72 },
73};
74
75static struct sh_eth_plat_data sh7757_eth0_pdata = {
76 .phy = 1,
77 .edmac_endian = EDMAC_LITTLE_ENDIAN,
78 .register_type = SH_ETH_REG_FAST_SH4,
79 .set_mdio_gate = sh7757_eth_set_mdio_gate,
80};
81
82static struct platform_device sh7757_eth0_device = {
83 .name = "sh-eth",
84 .resource = sh_eth0_resources,
85 .id = 0,
86 .num_resources = ARRAY_SIZE(sh_eth0_resources),
87 .dev = {
88 .platform_data = &sh7757_eth0_pdata,
89 },
90};
91
92static struct resource sh_eth1_resources[] = {
93 {
94 .start = 0xfef00800,
95 .end = 0xfef009ff,
96 .flags = IORESOURCE_MEM,
97 }, {
98 .start = evt2irq(0xc80),
99 .end = evt2irq(0xc80),
100 .flags = IORESOURCE_IRQ,
101 },
102};
103
104static struct sh_eth_plat_data sh7757_eth1_pdata = {
105 .phy = 1,
106 .edmac_endian = EDMAC_LITTLE_ENDIAN,
107 .register_type = SH_ETH_REG_FAST_SH4,
108 .set_mdio_gate = sh7757_eth_set_mdio_gate,
109};
110
111static struct platform_device sh7757_eth1_device = {
112 .name = "sh-eth",
113 .resource = sh_eth1_resources,
114 .id = 1,
115 .num_resources = ARRAY_SIZE(sh_eth1_resources),
116 .dev = {
117 .platform_data = &sh7757_eth1_pdata,
118 },
119};
120
121static void sh7757_eth_giga_set_mdio_gate(void *addr)
122{
123 if (((unsigned long)addr & 0x00000fff) < 0x0800) {
124 gpio_set_value(GPIO_PTT4, 1);
125 writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT);
126 } else {
127 gpio_set_value(GPIO_PTT4, 0);
128 writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT);
129 }
130}
131
132static struct resource sh_eth_giga0_resources[] = {
133 {
134 .start = 0xfee00000,
135 .end = 0xfee007ff,
136 .flags = IORESOURCE_MEM,
137 }, {
138 /* TSU */
139 .start = 0xfee01800,
140 .end = 0xfee01fff,
141 .flags = IORESOURCE_MEM,
142 }, {
143 .start = evt2irq(0x2960),
144 .end = evt2irq(0x2960),
145 .flags = IORESOURCE_IRQ,
146 },
147};
148
149static struct sh_eth_plat_data sh7757_eth_giga0_pdata = {
150 .phy = 18,
151 .edmac_endian = EDMAC_LITTLE_ENDIAN,
152 .register_type = SH_ETH_REG_GIGABIT,
153 .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
154 .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
155};
156
157static struct platform_device sh7757_eth_giga0_device = {
158 .name = "sh-eth",
159 .resource = sh_eth_giga0_resources,
160 .id = 2,
161 .num_resources = ARRAY_SIZE(sh_eth_giga0_resources),
162 .dev = {
163 .platform_data = &sh7757_eth_giga0_pdata,
164 },
165};
166
167static struct resource sh_eth_giga1_resources[] = {
168 {
169 .start = 0xfee00800,
170 .end = 0xfee00fff,
171 .flags = IORESOURCE_MEM,
172 }, {
173 /* TSU */
174 .start = 0xfee01800,
175 .end = 0xfee01fff,
176 .flags = IORESOURCE_MEM,
177 }, {
178 .start = evt2irq(0x2980),
179 .end = evt2irq(0x2980),
180 .flags = IORESOURCE_IRQ,
181 },
182};
183
184static struct sh_eth_plat_data sh7757_eth_giga1_pdata = {
185 .phy = 19,
186 .edmac_endian = EDMAC_LITTLE_ENDIAN,
187 .register_type = SH_ETH_REG_GIGABIT,
188 .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
189 .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
190};
191
192static struct platform_device sh7757_eth_giga1_device = {
193 .name = "sh-eth",
194 .resource = sh_eth_giga1_resources,
195 .id = 3,
196 .num_resources = ARRAY_SIZE(sh_eth_giga1_resources),
197 .dev = {
198 .platform_data = &sh7757_eth_giga1_pdata,
199 },
200};
201
202/* SH_MMCIF */
203static struct resource sh_mmcif_resources[] = {
204 [0] = {
205 .start = 0xffcb0000,
206 .end = 0xffcb00ff,
207 .flags = IORESOURCE_MEM,
208 },
209 [1] = {
210 .start = evt2irq(0x1c60),
211 .flags = IORESOURCE_IRQ,
212 },
213 [2] = {
214 .start = evt2irq(0x1c80),
215 .flags = IORESOURCE_IRQ,
216 },
217};
218
219static struct sh_mmcif_plat_data sh_mmcif_plat = {
220 .sup_pclk = 0x0f,
221 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
222 MMC_CAP_NONREMOVABLE,
223 .ocr = MMC_VDD_32_33 | MMC_VDD_33_34,
224 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
225 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
226};
227
228static struct platform_device sh_mmcif_device = {
229 .name = "sh_mmcif",
230 .id = 0,
231 .dev = {
232 .platform_data = &sh_mmcif_plat,
233 },
234 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
235 .resource = sh_mmcif_resources,
236};
237
238/* SDHI0 */
239static struct sh_mobile_sdhi_info sdhi_info = {
240 .dma_slave_tx = SHDMA_SLAVE_SDHI_TX,
241 .dma_slave_rx = SHDMA_SLAVE_SDHI_RX,
242 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
243};
244
245static struct resource sdhi_resources[] = {
246 [0] = {
247 .start = 0xffe50000,
248 .end = 0xffe501ff,
249 .flags = IORESOURCE_MEM,
250 },
251 [1] = {
252 .start = evt2irq(0x480),
253 .flags = IORESOURCE_IRQ,
254 },
255};
256
257static struct platform_device sdhi_device = {
258 .name = "sh_mobile_sdhi",
259 .num_resources = ARRAY_SIZE(sdhi_resources),
260 .resource = sdhi_resources,
261 .id = 0,
262 .dev = {
263 .platform_data = &sdhi_info,
264 },
265};
266
267static int usbhs0_get_id(struct platform_device *pdev)
268{
269 return USBHS_GADGET;
270}
271
272static struct renesas_usbhs_platform_info usb0_data = {
273 .platform_callback = {
274 .get_id = usbhs0_get_id,
275 },
276 .driver_param = {
277 .buswait_bwait = 5,
278 }
279};
280
281static struct resource usb0_resources[] = {
282 [0] = {
283 .start = 0xfe450000,
284 .end = 0xfe4501ff,
285 .flags = IORESOURCE_MEM,
286 },
287 [1] = {
288 .start = evt2irq(0x840),
289 .end = evt2irq(0x840),
290 .flags = IORESOURCE_IRQ,
291 },
292};
293
294static struct platform_device usb0_device = {
295 .name = "renesas_usbhs",
296 .id = 0,
297 .dev = {
298 .platform_data = &usb0_data,
299 },
300 .num_resources = ARRAY_SIZE(usb0_resources),
301 .resource = usb0_resources,
302};
303
304static struct platform_device *sh7757lcr_devices[] __initdata = {
305 &heartbeat_device,
306 &sh7757_eth0_device,
307 &sh7757_eth1_device,
308 &sh7757_eth_giga0_device,
309 &sh7757_eth_giga1_device,
310 &sh_mmcif_device,
311 &sdhi_device,
312 &usb0_device,
313};
314
315static struct flash_platform_data spi_flash_data = {
316 .name = "m25p80",
317 .type = "m25px64",
318};
319
320static struct spi_board_info spi_board_info[] = {
321 {
322 .modalias = "m25p80",
323 .max_speed_hz = 25000000,
324 .bus_num = 0,
325 .chip_select = 1,
326 .platform_data = &spi_flash_data,
327 },
328};
329
330static int __init sh7757lcr_devices_setup(void)
331{
332 /* RGMII (PTA) */
333 gpio_request(GPIO_FN_ET0_MDC, NULL);
334 gpio_request(GPIO_FN_ET0_MDIO, NULL);
335 gpio_request(GPIO_FN_ET1_MDC, NULL);
336 gpio_request(GPIO_FN_ET1_MDIO, NULL);
337
338 /* ONFI (PTB, PTZ) */
339 gpio_request(GPIO_FN_ON_NRE, NULL);
340 gpio_request(GPIO_FN_ON_NWE, NULL);
341 gpio_request(GPIO_FN_ON_NWP, NULL);
342 gpio_request(GPIO_FN_ON_NCE0, NULL);
343 gpio_request(GPIO_FN_ON_R_B0, NULL);
344 gpio_request(GPIO_FN_ON_ALE, NULL);
345 gpio_request(GPIO_FN_ON_CLE, NULL);
346
347 gpio_request(GPIO_FN_ON_DQ7, NULL);
348 gpio_request(GPIO_FN_ON_DQ6, NULL);
349 gpio_request(GPIO_FN_ON_DQ5, NULL);
350 gpio_request(GPIO_FN_ON_DQ4, NULL);
351 gpio_request(GPIO_FN_ON_DQ3, NULL);
352 gpio_request(GPIO_FN_ON_DQ2, NULL);
353 gpio_request(GPIO_FN_ON_DQ1, NULL);
354 gpio_request(GPIO_FN_ON_DQ0, NULL);
355
356 /* IRQ8 to 0 (PTB, PTC) */
357 gpio_request(GPIO_FN_IRQ8, NULL);
358 gpio_request(GPIO_FN_IRQ7, NULL);
359 gpio_request(GPIO_FN_IRQ6, NULL);
360 gpio_request(GPIO_FN_IRQ5, NULL);
361 gpio_request(GPIO_FN_IRQ4, NULL);
362 gpio_request(GPIO_FN_IRQ3, NULL);
363 gpio_request(GPIO_FN_IRQ2, NULL);
364 gpio_request(GPIO_FN_IRQ1, NULL);
365 gpio_request(GPIO_FN_IRQ0, NULL);
366
367 /* SPI0 (PTD) */
368 gpio_request(GPIO_FN_SP0_MOSI, NULL);
369 gpio_request(GPIO_FN_SP0_MISO, NULL);
370 gpio_request(GPIO_FN_SP0_SCK, NULL);
371 gpio_request(GPIO_FN_SP0_SCK_FB, NULL);
372 gpio_request(GPIO_FN_SP0_SS0, NULL);
373 gpio_request(GPIO_FN_SP0_SS1, NULL);
374 gpio_request(GPIO_FN_SP0_SS2, NULL);
375 gpio_request(GPIO_FN_SP0_SS3, NULL);
376
377 /* RMII 0/1 (PTE, PTF) */
378 gpio_request(GPIO_FN_RMII0_CRS_DV, NULL);
379 gpio_request(GPIO_FN_RMII0_TXD1, NULL);
380 gpio_request(GPIO_FN_RMII0_TXD0, NULL);
381 gpio_request(GPIO_FN_RMII0_TXEN, NULL);
382 gpio_request(GPIO_FN_RMII0_REFCLK, NULL);
383 gpio_request(GPIO_FN_RMII0_RXD1, NULL);
384 gpio_request(GPIO_FN_RMII0_RXD0, NULL);
385 gpio_request(GPIO_FN_RMII0_RX_ER, NULL);
386 gpio_request(GPIO_FN_RMII1_CRS_DV, NULL);
387 gpio_request(GPIO_FN_RMII1_TXD1, NULL);
388 gpio_request(GPIO_FN_RMII1_TXD0, NULL);
389 gpio_request(GPIO_FN_RMII1_TXEN, NULL);
390 gpio_request(GPIO_FN_RMII1_REFCLK, NULL);
391 gpio_request(GPIO_FN_RMII1_RXD1, NULL);
392 gpio_request(GPIO_FN_RMII1_RXD0, NULL);
393 gpio_request(GPIO_FN_RMII1_RX_ER, NULL);
394
395 /* eMMC (PTG) */
396 gpio_request(GPIO_FN_MMCCLK, NULL);
397 gpio_request(GPIO_FN_MMCCMD, NULL);
398 gpio_request(GPIO_FN_MMCDAT7, NULL);
399 gpio_request(GPIO_FN_MMCDAT6, NULL);
400 gpio_request(GPIO_FN_MMCDAT5, NULL);
401 gpio_request(GPIO_FN_MMCDAT4, NULL);
402 gpio_request(GPIO_FN_MMCDAT3, NULL);
403 gpio_request(GPIO_FN_MMCDAT2, NULL);
404 gpio_request(GPIO_FN_MMCDAT1, NULL);
405 gpio_request(GPIO_FN_MMCDAT0, NULL);
406
407 /* LPC (PTG, PTH, PTQ, PTU) */
408 gpio_request(GPIO_FN_SERIRQ, NULL);
409 gpio_request(GPIO_FN_LPCPD, NULL);
410 gpio_request(GPIO_FN_LDRQ, NULL);
411 gpio_request(GPIO_FN_WP, NULL);
412 gpio_request(GPIO_FN_FMS0, NULL);
413 gpio_request(GPIO_FN_LAD3, NULL);
414 gpio_request(GPIO_FN_LAD2, NULL);
415 gpio_request(GPIO_FN_LAD1, NULL);
416 gpio_request(GPIO_FN_LAD0, NULL);
417 gpio_request(GPIO_FN_LFRAME, NULL);
418 gpio_request(GPIO_FN_LRESET, NULL);
419 gpio_request(GPIO_FN_LCLK, NULL);
420 gpio_request(GPIO_FN_LGPIO7, NULL);
421 gpio_request(GPIO_FN_LGPIO6, NULL);
422 gpio_request(GPIO_FN_LGPIO5, NULL);
423 gpio_request(GPIO_FN_LGPIO4, NULL);
424
425 /* SPI1 (PTH) */
426 gpio_request(GPIO_FN_SP1_MOSI, NULL);
427 gpio_request(GPIO_FN_SP1_MISO, NULL);
428 gpio_request(GPIO_FN_SP1_SCK, NULL);
429 gpio_request(GPIO_FN_SP1_SCK_FB, NULL);
430 gpio_request(GPIO_FN_SP1_SS0, NULL);
431 gpio_request(GPIO_FN_SP1_SS1, NULL);
432
433 /* SDHI (PTI) */
434 gpio_request(GPIO_FN_SD_WP, NULL);
435 gpio_request(GPIO_FN_SD_CD, NULL);
436 gpio_request(GPIO_FN_SD_CLK, NULL);
437 gpio_request(GPIO_FN_SD_CMD, NULL);
438 gpio_request(GPIO_FN_SD_D3, NULL);
439 gpio_request(GPIO_FN_SD_D2, NULL);
440 gpio_request(GPIO_FN_SD_D1, NULL);
441 gpio_request(GPIO_FN_SD_D0, NULL);
442
443 /* SCIF3/4 (PTJ, PTW) */
444 gpio_request(GPIO_FN_RTS3, NULL);
445 gpio_request(GPIO_FN_CTS3, NULL);
446 gpio_request(GPIO_FN_TXD3, NULL);
447 gpio_request(GPIO_FN_RXD3, NULL);
448 gpio_request(GPIO_FN_RTS4, NULL);
449 gpio_request(GPIO_FN_RXD4, NULL);
450 gpio_request(GPIO_FN_TXD4, NULL);
451 gpio_request(GPIO_FN_CTS4, NULL);
452
453 /* SERMUX (PTK, PTL, PTO, PTV) */
454 gpio_request(GPIO_FN_COM2_TXD, NULL);
455 gpio_request(GPIO_FN_COM2_RXD, NULL);
456 gpio_request(GPIO_FN_COM2_RTS, NULL);
457 gpio_request(GPIO_FN_COM2_CTS, NULL);
458 gpio_request(GPIO_FN_COM2_DTR, NULL);
459 gpio_request(GPIO_FN_COM2_DSR, NULL);
460 gpio_request(GPIO_FN_COM2_DCD, NULL);
461 gpio_request(GPIO_FN_COM2_RI, NULL);
462 gpio_request(GPIO_FN_RAC_RXD, NULL);
463 gpio_request(GPIO_FN_RAC_RTS, NULL);
464 gpio_request(GPIO_FN_RAC_CTS, NULL);
465 gpio_request(GPIO_FN_RAC_DTR, NULL);
466 gpio_request(GPIO_FN_RAC_DSR, NULL);
467 gpio_request(GPIO_FN_RAC_DCD, NULL);
468 gpio_request(GPIO_FN_RAC_TXD, NULL);
469 gpio_request(GPIO_FN_COM1_TXD, NULL);
470 gpio_request(GPIO_FN_COM1_RXD, NULL);
471 gpio_request(GPIO_FN_COM1_RTS, NULL);
472 gpio_request(GPIO_FN_COM1_CTS, NULL);
473
474 writeb(0x10, 0xfe470000); /* SMR0: SerMux mode 0 */
475
476 /* IIC (PTM, PTR, PTS) */
477 gpio_request(GPIO_FN_SDA7, NULL);
478 gpio_request(GPIO_FN_SCL7, NULL);
479 gpio_request(GPIO_FN_SDA6, NULL);
480 gpio_request(GPIO_FN_SCL6, NULL);
481 gpio_request(GPIO_FN_SDA5, NULL);
482 gpio_request(GPIO_FN_SCL5, NULL);
483 gpio_request(GPIO_FN_SDA4, NULL);
484 gpio_request(GPIO_FN_SCL4, NULL);
485 gpio_request(GPIO_FN_SDA3, NULL);
486 gpio_request(GPIO_FN_SCL3, NULL);
487 gpio_request(GPIO_FN_SDA2, NULL);
488 gpio_request(GPIO_FN_SCL2, NULL);
489 gpio_request(GPIO_FN_SDA1, NULL);
490 gpio_request(GPIO_FN_SCL1, NULL);
491 gpio_request(GPIO_FN_SDA0, NULL);
492 gpio_request(GPIO_FN_SCL0, NULL);
493
494 /* USB (PTN) */
495 gpio_request(GPIO_FN_VBUS_EN, NULL);
496 gpio_request(GPIO_FN_VBUS_OC, NULL);
497
498 /* SGPIO1/0 (PTN, PTO) */
499 gpio_request(GPIO_FN_SGPIO1_CLK, NULL);
500 gpio_request(GPIO_FN_SGPIO1_LOAD, NULL);
501 gpio_request(GPIO_FN_SGPIO1_DI, NULL);
502 gpio_request(GPIO_FN_SGPIO1_DO, NULL);
503 gpio_request(GPIO_FN_SGPIO0_CLK, NULL);
504 gpio_request(GPIO_FN_SGPIO0_LOAD, NULL);
505 gpio_request(GPIO_FN_SGPIO0_DI, NULL);
506 gpio_request(GPIO_FN_SGPIO0_DO, NULL);
507
508 /* WDT (PTN) */
509 gpio_request(GPIO_FN_SUB_CLKIN, NULL);
510
511 /* System (PTT) */
512 gpio_request(GPIO_FN_STATUS1, NULL);
513 gpio_request(GPIO_FN_STATUS0, NULL);
514
515 /* PWMX (PTT) */
516 gpio_request(GPIO_FN_PWMX1, NULL);
517 gpio_request(GPIO_FN_PWMX0, NULL);
518
519 /* R-SPI (PTV) */
520 gpio_request(GPIO_FN_R_SPI_MOSI, NULL);
521 gpio_request(GPIO_FN_R_SPI_MISO, NULL);
522 gpio_request(GPIO_FN_R_SPI_RSPCK, NULL);
523 gpio_request(GPIO_FN_R_SPI_SSL0, NULL);
524 gpio_request(GPIO_FN_R_SPI_SSL1, NULL);
525
526 /* EVC (PTV, PTW) */
527 gpio_request(GPIO_FN_EVENT7, NULL);
528 gpio_request(GPIO_FN_EVENT6, NULL);
529 gpio_request(GPIO_FN_EVENT5, NULL);
530 gpio_request(GPIO_FN_EVENT4, NULL);
531 gpio_request(GPIO_FN_EVENT3, NULL);
532 gpio_request(GPIO_FN_EVENT2, NULL);
533 gpio_request(GPIO_FN_EVENT1, NULL);
534 gpio_request(GPIO_FN_EVENT0, NULL);
535
536 /* LED for heartbeat */
537 gpio_request(GPIO_PTU3, NULL);
538 gpio_direction_output(GPIO_PTU3, 1);
539 gpio_request(GPIO_PTU2, NULL);
540 gpio_direction_output(GPIO_PTU2, 1);
541 gpio_request(GPIO_PTU1, NULL);
542 gpio_direction_output(GPIO_PTU1, 1);
543 gpio_request(GPIO_PTU0, NULL);
544 gpio_direction_output(GPIO_PTU0, 1);
545
546 /* control for MDIO of Gigabit Ethernet */
547 gpio_request(GPIO_PTT4, NULL);
548 gpio_direction_output(GPIO_PTT4, 1);
549
550 /* control for eMMC */
551 gpio_request(GPIO_PTT7, NULL); /* eMMC_RST# */
552 gpio_direction_output(GPIO_PTT7, 0);
553 gpio_request(GPIO_PTT6, NULL); /* eMMC_INDEX# */
554 gpio_direction_output(GPIO_PTT6, 0);
555 gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */
556 gpio_direction_output(GPIO_PTT5, 1);
557
558 /* register SPI device information */
559 spi_register_board_info(spi_board_info,
560 ARRAY_SIZE(spi_board_info));
561
562 /* General platform */
563 return platform_add_devices(sh7757lcr_devices,
564 ARRAY_SIZE(sh7757lcr_devices));
565}
566arch_initcall(sh7757lcr_devices_setup);
567
568/* Initialize IRQ setting */
569void __init init_sh7757lcr_IRQ(void)
570{
571 plat_irq_setup_pins(IRQ_MODE_IRQ7654);
572 plat_irq_setup_pins(IRQ_MODE_IRQ3210);
573}
574
575/* Initialize the board */
576static void __init sh7757lcr_setup(char **cmdline_p)
577{
578 printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n");
579}
580
581static int sh7757lcr_mode_pins(void)
582{
583 int value = 0;
584
585 /* These are the factory default settings of S3 (Low active).
586 * If you change these dip switches then you will need to
587 * adjust the values below as well.
588 */
589 value |= MODE_PIN0; /* Clock Mode: 1 */
590
591 return value;
592}
593
594/* The Machine Vector */
595static struct sh_machine_vector mv_sh7757lcr __initmv = {
596 .mv_name = "SH7757LCR",
597 .mv_setup = sh7757lcr_setup,
598 .mv_init_irq = init_sh7757lcr_IRQ,
599 .mv_mode_pins = sh7757lcr_mode_pins,
600};
601