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1/*
2 * linux/arch/arm/mach-omap1/timer32k.c
3 *
4 * OMAP 32K Timer
5 *
6 * Copyright (C) 2004 - 2005 Nokia Corporation
7 * Partial timer rewrite and additional dynamic tick timer support by
8 * Tony Lindgen <tony@atomide.com> and
9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 * OMAP Dual-mode timer framework support by Timo Teras
11 *
12 * MPU timer code based on the older MPU timer code for OMAP
13 * Copyright (C) 2000 RidgeRun, Inc.
14 * Author: Greg Lonnon <glonnon@ridgerun.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */
36
37#include <linux/kernel.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/sched.h>
42#include <linux/spinlock.h>
43#include <linux/err.h>
44#include <linux/clk.h>
45#include <linux/clocksource.h>
46#include <linux/clockchips.h>
47#include <linux/io.h>
48
49#include <asm/irq.h>
50#include <asm/mach/irq.h>
51#include <asm/mach/time.h>
52
53#include <plat/counter-32k.h>
54
55#include <mach/hardware.h>
56
57#include "common.h"
58
59/*
60 * ---------------------------------------------------------------------------
61 * 32KHz OS timer
62 *
63 * This currently works only on 16xx, as 1510 does not have the continuous
64 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
65 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
66 * on 1510 would be possible, but the timer would not be as accurate as
67 * with the 32KHz synchronized timer.
68 * ---------------------------------------------------------------------------
69 */
70
71/* 16xx specific defines */
72#define OMAP1_32K_TIMER_BASE 0xfffb9000
73#define OMAP1_32KSYNC_TIMER_BASE 0xfffbc400
74#define OMAP1_32K_TIMER_CR 0x08
75#define OMAP1_32K_TIMER_TVR 0x00
76#define OMAP1_32K_TIMER_TCR 0x04
77
78#define OMAP_32K_TICKS_PER_SEC (32768)
79
80/*
81 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
82 * so with HZ = 128, TVR = 255.
83 */
84#define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
85
86#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
87 (((nr_jiffies) * (clock_rate)) / HZ)
88
89static inline void omap_32k_timer_write(int val, int reg)
90{
91 omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
92}
93
94static inline unsigned long omap_32k_timer_read(int reg)
95{
96 return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
97}
98
99static inline void omap_32k_timer_start(unsigned long load_val)
100{
101 if (!load_val)
102 load_val = 1;
103 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
104 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
105}
106
107static inline void omap_32k_timer_stop(void)
108{
109 omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
110}
111
112#define omap_32k_timer_ack_irq()
113
114static int omap_32k_timer_set_next_event(unsigned long delta,
115 struct clock_event_device *dev)
116{
117 omap_32k_timer_start(delta);
118
119 return 0;
120}
121
122static void omap_32k_timer_set_mode(enum clock_event_mode mode,
123 struct clock_event_device *evt)
124{
125 omap_32k_timer_stop();
126
127 switch (mode) {
128 case CLOCK_EVT_MODE_PERIODIC:
129 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
130 break;
131 case CLOCK_EVT_MODE_ONESHOT:
132 case CLOCK_EVT_MODE_UNUSED:
133 case CLOCK_EVT_MODE_SHUTDOWN:
134 break;
135 case CLOCK_EVT_MODE_RESUME:
136 break;
137 }
138}
139
140static struct clock_event_device clockevent_32k_timer = {
141 .name = "32k-timer",
142 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
143 .set_next_event = omap_32k_timer_set_next_event,
144 .set_mode = omap_32k_timer_set_mode,
145};
146
147static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
148{
149 struct clock_event_device *evt = &clockevent_32k_timer;
150 omap_32k_timer_ack_irq();
151
152 evt->event_handler(evt);
153
154 return IRQ_HANDLED;
155}
156
157static struct irqaction omap_32k_timer_irq = {
158 .name = "32KHz timer",
159 .flags = IRQF_TIMER | IRQF_IRQPOLL,
160 .handler = omap_32k_timer_interrupt,
161};
162
163static __init void omap_init_32k_timer(void)
164{
165 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
166
167 clockevent_32k_timer.cpumask = cpumask_of(0);
168 clockevents_config_and_register(&clockevent_32k_timer,
169 OMAP_32K_TICKS_PER_SEC, 1, 0xfffffffe);
170}
171
172/*
173 * ---------------------------------------------------------------------------
174 * Timer initialization
175 * ---------------------------------------------------------------------------
176 */
177int __init omap_32k_timer_init(void)
178{
179 int ret = -ENODEV;
180
181 if (cpu_is_omap16xx()) {
182 void __iomem *base;
183 struct clk *sync32k_ick;
184
185 base = ioremap(OMAP1_32KSYNC_TIMER_BASE, SZ_1K);
186 if (!base) {
187 pr_err("32k_counter: failed to map base addr\n");
188 return -ENODEV;
189 }
190
191 sync32k_ick = clk_get(NULL, "omap_32ksync_ick");
192 if (!IS_ERR(sync32k_ick))
193 clk_enable(sync32k_ick);
194
195 ret = omap_init_clocksource_32k(base);
196 }
197
198 if (!ret)
199 omap_init_32k_timer();
200
201 return ret;
202}
1/*
2 * linux/arch/arm/mach-omap1/timer32k.c
3 *
4 * OMAP 32K Timer
5 *
6 * Copyright (C) 2004 - 2005 Nokia Corporation
7 * Partial timer rewrite and additional dynamic tick timer support by
8 * Tony Lindgen <tony@atomide.com> and
9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 * OMAP Dual-mode timer framework support by Timo Teras
11 *
12 * MPU timer code based on the older MPU timer code for OMAP
13 * Copyright (C) 2000 RidgeRun, Inc.
14 * Author: Greg Lonnon <glonnon@ridgerun.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * You should have received a copy of the GNU General Public License along
33 * with this program; if not, write to the Free Software Foundation, Inc.,
34 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 */
36
37#include <linux/kernel.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/sched.h>
42#include <linux/spinlock.h>
43#include <linux/err.h>
44#include <linux/clk.h>
45#include <linux/clocksource.h>
46#include <linux/clockchips.h>
47#include <linux/io.h>
48
49#include <asm/leds.h>
50#include <asm/irq.h>
51#include <asm/mach/irq.h>
52#include <asm/mach/time.h>
53
54#include <plat/dmtimer.h>
55
56#include <mach/hardware.h>
57
58#include "common.h"
59
60/*
61 * ---------------------------------------------------------------------------
62 * 32KHz OS timer
63 *
64 * This currently works only on 16xx, as 1510 does not have the continuous
65 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
66 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
67 * on 1510 would be possible, but the timer would not be as accurate as
68 * with the 32KHz synchronized timer.
69 * ---------------------------------------------------------------------------
70 */
71
72/* 16xx specific defines */
73#define OMAP1_32K_TIMER_BASE 0xfffb9000
74#define OMAP1_32KSYNC_TIMER_BASE 0xfffbc400
75#define OMAP1_32K_TIMER_CR 0x08
76#define OMAP1_32K_TIMER_TVR 0x00
77#define OMAP1_32K_TIMER_TCR 0x04
78
79#define OMAP_32K_TICKS_PER_SEC (32768)
80
81/*
82 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
83 * so with HZ = 128, TVR = 255.
84 */
85#define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
86
87#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
88 (((nr_jiffies) * (clock_rate)) / HZ)
89
90static inline void omap_32k_timer_write(int val, int reg)
91{
92 omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
93}
94
95static inline unsigned long omap_32k_timer_read(int reg)
96{
97 return omap_readl(OMAP1_32K_TIMER_BASE + reg) & 0xffffff;
98}
99
100static inline void omap_32k_timer_start(unsigned long load_val)
101{
102 if (!load_val)
103 load_val = 1;
104 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
105 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
106}
107
108static inline void omap_32k_timer_stop(void)
109{
110 omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
111}
112
113#define omap_32k_timer_ack_irq()
114
115static int omap_32k_timer_set_next_event(unsigned long delta,
116 struct clock_event_device *dev)
117{
118 omap_32k_timer_start(delta);
119
120 return 0;
121}
122
123static void omap_32k_timer_set_mode(enum clock_event_mode mode,
124 struct clock_event_device *evt)
125{
126 omap_32k_timer_stop();
127
128 switch (mode) {
129 case CLOCK_EVT_MODE_PERIODIC:
130 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
131 break;
132 case CLOCK_EVT_MODE_ONESHOT:
133 case CLOCK_EVT_MODE_UNUSED:
134 case CLOCK_EVT_MODE_SHUTDOWN:
135 break;
136 case CLOCK_EVT_MODE_RESUME:
137 break;
138 }
139}
140
141static struct clock_event_device clockevent_32k_timer = {
142 .name = "32k-timer",
143 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
144 .shift = 32,
145 .set_next_event = omap_32k_timer_set_next_event,
146 .set_mode = omap_32k_timer_set_mode,
147};
148
149static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
150{
151 struct clock_event_device *evt = &clockevent_32k_timer;
152 omap_32k_timer_ack_irq();
153
154 evt->event_handler(evt);
155
156 return IRQ_HANDLED;
157}
158
159static struct irqaction omap_32k_timer_irq = {
160 .name = "32KHz timer",
161 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
162 .handler = omap_32k_timer_interrupt,
163};
164
165static __init void omap_init_32k_timer(void)
166{
167 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
168
169 clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
170 NSEC_PER_SEC,
171 clockevent_32k_timer.shift);
172 clockevent_32k_timer.max_delta_ns =
173 clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer);
174 clockevent_32k_timer.min_delta_ns =
175 clockevent_delta2ns(1, &clockevent_32k_timer);
176
177 clockevent_32k_timer.cpumask = cpumask_of(0);
178 clockevents_register_device(&clockevent_32k_timer);
179}
180
181/*
182 * ---------------------------------------------------------------------------
183 * Timer initialization
184 * ---------------------------------------------------------------------------
185 */
186int __init omap_32k_timer_init(void)
187{
188 int ret = -ENODEV;
189
190 if (cpu_is_omap16xx()) {
191 void __iomem *base;
192 struct clk *sync32k_ick;
193
194 base = ioremap(OMAP1_32KSYNC_TIMER_BASE, SZ_1K);
195 if (!base) {
196 pr_err("32k_counter: failed to map base addr\n");
197 return -ENODEV;
198 }
199
200 sync32k_ick = clk_get(NULL, "omap_32ksync_ick");
201 if (!IS_ERR(sync32k_ick))
202 clk_enable(sync32k_ick);
203
204 ret = omap_init_clocksource_32k(base);
205 }
206
207 if (!ret)
208 omap_init_32k_timer();
209
210 return ret;
211}