Loading...
1/*
2 * arch/arm/include/asm/mmu_context.h
3 *
4 * Copyright (C) 1996 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Changelog:
11 * 27-06-1996 RMK Created
12 */
13#ifndef __ASM_ARM_MMU_CONTEXT_H
14#define __ASM_ARM_MMU_CONTEXT_H
15
16#include <linux/compiler.h>
17#include <linux/sched.h>
18#include <asm/cacheflush.h>
19#include <asm/cachetype.h>
20#include <asm/proc-fns.h>
21#include <asm/smp_plat.h>
22#include <asm-generic/mm_hooks.h>
23
24void __check_vmalloc_seq(struct mm_struct *mm);
25
26#ifdef CONFIG_CPU_HAS_ASID
27
28void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
29#define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; })
30
31#ifdef CONFIG_ARM_ERRATA_798181
32void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
33 cpumask_t *mask);
34#else /* !CONFIG_ARM_ERRATA_798181 */
35static inline void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
36 cpumask_t *mask)
37{
38}
39#endif /* CONFIG_ARM_ERRATA_798181 */
40
41#else /* !CONFIG_CPU_HAS_ASID */
42
43#ifdef CONFIG_MMU
44
45static inline void check_and_switch_context(struct mm_struct *mm,
46 struct task_struct *tsk)
47{
48 if (unlikely(mm->context.vmalloc_seq != init_mm.context.vmalloc_seq))
49 __check_vmalloc_seq(mm);
50
51 if (irqs_disabled())
52 /*
53 * cpu_switch_mm() needs to flush the VIVT caches. To avoid
54 * high interrupt latencies, defer the call and continue
55 * running with the old mm. Since we only support UP systems
56 * on non-ASID CPUs, the old mm will remain valid until the
57 * finish_arch_post_lock_switch() call.
58 */
59 mm->context.switch_pending = 1;
60 else
61 cpu_switch_mm(mm->pgd, mm);
62}
63
64#define finish_arch_post_lock_switch \
65 finish_arch_post_lock_switch
66static inline void finish_arch_post_lock_switch(void)
67{
68 struct mm_struct *mm = current->mm;
69
70 if (mm && mm->context.switch_pending) {
71 /*
72 * Preemption must be disabled during cpu_switch_mm() as we
73 * have some stateful cache flush implementations. Check
74 * switch_pending again in case we were preempted and the
75 * switch to this mm was already done.
76 */
77 preempt_disable();
78 if (mm->context.switch_pending) {
79 mm->context.switch_pending = 0;
80 cpu_switch_mm(mm->pgd, mm);
81 }
82 preempt_enable_no_resched();
83 }
84}
85
86#endif /* CONFIG_MMU */
87
88#define init_new_context(tsk,mm) 0
89
90#endif /* CONFIG_CPU_HAS_ASID */
91
92#define destroy_context(mm) do { } while(0)
93#define activate_mm(prev,next) switch_mm(prev, next, NULL)
94
95/*
96 * This is called when "tsk" is about to enter lazy TLB mode.
97 *
98 * mm: describes the currently active mm context
99 * tsk: task which is entering lazy tlb
100 * cpu: cpu number which is entering lazy tlb
101 *
102 * tsk->mm will be NULL
103 */
104static inline void
105enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
106{
107}
108
109/*
110 * This is the actual mm switch as far as the scheduler
111 * is concerned. No registers are touched. We avoid
112 * calling the CPU specific function when the mm hasn't
113 * actually changed.
114 */
115static inline void
116switch_mm(struct mm_struct *prev, struct mm_struct *next,
117 struct task_struct *tsk)
118{
119#ifdef CONFIG_MMU
120 unsigned int cpu = smp_processor_id();
121
122 /*
123 * __sync_icache_dcache doesn't broadcast the I-cache invalidation,
124 * so check for possible thread migration and invalidate the I-cache
125 * if we're new to this CPU.
126 */
127 if (cache_ops_need_broadcast() &&
128 !cpumask_empty(mm_cpumask(next)) &&
129 !cpumask_test_cpu(cpu, mm_cpumask(next)))
130 __flush_icache_all();
131
132 if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
133 check_and_switch_context(next, tsk);
134 if (cache_is_vivt())
135 cpumask_clear_cpu(cpu, mm_cpumask(prev));
136 }
137#endif
138}
139
140#define deactivate_mm(tsk,mm) do { } while (0)
141
142#endif
1/*
2 * arch/arm/include/asm/mmu_context.h
3 *
4 * Copyright (C) 1996 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Changelog:
11 * 27-06-1996 RMK Created
12 */
13#ifndef __ASM_ARM_MMU_CONTEXT_H
14#define __ASM_ARM_MMU_CONTEXT_H
15
16#include <linux/compiler.h>
17#include <linux/sched.h>
18#include <asm/cacheflush.h>
19#include <asm/cachetype.h>
20#include <asm/proc-fns.h>
21#include <asm-generic/mm_hooks.h>
22
23void __check_kvm_seq(struct mm_struct *mm);
24
25#ifdef CONFIG_CPU_HAS_ASID
26
27/*
28 * On ARMv6, we have the following structure in the Context ID:
29 *
30 * 31 7 0
31 * +-------------------------+-----------+
32 * | process ID | ASID |
33 * +-------------------------+-----------+
34 * | context ID |
35 * +-------------------------------------+
36 *
37 * The ASID is used to tag entries in the CPU caches and TLBs.
38 * The context ID is used by debuggers and trace logic, and
39 * should be unique within all running processes.
40 */
41#define ASID_BITS 8
42#define ASID_MASK ((~0) << ASID_BITS)
43#define ASID_FIRST_VERSION (1 << ASID_BITS)
44
45extern unsigned int cpu_last_asid;
46
47void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
48void __new_context(struct mm_struct *mm);
49void cpu_set_reserved_ttbr0(void);
50
51static inline void switch_new_context(struct mm_struct *mm)
52{
53 unsigned long flags;
54
55 __new_context(mm);
56
57 local_irq_save(flags);
58 cpu_switch_mm(mm->pgd, mm);
59 local_irq_restore(flags);
60}
61
62static inline void check_and_switch_context(struct mm_struct *mm,
63 struct task_struct *tsk)
64{
65 if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
66 __check_kvm_seq(mm);
67
68 /*
69 * Required during context switch to avoid speculative page table
70 * walking with the wrong TTBR.
71 */
72 cpu_set_reserved_ttbr0();
73
74 if (!((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
75 /*
76 * The ASID is from the current generation, just switch to the
77 * new pgd. This condition is only true for calls from
78 * context_switch() and interrupts are already disabled.
79 */
80 cpu_switch_mm(mm->pgd, mm);
81 else if (irqs_disabled())
82 /*
83 * Defer the new ASID allocation until after the context
84 * switch critical region since __new_context() cannot be
85 * called with interrupts disabled (it sends IPIs).
86 */
87 set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
88 else
89 /*
90 * That is a direct call to switch_mm() or activate_mm() with
91 * interrupts enabled and a new context.
92 */
93 switch_new_context(mm);
94}
95
96#define init_new_context(tsk,mm) (__init_new_context(tsk,mm),0)
97
98#define finish_arch_post_lock_switch \
99 finish_arch_post_lock_switch
100static inline void finish_arch_post_lock_switch(void)
101{
102 if (test_and_clear_thread_flag(TIF_SWITCH_MM))
103 switch_new_context(current->mm);
104}
105
106#else /* !CONFIG_CPU_HAS_ASID */
107
108#ifdef CONFIG_MMU
109
110static inline void check_and_switch_context(struct mm_struct *mm,
111 struct task_struct *tsk)
112{
113 if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
114 __check_kvm_seq(mm);
115
116 if (irqs_disabled())
117 /*
118 * cpu_switch_mm() needs to flush the VIVT caches. To avoid
119 * high interrupt latencies, defer the call and continue
120 * running with the old mm. Since we only support UP systems
121 * on non-ASID CPUs, the old mm will remain valid until the
122 * finish_arch_post_lock_switch() call.
123 */
124 set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
125 else
126 cpu_switch_mm(mm->pgd, mm);
127}
128
129#define finish_arch_post_lock_switch \
130 finish_arch_post_lock_switch
131static inline void finish_arch_post_lock_switch(void)
132{
133 if (test_and_clear_thread_flag(TIF_SWITCH_MM)) {
134 struct mm_struct *mm = current->mm;
135 cpu_switch_mm(mm->pgd, mm);
136 }
137}
138
139#endif /* CONFIG_MMU */
140
141#define init_new_context(tsk,mm) 0
142
143#endif /* CONFIG_CPU_HAS_ASID */
144
145#define destroy_context(mm) do { } while(0)
146
147/*
148 * This is called when "tsk" is about to enter lazy TLB mode.
149 *
150 * mm: describes the currently active mm context
151 * tsk: task which is entering lazy tlb
152 * cpu: cpu number which is entering lazy tlb
153 *
154 * tsk->mm will be NULL
155 */
156static inline void
157enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
158{
159}
160
161/*
162 * This is the actual mm switch as far as the scheduler
163 * is concerned. No registers are touched. We avoid
164 * calling the CPU specific function when the mm hasn't
165 * actually changed.
166 */
167static inline void
168switch_mm(struct mm_struct *prev, struct mm_struct *next,
169 struct task_struct *tsk)
170{
171#ifdef CONFIG_MMU
172 unsigned int cpu = smp_processor_id();
173
174#ifdef CONFIG_SMP
175 /* check for possible thread migration */
176 if (!cpumask_empty(mm_cpumask(next)) &&
177 !cpumask_test_cpu(cpu, mm_cpumask(next)))
178 __flush_icache_all();
179#endif
180 if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
181 check_and_switch_context(next, tsk);
182 if (cache_is_vivt())
183 cpumask_clear_cpu(cpu, mm_cpumask(prev));
184 }
185#endif
186}
187
188#define deactivate_mm(tsk,mm) do { } while (0)
189#define activate_mm(prev,next) switch_mm(prev, next, NULL)
190
191#endif