1Software emulation of deprecated SWP instruction (CONFIG_SWP_EMULATE)
 2---------------------------------------------------------------------
 3
 4ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommeds
 5moving to the load-locked/store-conditional instructions LDREX and STREX.
 6
 7ARMv7 multiprocessing extensions introduce the ability to disable these
 8instructions, triggering an undefined instruction exception when executed.
 9Trapped instructions are emulated using an LDREX/STREX or LDREXB/STREXB
10sequence. If a memory access fault (an abort) occurs, a segmentation fault is
11signalled to the triggering process.
12
13/proc/cpu/swp_emulation holds some statistics/information, including the PID of
14the last process to trigger the emulation to be invocated. For example:
15---
16Emulated SWP:		12
17Emulated SWPB:		0
18Aborted SWP{B}:		1
19Last process:		314
20---
21
22NOTE: when accessing uncached shared regions, LDREX/STREX rely on an external
23transaction monitoring block called a global monitor to maintain update
24atomicity. If your system does not implement a global monitor, this option can
25cause programs that perform SWP operations to uncached memory to deadlock, as
26the STREX operation will always fail.
27

 1Software emulation of deprecated SWP instruction (CONFIG_SWP_EMULATE)
 2---------------------------------------------------------------------
 3
 4ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommeds
 5moving to the load-locked/store-conditional instructions LDREX and STREX.
 6
 7ARMv7 multiprocessing extensions introduce the ability to disable these
 8instructions, triggering an undefined instruction exception when executed.
 9Trapped instructions are emulated using an LDREX/STREX or LDREXB/STREXB
10sequence. If a memory access fault (an abort) occurs, a segmentation fault is
11signalled to the triggering process.
12
13/proc/cpu/swp_emulation holds some statistics/information, including the PID of
14the last process to trigger the emulation to be invocated. For example:
15---
16Emulated SWP:		12
17Emulated SWPB:		0
18Aborted SWP{B}:		1
19Last process:		314
20---
21
22NOTE: when accessing uncached shared regions, LDREX/STREX rely on an external
23transaction monitoring block called a global monitor to maintain update
24atomicity. If your system does not implement a global monitor, this option can
25cause programs that perform SWP operations to uncached memory to deadlock, as
26the STREX operation will always fail.
27