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1/*
2 * linux/drivers/net/ethernet/ibm/ehea/ehea.h
3 *
4 * eHEA ethernet device driver for IBM eServer System p
5 *
6 * (C) Copyright IBM Corp. 2006
7 *
8 * Authors:
9 * Christoph Raisch <raisch@de.ibm.com>
10 * Jan-Bernd Themann <themann@de.ibm.com>
11 * Thomas Klein <tklein@de.ibm.com>
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2, or (at your option)
17 * any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __EHEA_H__
30#define __EHEA_H__
31
32#include <linux/module.h>
33#include <linux/ethtool.h>
34#include <linux/vmalloc.h>
35#include <linux/if_vlan.h>
36
37#include <asm/ibmebus.h>
38#include <asm/io.h>
39
40#define DRV_NAME "ehea"
41#define DRV_VERSION "EHEA_0107"
42
43/* eHEA capability flags */
44#define DLPAR_PORT_ADD_REM 1
45#define DLPAR_MEM_ADD 2
46#define DLPAR_MEM_REM 4
47#define EHEA_CAPABILITIES (DLPAR_PORT_ADD_REM | DLPAR_MEM_ADD | DLPAR_MEM_REM)
48
49#define EHEA_MSG_DEFAULT (NETIF_MSG_LINK | NETIF_MSG_TIMER \
50 | NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
51
52#define EHEA_MAX_ENTRIES_RQ1 32767
53#define EHEA_MAX_ENTRIES_RQ2 16383
54#define EHEA_MAX_ENTRIES_RQ3 16383
55#define EHEA_MAX_ENTRIES_SQ 32767
56#define EHEA_MIN_ENTRIES_QP 127
57
58#define EHEA_SMALL_QUEUES
59
60#ifdef EHEA_SMALL_QUEUES
61#define EHEA_MAX_CQE_COUNT 1023
62#define EHEA_DEF_ENTRIES_SQ 1023
63#define EHEA_DEF_ENTRIES_RQ1 1023
64#define EHEA_DEF_ENTRIES_RQ2 1023
65#define EHEA_DEF_ENTRIES_RQ3 511
66#else
67#define EHEA_MAX_CQE_COUNT 4080
68#define EHEA_DEF_ENTRIES_SQ 4080
69#define EHEA_DEF_ENTRIES_RQ1 8160
70#define EHEA_DEF_ENTRIES_RQ2 2040
71#define EHEA_DEF_ENTRIES_RQ3 2040
72#endif
73
74#define EHEA_MAX_ENTRIES_EQ 20
75
76#define EHEA_SG_SQ 2
77#define EHEA_SG_RQ1 1
78#define EHEA_SG_RQ2 0
79#define EHEA_SG_RQ3 0
80
81#define EHEA_MAX_PACKET_SIZE 9022 /* for jumbo frames */
82#define EHEA_RQ2_PKT_SIZE 2048
83#define EHEA_L_PKT_SIZE 256 /* low latency */
84
85/* Send completion signaling */
86
87/* Protection Domain Identifier */
88#define EHEA_PD_ID 0xaabcdeff
89
90#define EHEA_RQ2_THRESHOLD 1
91#define EHEA_RQ3_THRESHOLD 4 /* use RQ3 threshold of 2048 bytes */
92
93#define EHEA_SPEED_10G 10000
94#define EHEA_SPEED_1G 1000
95#define EHEA_SPEED_100M 100
96#define EHEA_SPEED_10M 10
97#define EHEA_SPEED_AUTONEG 0
98
99/* Broadcast/Multicast registration types */
100#define EHEA_BCMC_SCOPE_ALL 0x08
101#define EHEA_BCMC_SCOPE_SINGLE 0x00
102#define EHEA_BCMC_MULTICAST 0x04
103#define EHEA_BCMC_BROADCAST 0x00
104#define EHEA_BCMC_UNTAGGED 0x02
105#define EHEA_BCMC_TAGGED 0x00
106#define EHEA_BCMC_VLANID_ALL 0x01
107#define EHEA_BCMC_VLANID_SINGLE 0x00
108
109#define EHEA_CACHE_LINE 128
110
111/* Memory Regions */
112#define EHEA_MR_ACC_CTRL 0x00800000
113
114#define EHEA_BUSMAP_START 0x8000000000000000ULL
115#define EHEA_INVAL_ADDR 0xFFFFFFFFFFFFFFFFULL
116#define EHEA_DIR_INDEX_SHIFT 13 /* 8k Entries in 64k block */
117#define EHEA_TOP_INDEX_SHIFT (EHEA_DIR_INDEX_SHIFT * 2)
118#define EHEA_MAP_ENTRIES (1 << EHEA_DIR_INDEX_SHIFT)
119#define EHEA_MAP_SIZE (0x10000) /* currently fixed map size */
120#define EHEA_INDEX_MASK (EHEA_MAP_ENTRIES - 1)
121
122
123#define EHEA_WATCH_DOG_TIMEOUT 10*HZ
124
125/* utility functions */
126
127void ehea_dump(void *adr, int len, char *msg);
128
129#define EHEA_BMASK(pos, length) (((pos) << 16) + (length))
130
131#define EHEA_BMASK_IBM(from, to) (((63 - to) << 16) + ((to) - (from) + 1))
132
133#define EHEA_BMASK_SHIFTPOS(mask) (((mask) >> 16) & 0xffff)
134
135#define EHEA_BMASK_MASK(mask) \
136 (0xffffffffffffffffULL >> ((64 - (mask)) & 0xffff))
137
138#define EHEA_BMASK_SET(mask, value) \
139 ((EHEA_BMASK_MASK(mask) & ((u64)(value))) << EHEA_BMASK_SHIFTPOS(mask))
140
141#define EHEA_BMASK_GET(mask, value) \
142 (EHEA_BMASK_MASK(mask) & (((u64)(value)) >> EHEA_BMASK_SHIFTPOS(mask)))
143
144/*
145 * Generic ehea page
146 */
147struct ehea_page {
148 u8 entries[PAGE_SIZE];
149};
150
151/*
152 * Generic queue in linux kernel virtual memory
153 */
154struct hw_queue {
155 u64 current_q_offset; /* current queue entry */
156 struct ehea_page **queue_pages; /* array of pages belonging to queue */
157 u32 qe_size; /* queue entry size */
158 u32 queue_length; /* queue length allocated in bytes */
159 u32 pagesize;
160 u32 toggle_state; /* toggle flag - per page */
161 u32 reserved; /* 64 bit alignment */
162};
163
164/*
165 * For pSeries this is a 64bit memory address where
166 * I/O memory is mapped into CPU address space
167 */
168struct h_epa {
169 void __iomem *addr;
170};
171
172struct h_epa_user {
173 u64 addr;
174};
175
176struct h_epas {
177 struct h_epa kernel; /* kernel space accessible resource,
178 set to 0 if unused */
179 struct h_epa_user user; /* user space accessible resource
180 set to 0 if unused */
181};
182
183/*
184 * Memory map data structures
185 */
186struct ehea_dir_bmap
187{
188 u64 ent[EHEA_MAP_ENTRIES];
189};
190struct ehea_top_bmap
191{
192 struct ehea_dir_bmap *dir[EHEA_MAP_ENTRIES];
193};
194struct ehea_bmap
195{
196 struct ehea_top_bmap *top[EHEA_MAP_ENTRIES];
197};
198
199struct ehea_qp;
200struct ehea_cq;
201struct ehea_eq;
202struct ehea_port;
203struct ehea_av;
204
205/*
206 * Queue attributes passed to ehea_create_qp()
207 */
208struct ehea_qp_init_attr {
209 /* input parameter */
210 u32 qp_token; /* queue token */
211 u8 low_lat_rq1;
212 u8 signalingtype; /* cqe generation flag */
213 u8 rq_count; /* num of receive queues */
214 u8 eqe_gen; /* eqe generation flag */
215 u16 max_nr_send_wqes; /* max number of send wqes */
216 u16 max_nr_rwqes_rq1; /* max number of receive wqes */
217 u16 max_nr_rwqes_rq2;
218 u16 max_nr_rwqes_rq3;
219 u8 wqe_size_enc_sq;
220 u8 wqe_size_enc_rq1;
221 u8 wqe_size_enc_rq2;
222 u8 wqe_size_enc_rq3;
223 u8 swqe_imm_data_len; /* immediate data length for swqes */
224 u16 port_nr;
225 u16 rq2_threshold;
226 u16 rq3_threshold;
227 u64 send_cq_handle;
228 u64 recv_cq_handle;
229 u64 aff_eq_handle;
230
231 /* output parameter */
232 u32 qp_nr;
233 u16 act_nr_send_wqes;
234 u16 act_nr_rwqes_rq1;
235 u16 act_nr_rwqes_rq2;
236 u16 act_nr_rwqes_rq3;
237 u8 act_wqe_size_enc_sq;
238 u8 act_wqe_size_enc_rq1;
239 u8 act_wqe_size_enc_rq2;
240 u8 act_wqe_size_enc_rq3;
241 u32 nr_sq_pages;
242 u32 nr_rq1_pages;
243 u32 nr_rq2_pages;
244 u32 nr_rq3_pages;
245 u32 liobn_sq;
246 u32 liobn_rq1;
247 u32 liobn_rq2;
248 u32 liobn_rq3;
249};
250
251/*
252 * Event Queue attributes, passed as parameter
253 */
254struct ehea_eq_attr {
255 u32 type;
256 u32 max_nr_of_eqes;
257 u8 eqe_gen; /* generate eqe flag */
258 u64 eq_handle;
259 u32 act_nr_of_eqes;
260 u32 nr_pages;
261 u32 ist1; /* Interrupt service token */
262 u32 ist2;
263 u32 ist3;
264 u32 ist4;
265};
266
267
268/*
269 * Event Queue
270 */
271struct ehea_eq {
272 struct ehea_adapter *adapter;
273 struct hw_queue hw_queue;
274 u64 fw_handle;
275 struct h_epas epas;
276 spinlock_t spinlock;
277 struct ehea_eq_attr attr;
278};
279
280/*
281 * HEA Queues
282 */
283struct ehea_qp {
284 struct ehea_adapter *adapter;
285 u64 fw_handle; /* QP handle for firmware calls */
286 struct hw_queue hw_squeue;
287 struct hw_queue hw_rqueue1;
288 struct hw_queue hw_rqueue2;
289 struct hw_queue hw_rqueue3;
290 struct h_epas epas;
291 struct ehea_qp_init_attr init_attr;
292};
293
294/*
295 * Completion Queue attributes
296 */
297struct ehea_cq_attr {
298 /* input parameter */
299 u32 max_nr_of_cqes;
300 u32 cq_token;
301 u64 eq_handle;
302
303 /* output parameter */
304 u32 act_nr_of_cqes;
305 u32 nr_pages;
306};
307
308/*
309 * Completion Queue
310 */
311struct ehea_cq {
312 struct ehea_adapter *adapter;
313 u64 fw_handle;
314 struct hw_queue hw_queue;
315 struct h_epas epas;
316 struct ehea_cq_attr attr;
317};
318
319/*
320 * Memory Region
321 */
322struct ehea_mr {
323 struct ehea_adapter *adapter;
324 u64 handle;
325 u64 vaddr;
326 u32 lkey;
327};
328
329/*
330 * Port state information
331 */
332struct port_stats {
333 int poll_receive_errors;
334 int queue_stopped;
335 int err_tcp_cksum;
336 int err_ip_cksum;
337 int err_frame_crc;
338};
339
340#define EHEA_IRQ_NAME_SIZE 20
341
342/*
343 * Queue SKB Array
344 */
345struct ehea_q_skb_arr {
346 struct sk_buff **arr; /* skb array for queue */
347 int len; /* array length */
348 int index; /* array index */
349 int os_skbs; /* rq2/rq3 only: outstanding skbs */
350};
351
352/*
353 * Port resources
354 */
355struct ehea_port_res {
356 struct napi_struct napi;
357 struct port_stats p_stats;
358 struct ehea_mr send_mr; /* send memory region */
359 struct ehea_mr recv_mr; /* receive memory region */
360 struct ehea_port *port;
361 char int_recv_name[EHEA_IRQ_NAME_SIZE];
362 char int_send_name[EHEA_IRQ_NAME_SIZE];
363 struct ehea_qp *qp;
364 struct ehea_cq *send_cq;
365 struct ehea_cq *recv_cq;
366 struct ehea_eq *eq;
367 struct ehea_q_skb_arr rq1_skba;
368 struct ehea_q_skb_arr rq2_skba;
369 struct ehea_q_skb_arr rq3_skba;
370 struct ehea_q_skb_arr sq_skba;
371 int sq_skba_size;
372 int swqe_refill_th;
373 atomic_t swqe_avail;
374 int swqe_ll_count;
375 u32 swqe_id_counter;
376 u64 tx_packets;
377 u64 tx_bytes;
378 u64 rx_packets;
379 u64 rx_bytes;
380 int sq_restart_flag;
381};
382
383
384#define EHEA_MAX_PORTS 16
385
386#define EHEA_NUM_PORTRES_FW_HANDLES 6 /* QP handle, SendCQ handle,
387 RecvCQ handle, EQ handle,
388 SendMR handle, RecvMR handle */
389#define EHEA_NUM_PORT_FW_HANDLES 1 /* EQ handle */
390#define EHEA_NUM_ADAPTER_FW_HANDLES 2 /* MR handle, NEQ handle */
391
392struct ehea_adapter {
393 u64 handle;
394 struct platform_device *ofdev;
395 struct ehea_port *port[EHEA_MAX_PORTS];
396 struct ehea_eq *neq; /* notification event queue */
397 struct tasklet_struct neq_tasklet;
398 struct ehea_mr mr;
399 u32 pd; /* protection domain */
400 u64 max_mc_mac; /* max number of multicast mac addresses */
401 int active_ports;
402 struct list_head list;
403};
404
405
406struct ehea_mc_list {
407 struct list_head list;
408 u64 macaddr;
409};
410
411/* kdump support */
412struct ehea_fw_handle_entry {
413 u64 adh; /* Adapter Handle */
414 u64 fwh; /* Firmware Handle */
415};
416
417struct ehea_fw_handle_array {
418 struct ehea_fw_handle_entry *arr;
419 int num_entries;
420 struct mutex lock;
421};
422
423struct ehea_bcmc_reg_entry {
424 u64 adh; /* Adapter Handle */
425 u32 port_id; /* Logical Port Id */
426 u8 reg_type; /* Registration Type */
427 u64 macaddr;
428};
429
430struct ehea_bcmc_reg_array {
431 struct ehea_bcmc_reg_entry *arr;
432 int num_entries;
433 spinlock_t lock;
434};
435
436#define EHEA_PORT_UP 1
437#define EHEA_PORT_DOWN 0
438#define EHEA_PHY_LINK_UP 1
439#define EHEA_PHY_LINK_DOWN 0
440#define EHEA_MAX_PORT_RES 16
441struct ehea_port {
442 struct ehea_adapter *adapter; /* adapter that owns this port */
443 struct net_device *netdev;
444 struct rtnl_link_stats64 stats;
445 struct ehea_port_res port_res[EHEA_MAX_PORT_RES];
446 struct platform_device ofdev; /* Open Firmware Device */
447 struct ehea_mc_list *mc_list; /* Multicast MAC addresses */
448 struct ehea_eq *qp_eq;
449 struct work_struct reset_task;
450 struct delayed_work stats_work;
451 struct mutex port_lock;
452 char int_aff_name[EHEA_IRQ_NAME_SIZE];
453 int allmulti; /* Indicates IFF_ALLMULTI state */
454 int promisc; /* Indicates IFF_PROMISC state */
455 int num_mcs;
456 int resets;
457 unsigned long flags;
458 u64 mac_addr;
459 u32 logical_port_id;
460 u32 port_speed;
461 u32 msg_enable;
462 u32 sig_comp_iv;
463 u32 state;
464 u8 phy_link;
465 u8 full_duplex;
466 u8 autoneg;
467 u8 num_def_qps;
468 wait_queue_head_t swqe_avail_wq;
469 wait_queue_head_t restart_wq;
470};
471
472struct port_res_cfg {
473 int max_entries_rcq;
474 int max_entries_scq;
475 int max_entries_sq;
476 int max_entries_rq1;
477 int max_entries_rq2;
478 int max_entries_rq3;
479};
480
481enum ehea_flag_bits {
482 __EHEA_STOP_XFER,
483 __EHEA_DISABLE_PORT_RESET
484};
485
486void ehea_set_ethtool_ops(struct net_device *netdev);
487int ehea_sense_port_attr(struct ehea_port *port);
488int ehea_set_portspeed(struct ehea_port *port, u32 port_speed);
489
490#endif /* __EHEA_H__ */
1/*
2 * linux/drivers/net/ethernet/ibm/ehea/ehea.h
3 *
4 * eHEA ethernet device driver for IBM eServer System p
5 *
6 * (C) Copyright IBM Corp. 2006
7 *
8 * Authors:
9 * Christoph Raisch <raisch@de.ibm.com>
10 * Jan-Bernd Themann <themann@de.ibm.com>
11 * Thomas Klein <tklein@de.ibm.com>
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2, or (at your option)
17 * any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __EHEA_H__
30#define __EHEA_H__
31
32#include <linux/module.h>
33#include <linux/ethtool.h>
34#include <linux/vmalloc.h>
35#include <linux/if_vlan.h>
36
37#include <asm/ibmebus.h>
38#include <asm/io.h>
39
40#define DRV_NAME "ehea"
41#define DRV_VERSION "EHEA_0107"
42
43/* eHEA capability flags */
44#define DLPAR_PORT_ADD_REM 1
45#define DLPAR_MEM_ADD 2
46#define DLPAR_MEM_REM 4
47#define EHEA_CAPABILITIES (DLPAR_PORT_ADD_REM | DLPAR_MEM_ADD | DLPAR_MEM_REM)
48
49#define EHEA_MSG_DEFAULT (NETIF_MSG_LINK | NETIF_MSG_TIMER \
50 | NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
51
52#define EHEA_MAX_ENTRIES_RQ1 32767
53#define EHEA_MAX_ENTRIES_RQ2 16383
54#define EHEA_MAX_ENTRIES_RQ3 16383
55#define EHEA_MAX_ENTRIES_SQ 32767
56#define EHEA_MIN_ENTRIES_QP 127
57
58#define EHEA_SMALL_QUEUES
59
60#ifdef EHEA_SMALL_QUEUES
61#define EHEA_MAX_CQE_COUNT 1023
62#define EHEA_DEF_ENTRIES_SQ 1023
63#define EHEA_DEF_ENTRIES_RQ1 1023
64#define EHEA_DEF_ENTRIES_RQ2 1023
65#define EHEA_DEF_ENTRIES_RQ3 511
66#else
67#define EHEA_MAX_CQE_COUNT 4080
68#define EHEA_DEF_ENTRIES_SQ 4080
69#define EHEA_DEF_ENTRIES_RQ1 8160
70#define EHEA_DEF_ENTRIES_RQ2 2040
71#define EHEA_DEF_ENTRIES_RQ3 2040
72#endif
73
74#define EHEA_MAX_ENTRIES_EQ 20
75
76#define EHEA_SG_SQ 2
77#define EHEA_SG_RQ1 1
78#define EHEA_SG_RQ2 0
79#define EHEA_SG_RQ3 0
80
81#define EHEA_MAX_PACKET_SIZE 9022 /* for jumbo frames */
82#define EHEA_RQ2_PKT_SIZE 2048
83#define EHEA_L_PKT_SIZE 256 /* low latency */
84
85/* Send completion signaling */
86
87/* Protection Domain Identifier */
88#define EHEA_PD_ID 0xaabcdeff
89
90#define EHEA_RQ2_THRESHOLD 1
91#define EHEA_RQ3_THRESHOLD 4 /* use RQ3 threshold of 2048 bytes */
92
93#define EHEA_SPEED_10G 10000
94#define EHEA_SPEED_1G 1000
95#define EHEA_SPEED_100M 100
96#define EHEA_SPEED_10M 10
97#define EHEA_SPEED_AUTONEG 0
98
99/* Broadcast/Multicast registration types */
100#define EHEA_BCMC_SCOPE_ALL 0x08
101#define EHEA_BCMC_SCOPE_SINGLE 0x00
102#define EHEA_BCMC_MULTICAST 0x04
103#define EHEA_BCMC_BROADCAST 0x00
104#define EHEA_BCMC_UNTAGGED 0x02
105#define EHEA_BCMC_TAGGED 0x00
106#define EHEA_BCMC_VLANID_ALL 0x01
107#define EHEA_BCMC_VLANID_SINGLE 0x00
108
109#define EHEA_CACHE_LINE 128
110
111/* Memory Regions */
112#define EHEA_MR_ACC_CTRL 0x00800000
113
114#define EHEA_BUSMAP_START 0x8000000000000000ULL
115#define EHEA_INVAL_ADDR 0xFFFFFFFFFFFFFFFFULL
116#define EHEA_DIR_INDEX_SHIFT 13 /* 8k Entries in 64k block */
117#define EHEA_TOP_INDEX_SHIFT (EHEA_DIR_INDEX_SHIFT * 2)
118#define EHEA_MAP_ENTRIES (1 << EHEA_DIR_INDEX_SHIFT)
119#define EHEA_MAP_SIZE (0x10000) /* currently fixed map size */
120#define EHEA_INDEX_MASK (EHEA_MAP_ENTRIES - 1)
121
122
123#define EHEA_WATCH_DOG_TIMEOUT 10*HZ
124
125/* utility functions */
126
127void ehea_dump(void *adr, int len, char *msg);
128
129#define EHEA_BMASK(pos, length) (((pos) << 16) + (length))
130
131#define EHEA_BMASK_IBM(from, to) (((63 - to) << 16) + ((to) - (from) + 1))
132
133#define EHEA_BMASK_SHIFTPOS(mask) (((mask) >> 16) & 0xffff)
134
135#define EHEA_BMASK_MASK(mask) \
136 (0xffffffffffffffffULL >> ((64 - (mask)) & 0xffff))
137
138#define EHEA_BMASK_SET(mask, value) \
139 ((EHEA_BMASK_MASK(mask) & ((u64)(value))) << EHEA_BMASK_SHIFTPOS(mask))
140
141#define EHEA_BMASK_GET(mask, value) \
142 (EHEA_BMASK_MASK(mask) & (((u64)(value)) >> EHEA_BMASK_SHIFTPOS(mask)))
143
144/*
145 * Generic ehea page
146 */
147struct ehea_page {
148 u8 entries[PAGE_SIZE];
149};
150
151/*
152 * Generic queue in linux kernel virtual memory
153 */
154struct hw_queue {
155 u64 current_q_offset; /* current queue entry */
156 struct ehea_page **queue_pages; /* array of pages belonging to queue */
157 u32 qe_size; /* queue entry size */
158 u32 queue_length; /* queue length allocated in bytes */
159 u32 pagesize;
160 u32 toggle_state; /* toggle flag - per page */
161 u32 reserved; /* 64 bit alignment */
162};
163
164/*
165 * For pSeries this is a 64bit memory address where
166 * I/O memory is mapped into CPU address space
167 */
168struct h_epa {
169 void __iomem *addr;
170};
171
172struct h_epa_user {
173 u64 addr;
174};
175
176struct h_epas {
177 struct h_epa kernel; /* kernel space accessible resource,
178 set to 0 if unused */
179 struct h_epa_user user; /* user space accessible resource
180 set to 0 if unused */
181};
182
183/*
184 * Memory map data structures
185 */
186struct ehea_dir_bmap
187{
188 u64 ent[EHEA_MAP_ENTRIES];
189};
190struct ehea_top_bmap
191{
192 struct ehea_dir_bmap *dir[EHEA_MAP_ENTRIES];
193};
194struct ehea_bmap
195{
196 struct ehea_top_bmap *top[EHEA_MAP_ENTRIES];
197};
198
199struct ehea_qp;
200struct ehea_cq;
201struct ehea_eq;
202struct ehea_port;
203struct ehea_av;
204
205/*
206 * Queue attributes passed to ehea_create_qp()
207 */
208struct ehea_qp_init_attr {
209 /* input parameter */
210 u32 qp_token; /* queue token */
211 u8 low_lat_rq1;
212 u8 signalingtype; /* cqe generation flag */
213 u8 rq_count; /* num of receive queues */
214 u8 eqe_gen; /* eqe generation flag */
215 u16 max_nr_send_wqes; /* max number of send wqes */
216 u16 max_nr_rwqes_rq1; /* max number of receive wqes */
217 u16 max_nr_rwqes_rq2;
218 u16 max_nr_rwqes_rq3;
219 u8 wqe_size_enc_sq;
220 u8 wqe_size_enc_rq1;
221 u8 wqe_size_enc_rq2;
222 u8 wqe_size_enc_rq3;
223 u8 swqe_imm_data_len; /* immediate data length for swqes */
224 u16 port_nr;
225 u16 rq2_threshold;
226 u16 rq3_threshold;
227 u64 send_cq_handle;
228 u64 recv_cq_handle;
229 u64 aff_eq_handle;
230
231 /* output parameter */
232 u32 qp_nr;
233 u16 act_nr_send_wqes;
234 u16 act_nr_rwqes_rq1;
235 u16 act_nr_rwqes_rq2;
236 u16 act_nr_rwqes_rq3;
237 u8 act_wqe_size_enc_sq;
238 u8 act_wqe_size_enc_rq1;
239 u8 act_wqe_size_enc_rq2;
240 u8 act_wqe_size_enc_rq3;
241 u32 nr_sq_pages;
242 u32 nr_rq1_pages;
243 u32 nr_rq2_pages;
244 u32 nr_rq3_pages;
245 u32 liobn_sq;
246 u32 liobn_rq1;
247 u32 liobn_rq2;
248 u32 liobn_rq3;
249};
250
251/*
252 * Event Queue attributes, passed as parameter
253 */
254struct ehea_eq_attr {
255 u32 type;
256 u32 max_nr_of_eqes;
257 u8 eqe_gen; /* generate eqe flag */
258 u64 eq_handle;
259 u32 act_nr_of_eqes;
260 u32 nr_pages;
261 u32 ist1; /* Interrupt service token */
262 u32 ist2;
263 u32 ist3;
264 u32 ist4;
265};
266
267
268/*
269 * Event Queue
270 */
271struct ehea_eq {
272 struct ehea_adapter *adapter;
273 struct hw_queue hw_queue;
274 u64 fw_handle;
275 struct h_epas epas;
276 spinlock_t spinlock;
277 struct ehea_eq_attr attr;
278};
279
280/*
281 * HEA Queues
282 */
283struct ehea_qp {
284 struct ehea_adapter *adapter;
285 u64 fw_handle; /* QP handle for firmware calls */
286 struct hw_queue hw_squeue;
287 struct hw_queue hw_rqueue1;
288 struct hw_queue hw_rqueue2;
289 struct hw_queue hw_rqueue3;
290 struct h_epas epas;
291 struct ehea_qp_init_attr init_attr;
292};
293
294/*
295 * Completion Queue attributes
296 */
297struct ehea_cq_attr {
298 /* input parameter */
299 u32 max_nr_of_cqes;
300 u32 cq_token;
301 u64 eq_handle;
302
303 /* output parameter */
304 u32 act_nr_of_cqes;
305 u32 nr_pages;
306};
307
308/*
309 * Completion Queue
310 */
311struct ehea_cq {
312 struct ehea_adapter *adapter;
313 u64 fw_handle;
314 struct hw_queue hw_queue;
315 struct h_epas epas;
316 struct ehea_cq_attr attr;
317};
318
319/*
320 * Memory Region
321 */
322struct ehea_mr {
323 struct ehea_adapter *adapter;
324 u64 handle;
325 u64 vaddr;
326 u32 lkey;
327};
328
329/*
330 * Port state information
331 */
332struct port_stats {
333 int poll_receive_errors;
334 int queue_stopped;
335 int err_tcp_cksum;
336 int err_ip_cksum;
337 int err_frame_crc;
338};
339
340#define EHEA_IRQ_NAME_SIZE 20
341
342/*
343 * Queue SKB Array
344 */
345struct ehea_q_skb_arr {
346 struct sk_buff **arr; /* skb array for queue */
347 int len; /* array length */
348 int index; /* array index */
349 int os_skbs; /* rq2/rq3 only: outstanding skbs */
350};
351
352/*
353 * Port resources
354 */
355struct ehea_port_res {
356 struct napi_struct napi;
357 struct port_stats p_stats;
358 struct ehea_mr send_mr; /* send memory region */
359 struct ehea_mr recv_mr; /* receive memory region */
360 struct ehea_port *port;
361 char int_recv_name[EHEA_IRQ_NAME_SIZE];
362 char int_send_name[EHEA_IRQ_NAME_SIZE];
363 struct ehea_qp *qp;
364 struct ehea_cq *send_cq;
365 struct ehea_cq *recv_cq;
366 struct ehea_eq *eq;
367 struct ehea_q_skb_arr rq1_skba;
368 struct ehea_q_skb_arr rq2_skba;
369 struct ehea_q_skb_arr rq3_skba;
370 struct ehea_q_skb_arr sq_skba;
371 int sq_skba_size;
372 int swqe_refill_th;
373 atomic_t swqe_avail;
374 int swqe_ll_count;
375 u32 swqe_id_counter;
376 u64 tx_packets;
377 u64 tx_bytes;
378 u64 rx_packets;
379 u64 rx_bytes;
380 int sq_restart_flag;
381};
382
383
384#define EHEA_MAX_PORTS 16
385
386#define EHEA_NUM_PORTRES_FW_HANDLES 6 /* QP handle, SendCQ handle,
387 RecvCQ handle, EQ handle,
388 SendMR handle, RecvMR handle */
389#define EHEA_NUM_PORT_FW_HANDLES 1 /* EQ handle */
390#define EHEA_NUM_ADAPTER_FW_HANDLES 2 /* MR handle, NEQ handle */
391
392struct ehea_adapter {
393 u64 handle;
394 struct platform_device *ofdev;
395 struct ehea_port *port[EHEA_MAX_PORTS];
396 struct ehea_eq *neq; /* notification event queue */
397 struct tasklet_struct neq_tasklet;
398 struct ehea_mr mr;
399 u32 pd; /* protection domain */
400 u64 max_mc_mac; /* max number of multicast mac addresses */
401 int active_ports;
402 struct list_head list;
403};
404
405
406struct ehea_mc_list {
407 struct list_head list;
408 u64 macaddr;
409};
410
411/* kdump support */
412struct ehea_fw_handle_entry {
413 u64 adh; /* Adapter Handle */
414 u64 fwh; /* Firmware Handle */
415};
416
417struct ehea_fw_handle_array {
418 struct ehea_fw_handle_entry *arr;
419 int num_entries;
420 struct mutex lock;
421};
422
423struct ehea_bcmc_reg_entry {
424 u64 adh; /* Adapter Handle */
425 u32 port_id; /* Logical Port Id */
426 u8 reg_type; /* Registration Type */
427 u64 macaddr;
428};
429
430struct ehea_bcmc_reg_array {
431 struct ehea_bcmc_reg_entry *arr;
432 int num_entries;
433 spinlock_t lock;
434};
435
436#define EHEA_PORT_UP 1
437#define EHEA_PORT_DOWN 0
438#define EHEA_PHY_LINK_UP 1
439#define EHEA_PHY_LINK_DOWN 0
440#define EHEA_MAX_PORT_RES 16
441struct ehea_port {
442 struct ehea_adapter *adapter; /* adapter that owns this port */
443 struct net_device *netdev;
444 struct rtnl_link_stats64 stats;
445 struct ehea_port_res port_res[EHEA_MAX_PORT_RES];
446 struct platform_device ofdev; /* Open Firmware Device */
447 struct ehea_mc_list *mc_list; /* Multicast MAC addresses */
448 struct ehea_eq *qp_eq;
449 struct work_struct reset_task;
450 struct delayed_work stats_work;
451 struct mutex port_lock;
452 char int_aff_name[EHEA_IRQ_NAME_SIZE];
453 int allmulti; /* Indicates IFF_ALLMULTI state */
454 int promisc; /* Indicates IFF_PROMISC state */
455 int num_mcs;
456 int resets;
457 unsigned long flags;
458 u64 mac_addr;
459 u32 logical_port_id;
460 u32 port_speed;
461 u32 msg_enable;
462 u32 sig_comp_iv;
463 u32 state;
464 u8 phy_link;
465 u8 full_duplex;
466 u8 autoneg;
467 u8 num_def_qps;
468 wait_queue_head_t swqe_avail_wq;
469 wait_queue_head_t restart_wq;
470};
471
472struct port_res_cfg {
473 int max_entries_rcq;
474 int max_entries_scq;
475 int max_entries_sq;
476 int max_entries_rq1;
477 int max_entries_rq2;
478 int max_entries_rq3;
479};
480
481enum ehea_flag_bits {
482 __EHEA_STOP_XFER,
483 __EHEA_DISABLE_PORT_RESET
484};
485
486void ehea_set_ethtool_ops(struct net_device *netdev);
487int ehea_sense_port_attr(struct ehea_port *port);
488int ehea_set_portspeed(struct ehea_port *port, u32 port_speed);
489
490#endif /* __EHEA_H__ */