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1/*
2 * Library implementing the most common irq chip callback functions
3 *
4 * Copyright (C) 2011, Thomas Gleixner
5 */
6#include <linux/io.h>
7#include <linux/irq.h>
8#include <linux/slab.h>
9#include <linux/export.h>
10#include <linux/irqdomain.h>
11#include <linux/interrupt.h>
12#include <linux/kernel_stat.h>
13#include <linux/syscore_ops.h>
14
15#include "internals.h"
16
17static LIST_HEAD(gc_list);
18static DEFINE_RAW_SPINLOCK(gc_lock);
19
20/**
21 * irq_gc_noop - NOOP function
22 * @d: irq_data
23 */
24void irq_gc_noop(struct irq_data *d)
25{
26}
27
28/**
29 * irq_gc_mask_disable_reg - Mask chip via disable register
30 * @d: irq_data
31 *
32 * Chip has separate enable/disable registers instead of a single mask
33 * register.
34 */
35void irq_gc_mask_disable_reg(struct irq_data *d)
36{
37 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
38 struct irq_chip_type *ct = irq_data_get_chip_type(d);
39 u32 mask = d->mask;
40
41 irq_gc_lock(gc);
42 irq_reg_writel(mask, gc->reg_base + ct->regs.disable);
43 *ct->mask_cache &= ~mask;
44 irq_gc_unlock(gc);
45}
46
47/**
48 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
49 * @d: irq_data
50 *
51 * Chip has a single mask register. Values of this register are cached
52 * and protected by gc->lock
53 */
54void irq_gc_mask_set_bit(struct irq_data *d)
55{
56 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
57 struct irq_chip_type *ct = irq_data_get_chip_type(d);
58 u32 mask = d->mask;
59
60 irq_gc_lock(gc);
61 *ct->mask_cache |= mask;
62 irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
63 irq_gc_unlock(gc);
64}
65EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
66
67/**
68 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
69 * @d: irq_data
70 *
71 * Chip has a single mask register. Values of this register are cached
72 * and protected by gc->lock
73 */
74void irq_gc_mask_clr_bit(struct irq_data *d)
75{
76 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
77 struct irq_chip_type *ct = irq_data_get_chip_type(d);
78 u32 mask = d->mask;
79
80 irq_gc_lock(gc);
81 *ct->mask_cache &= ~mask;
82 irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
83 irq_gc_unlock(gc);
84}
85EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
86
87/**
88 * irq_gc_unmask_enable_reg - Unmask chip via enable register
89 * @d: irq_data
90 *
91 * Chip has separate enable/disable registers instead of a single mask
92 * register.
93 */
94void irq_gc_unmask_enable_reg(struct irq_data *d)
95{
96 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
97 struct irq_chip_type *ct = irq_data_get_chip_type(d);
98 u32 mask = d->mask;
99
100 irq_gc_lock(gc);
101 irq_reg_writel(mask, gc->reg_base + ct->regs.enable);
102 *ct->mask_cache |= mask;
103 irq_gc_unlock(gc);
104}
105
106/**
107 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
108 * @d: irq_data
109 */
110void irq_gc_ack_set_bit(struct irq_data *d)
111{
112 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
113 struct irq_chip_type *ct = irq_data_get_chip_type(d);
114 u32 mask = d->mask;
115
116 irq_gc_lock(gc);
117 irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
118 irq_gc_unlock(gc);
119}
120EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
121
122/**
123 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
124 * @d: irq_data
125 */
126void irq_gc_ack_clr_bit(struct irq_data *d)
127{
128 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
129 struct irq_chip_type *ct = irq_data_get_chip_type(d);
130 u32 mask = ~d->mask;
131
132 irq_gc_lock(gc);
133 irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
134 irq_gc_unlock(gc);
135}
136
137/**
138 * irq_gc_mask_disable_reg_and_ack - Mask and ack pending interrupt
139 * @d: irq_data
140 */
141void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
142{
143 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
144 struct irq_chip_type *ct = irq_data_get_chip_type(d);
145 u32 mask = d->mask;
146
147 irq_gc_lock(gc);
148 irq_reg_writel(mask, gc->reg_base + ct->regs.mask);
149 irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
150 irq_gc_unlock(gc);
151}
152
153/**
154 * irq_gc_eoi - EOI interrupt
155 * @d: irq_data
156 */
157void irq_gc_eoi(struct irq_data *d)
158{
159 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
160 struct irq_chip_type *ct = irq_data_get_chip_type(d);
161 u32 mask = d->mask;
162
163 irq_gc_lock(gc);
164 irq_reg_writel(mask, gc->reg_base + ct->regs.eoi);
165 irq_gc_unlock(gc);
166}
167
168/**
169 * irq_gc_set_wake - Set/clr wake bit for an interrupt
170 * @d: irq_data
171 * @on: Indicates whether the wake bit should be set or cleared
172 *
173 * For chips where the wake from suspend functionality is not
174 * configured in a separate register and the wakeup active state is
175 * just stored in a bitmask.
176 */
177int irq_gc_set_wake(struct irq_data *d, unsigned int on)
178{
179 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
180 u32 mask = d->mask;
181
182 if (!(mask & gc->wake_enabled))
183 return -EINVAL;
184
185 irq_gc_lock(gc);
186 if (on)
187 gc->wake_active |= mask;
188 else
189 gc->wake_active &= ~mask;
190 irq_gc_unlock(gc);
191 return 0;
192}
193
194static void
195irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
196 int num_ct, unsigned int irq_base,
197 void __iomem *reg_base, irq_flow_handler_t handler)
198{
199 raw_spin_lock_init(&gc->lock);
200 gc->num_ct = num_ct;
201 gc->irq_base = irq_base;
202 gc->reg_base = reg_base;
203 gc->chip_types->chip.name = name;
204 gc->chip_types->handler = handler;
205}
206
207/**
208 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
209 * @name: Name of the irq chip
210 * @num_ct: Number of irq_chip_type instances associated with this
211 * @irq_base: Interrupt base nr for this chip
212 * @reg_base: Register base address (virtual)
213 * @handler: Default flow handler associated with this chip
214 *
215 * Returns an initialized irq_chip_generic structure. The chip defaults
216 * to the primary (index 0) irq_chip_type and @handler
217 */
218struct irq_chip_generic *
219irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
220 void __iomem *reg_base, irq_flow_handler_t handler)
221{
222 struct irq_chip_generic *gc;
223 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
224
225 gc = kzalloc(sz, GFP_KERNEL);
226 if (gc) {
227 irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
228 handler);
229 }
230 return gc;
231}
232EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
233
234static void
235irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
236{
237 struct irq_chip_type *ct = gc->chip_types;
238 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
239 int i;
240
241 for (i = 0; i < gc->num_ct; i++) {
242 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
243 mskptr = &ct[i].mask_cache_priv;
244 mskreg = ct[i].regs.mask;
245 }
246 ct[i].mask_cache = mskptr;
247 if (flags & IRQ_GC_INIT_MASK_CACHE)
248 *mskptr = irq_reg_readl(gc->reg_base + mskreg);
249 }
250}
251
252/**
253 * irq_alloc_domain_generic_chip - Allocate generic chips for an irq domain
254 * @d: irq domain for which to allocate chips
255 * @irqs_per_chip: Number of interrupts each chip handles
256 * @num_ct: Number of irq_chip_type instances associated with this
257 * @name: Name of the irq chip
258 * @handler: Default flow handler associated with these chips
259 * @clr: IRQ_* bits to clear in the mapping function
260 * @set: IRQ_* bits to set in the mapping function
261 * @gcflags: Generic chip specific setup flags
262 */
263int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
264 int num_ct, const char *name,
265 irq_flow_handler_t handler,
266 unsigned int clr, unsigned int set,
267 enum irq_gc_flags gcflags)
268{
269 struct irq_domain_chip_generic *dgc;
270 struct irq_chip_generic *gc;
271 int numchips, sz, i;
272 unsigned long flags;
273 void *tmp;
274
275 if (d->gc)
276 return -EBUSY;
277
278 numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
279 if (!numchips)
280 return -EINVAL;
281
282 /* Allocate a pointer, generic chip and chiptypes for each chip */
283 sz = sizeof(*dgc) + numchips * sizeof(gc);
284 sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type));
285
286 tmp = dgc = kzalloc(sz, GFP_KERNEL);
287 if (!dgc)
288 return -ENOMEM;
289 dgc->irqs_per_chip = irqs_per_chip;
290 dgc->num_chips = numchips;
291 dgc->irq_flags_to_set = set;
292 dgc->irq_flags_to_clear = clr;
293 dgc->gc_flags = gcflags;
294 d->gc = dgc;
295
296 /* Calc pointer to the first generic chip */
297 tmp += sizeof(*dgc) + numchips * sizeof(gc);
298 for (i = 0; i < numchips; i++) {
299 /* Store the pointer to the generic chip */
300 dgc->gc[i] = gc = tmp;
301 irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
302 NULL, handler);
303 gc->domain = d;
304 raw_spin_lock_irqsave(&gc_lock, flags);
305 list_add_tail(&gc->list, &gc_list);
306 raw_spin_unlock_irqrestore(&gc_lock, flags);
307 /* Calc pointer to the next generic chip */
308 tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
309 }
310 d->name = name;
311 return 0;
312}
313EXPORT_SYMBOL_GPL(irq_alloc_domain_generic_chips);
314
315/**
316 * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
317 * @d: irq domain pointer
318 * @hw_irq: Hardware interrupt number
319 */
320struct irq_chip_generic *
321irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
322{
323 struct irq_domain_chip_generic *dgc = d->gc;
324 int idx;
325
326 if (!dgc)
327 return NULL;
328 idx = hw_irq / dgc->irqs_per_chip;
329 if (idx >= dgc->num_chips)
330 return NULL;
331 return dgc->gc[idx];
332}
333EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
334
335/*
336 * Separate lockdep class for interrupt chip which can nest irq_desc
337 * lock.
338 */
339static struct lock_class_key irq_nested_lock_class;
340
341/*
342 * irq_map_generic_chip - Map a generic chip for an irq domain
343 */
344static int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
345 irq_hw_number_t hw_irq)
346{
347 struct irq_data *data = irq_get_irq_data(virq);
348 struct irq_domain_chip_generic *dgc = d->gc;
349 struct irq_chip_generic *gc;
350 struct irq_chip_type *ct;
351 struct irq_chip *chip;
352 unsigned long flags;
353 int idx;
354
355 if (!d->gc)
356 return -ENODEV;
357
358 idx = hw_irq / dgc->irqs_per_chip;
359 if (idx >= dgc->num_chips)
360 return -EINVAL;
361 gc = dgc->gc[idx];
362
363 idx = hw_irq % dgc->irqs_per_chip;
364
365 if (test_bit(idx, &gc->unused))
366 return -ENOTSUPP;
367
368 if (test_bit(idx, &gc->installed))
369 return -EBUSY;
370
371 ct = gc->chip_types;
372 chip = &ct->chip;
373
374 /* We only init the cache for the first mapping of a generic chip */
375 if (!gc->installed) {
376 raw_spin_lock_irqsave(&gc->lock, flags);
377 irq_gc_init_mask_cache(gc, dgc->gc_flags);
378 raw_spin_unlock_irqrestore(&gc->lock, flags);
379 }
380
381 /* Mark the interrupt as installed */
382 set_bit(idx, &gc->installed);
383
384 if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
385 irq_set_lockdep_class(virq, &irq_nested_lock_class);
386
387 if (chip->irq_calc_mask)
388 chip->irq_calc_mask(data);
389 else
390 data->mask = 1 << idx;
391
392 irq_set_chip_and_handler(virq, chip, ct->handler);
393 irq_set_chip_data(virq, gc);
394 irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
395 return 0;
396}
397
398struct irq_domain_ops irq_generic_chip_ops = {
399 .map = irq_map_generic_chip,
400 .xlate = irq_domain_xlate_onetwocell,
401};
402EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
403
404/**
405 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
406 * @gc: Generic irq chip holding all data
407 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
408 * @flags: Flags for initialization
409 * @clr: IRQ_* bits to clear
410 * @set: IRQ_* bits to set
411 *
412 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
413 * initializes all interrupts to the primary irq_chip_type and its
414 * associated handler.
415 */
416void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
417 enum irq_gc_flags flags, unsigned int clr,
418 unsigned int set)
419{
420 struct irq_chip_type *ct = gc->chip_types;
421 struct irq_chip *chip = &ct->chip;
422 unsigned int i;
423
424 raw_spin_lock(&gc_lock);
425 list_add_tail(&gc->list, &gc_list);
426 raw_spin_unlock(&gc_lock);
427
428 irq_gc_init_mask_cache(gc, flags);
429
430 for (i = gc->irq_base; msk; msk >>= 1, i++) {
431 if (!(msk & 0x01))
432 continue;
433
434 if (flags & IRQ_GC_INIT_NESTED_LOCK)
435 irq_set_lockdep_class(i, &irq_nested_lock_class);
436
437 if (!(flags & IRQ_GC_NO_MASK)) {
438 struct irq_data *d = irq_get_irq_data(i);
439
440 if (chip->irq_calc_mask)
441 chip->irq_calc_mask(d);
442 else
443 d->mask = 1 << (i - gc->irq_base);
444 }
445 irq_set_chip_and_handler(i, chip, ct->handler);
446 irq_set_chip_data(i, gc);
447 irq_modify_status(i, clr, set);
448 }
449 gc->irq_cnt = i - gc->irq_base;
450}
451EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
452
453/**
454 * irq_setup_alt_chip - Switch to alternative chip
455 * @d: irq_data for this interrupt
456 * @type: Flow type to be initialized
457 *
458 * Only to be called from chip->irq_set_type() callbacks.
459 */
460int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
461{
462 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
463 struct irq_chip_type *ct = gc->chip_types;
464 unsigned int i;
465
466 for (i = 0; i < gc->num_ct; i++, ct++) {
467 if (ct->type & type) {
468 d->chip = &ct->chip;
469 irq_data_to_desc(d)->handle_irq = ct->handler;
470 return 0;
471 }
472 }
473 return -EINVAL;
474}
475EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
476
477/**
478 * irq_remove_generic_chip - Remove a chip
479 * @gc: Generic irq chip holding all data
480 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
481 * @clr: IRQ_* bits to clear
482 * @set: IRQ_* bits to set
483 *
484 * Remove up to 32 interrupts starting from gc->irq_base.
485 */
486void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
487 unsigned int clr, unsigned int set)
488{
489 unsigned int i = gc->irq_base;
490
491 raw_spin_lock(&gc_lock);
492 list_del(&gc->list);
493 raw_spin_unlock(&gc_lock);
494
495 for (; msk; msk >>= 1, i++) {
496 if (!(msk & 0x01))
497 continue;
498
499 /* Remove handler first. That will mask the irq line */
500 irq_set_handler(i, NULL);
501 irq_set_chip(i, &no_irq_chip);
502 irq_set_chip_data(i, NULL);
503 irq_modify_status(i, clr, set);
504 }
505}
506EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
507
508static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
509{
510 unsigned int virq;
511
512 if (!gc->domain)
513 return irq_get_irq_data(gc->irq_base);
514
515 /*
516 * We don't know which of the irqs has been actually
517 * installed. Use the first one.
518 */
519 if (!gc->installed)
520 return NULL;
521
522 virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
523 return virq ? irq_get_irq_data(virq) : NULL;
524}
525
526#ifdef CONFIG_PM
527static int irq_gc_suspend(void)
528{
529 struct irq_chip_generic *gc;
530
531 list_for_each_entry(gc, &gc_list, list) {
532 struct irq_chip_type *ct = gc->chip_types;
533
534 if (ct->chip.irq_suspend) {
535 struct irq_data *data = irq_gc_get_irq_data(gc);
536
537 if (data)
538 ct->chip.irq_suspend(data);
539 }
540 }
541 return 0;
542}
543
544static void irq_gc_resume(void)
545{
546 struct irq_chip_generic *gc;
547
548 list_for_each_entry(gc, &gc_list, list) {
549 struct irq_chip_type *ct = gc->chip_types;
550
551 if (ct->chip.irq_resume) {
552 struct irq_data *data = irq_gc_get_irq_data(gc);
553
554 if (data)
555 ct->chip.irq_resume(data);
556 }
557 }
558}
559#else
560#define irq_gc_suspend NULL
561#define irq_gc_resume NULL
562#endif
563
564static void irq_gc_shutdown(void)
565{
566 struct irq_chip_generic *gc;
567
568 list_for_each_entry(gc, &gc_list, list) {
569 struct irq_chip_type *ct = gc->chip_types;
570
571 if (ct->chip.irq_pm_shutdown) {
572 struct irq_data *data = irq_gc_get_irq_data(gc);
573
574 if (data)
575 ct->chip.irq_pm_shutdown(data);
576 }
577 }
578}
579
580static struct syscore_ops irq_gc_syscore_ops = {
581 .suspend = irq_gc_suspend,
582 .resume = irq_gc_resume,
583 .shutdown = irq_gc_shutdown,
584};
585
586static int __init irq_gc_init_ops(void)
587{
588 register_syscore_ops(&irq_gc_syscore_ops);
589 return 0;
590}
591device_initcall(irq_gc_init_ops);
1/*
2 * Library implementing the most common irq chip callback functions
3 *
4 * Copyright (C) 2011, Thomas Gleixner
5 */
6#include <linux/io.h>
7#include <linux/irq.h>
8#include <linux/slab.h>
9#include <linux/interrupt.h>
10#include <linux/kernel_stat.h>
11#include <linux/syscore_ops.h>
12
13#include "internals.h"
14
15static LIST_HEAD(gc_list);
16static DEFINE_RAW_SPINLOCK(gc_lock);
17
18static inline struct irq_chip_regs *cur_regs(struct irq_data *d)
19{
20 return &container_of(d->chip, struct irq_chip_type, chip)->regs;
21}
22
23/**
24 * irq_gc_noop - NOOP function
25 * @d: irq_data
26 */
27void irq_gc_noop(struct irq_data *d)
28{
29}
30
31/**
32 * irq_gc_mask_disable_reg - Mask chip via disable register
33 * @d: irq_data
34 *
35 * Chip has separate enable/disable registers instead of a single mask
36 * register.
37 */
38void irq_gc_mask_disable_reg(struct irq_data *d)
39{
40 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
41 u32 mask = 1 << (d->irq - gc->irq_base);
42
43 irq_gc_lock(gc);
44 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->disable);
45 gc->mask_cache &= ~mask;
46 irq_gc_unlock(gc);
47}
48
49/**
50 * irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register
51 * @d: irq_data
52 *
53 * Chip has a single mask register. Values of this register are cached
54 * and protected by gc->lock
55 */
56void irq_gc_mask_set_bit(struct irq_data *d)
57{
58 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
59 u32 mask = 1 << (d->irq - gc->irq_base);
60
61 irq_gc_lock(gc);
62 gc->mask_cache |= mask;
63 irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);
64 irq_gc_unlock(gc);
65}
66
67/**
68 * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register
69 * @d: irq_data
70 *
71 * Chip has a single mask register. Values of this register are cached
72 * and protected by gc->lock
73 */
74void irq_gc_mask_clr_bit(struct irq_data *d)
75{
76 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
77 u32 mask = 1 << (d->irq - gc->irq_base);
78
79 irq_gc_lock(gc);
80 gc->mask_cache &= ~mask;
81 irq_reg_writel(gc->mask_cache, gc->reg_base + cur_regs(d)->mask);
82 irq_gc_unlock(gc);
83}
84
85/**
86 * irq_gc_unmask_enable_reg - Unmask chip via enable register
87 * @d: irq_data
88 *
89 * Chip has separate enable/disable registers instead of a single mask
90 * register.
91 */
92void irq_gc_unmask_enable_reg(struct irq_data *d)
93{
94 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
95 u32 mask = 1 << (d->irq - gc->irq_base);
96
97 irq_gc_lock(gc);
98 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->enable);
99 gc->mask_cache |= mask;
100 irq_gc_unlock(gc);
101}
102
103/**
104 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
105 * @d: irq_data
106 */
107void irq_gc_ack_set_bit(struct irq_data *d)
108{
109 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
110 u32 mask = 1 << (d->irq - gc->irq_base);
111
112 irq_gc_lock(gc);
113 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
114 irq_gc_unlock(gc);
115}
116
117/**
118 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
119 * @d: irq_data
120 */
121void irq_gc_ack_clr_bit(struct irq_data *d)
122{
123 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
124 u32 mask = ~(1 << (d->irq - gc->irq_base));
125
126 irq_gc_lock(gc);
127 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
128 irq_gc_unlock(gc);
129}
130
131/**
132 * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
133 * @d: irq_data
134 */
135void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
136{
137 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
138 u32 mask = 1 << (d->irq - gc->irq_base);
139
140 irq_gc_lock(gc);
141 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->mask);
142 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack);
143 irq_gc_unlock(gc);
144}
145
146/**
147 * irq_gc_eoi - EOI interrupt
148 * @d: irq_data
149 */
150void irq_gc_eoi(struct irq_data *d)
151{
152 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
153 u32 mask = 1 << (d->irq - gc->irq_base);
154
155 irq_gc_lock(gc);
156 irq_reg_writel(mask, gc->reg_base + cur_regs(d)->eoi);
157 irq_gc_unlock(gc);
158}
159
160/**
161 * irq_gc_set_wake - Set/clr wake bit for an interrupt
162 * @d: irq_data
163 *
164 * For chips where the wake from suspend functionality is not
165 * configured in a separate register and the wakeup active state is
166 * just stored in a bitmask.
167 */
168int irq_gc_set_wake(struct irq_data *d, unsigned int on)
169{
170 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
171 u32 mask = 1 << (d->irq - gc->irq_base);
172
173 if (!(mask & gc->wake_enabled))
174 return -EINVAL;
175
176 irq_gc_lock(gc);
177 if (on)
178 gc->wake_active |= mask;
179 else
180 gc->wake_active &= ~mask;
181 irq_gc_unlock(gc);
182 return 0;
183}
184
185/**
186 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
187 * @name: Name of the irq chip
188 * @num_ct: Number of irq_chip_type instances associated with this
189 * @irq_base: Interrupt base nr for this chip
190 * @reg_base: Register base address (virtual)
191 * @handler: Default flow handler associated with this chip
192 *
193 * Returns an initialized irq_chip_generic structure. The chip defaults
194 * to the primary (index 0) irq_chip_type and @handler
195 */
196struct irq_chip_generic *
197irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
198 void __iomem *reg_base, irq_flow_handler_t handler)
199{
200 struct irq_chip_generic *gc;
201 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
202
203 gc = kzalloc(sz, GFP_KERNEL);
204 if (gc) {
205 raw_spin_lock_init(&gc->lock);
206 gc->num_ct = num_ct;
207 gc->irq_base = irq_base;
208 gc->reg_base = reg_base;
209 gc->chip_types->chip.name = name;
210 gc->chip_types->handler = handler;
211 }
212 return gc;
213}
214
215/*
216 * Separate lockdep class for interrupt chip which can nest irq_desc
217 * lock.
218 */
219static struct lock_class_key irq_nested_lock_class;
220
221/**
222 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
223 * @gc: Generic irq chip holding all data
224 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
225 * @flags: Flags for initialization
226 * @clr: IRQ_* bits to clear
227 * @set: IRQ_* bits to set
228 *
229 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
230 * initializes all interrupts to the primary irq_chip_type and its
231 * associated handler.
232 */
233void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
234 enum irq_gc_flags flags, unsigned int clr,
235 unsigned int set)
236{
237 struct irq_chip_type *ct = gc->chip_types;
238 unsigned int i;
239
240 raw_spin_lock(&gc_lock);
241 list_add_tail(&gc->list, &gc_list);
242 raw_spin_unlock(&gc_lock);
243
244 /* Init mask cache ? */
245 if (flags & IRQ_GC_INIT_MASK_CACHE)
246 gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask);
247
248 for (i = gc->irq_base; msk; msk >>= 1, i++) {
249 if (!(msk & 0x01))
250 continue;
251
252 if (flags & IRQ_GC_INIT_NESTED_LOCK)
253 irq_set_lockdep_class(i, &irq_nested_lock_class);
254
255 irq_set_chip_and_handler(i, &ct->chip, ct->handler);
256 irq_set_chip_data(i, gc);
257 irq_modify_status(i, clr, set);
258 }
259 gc->irq_cnt = i - gc->irq_base;
260}
261
262/**
263 * irq_setup_alt_chip - Switch to alternative chip
264 * @d: irq_data for this interrupt
265 * @type Flow type to be initialized
266 *
267 * Only to be called from chip->irq_set_type() callbacks.
268 */
269int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
270{
271 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
272 struct irq_chip_type *ct = gc->chip_types;
273 unsigned int i;
274
275 for (i = 0; i < gc->num_ct; i++, ct++) {
276 if (ct->type & type) {
277 d->chip = &ct->chip;
278 irq_data_to_desc(d)->handle_irq = ct->handler;
279 return 0;
280 }
281 }
282 return -EINVAL;
283}
284
285/**
286 * irq_remove_generic_chip - Remove a chip
287 * @gc: Generic irq chip holding all data
288 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
289 * @clr: IRQ_* bits to clear
290 * @set: IRQ_* bits to set
291 *
292 * Remove up to 32 interrupts starting from gc->irq_base.
293 */
294void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
295 unsigned int clr, unsigned int set)
296{
297 unsigned int i = gc->irq_base;
298
299 raw_spin_lock(&gc_lock);
300 list_del(&gc->list);
301 raw_spin_unlock(&gc_lock);
302
303 for (; msk; msk >>= 1, i++) {
304 if (!(msk & 0x01))
305 continue;
306
307 /* Remove handler first. That will mask the irq line */
308 irq_set_handler(i, NULL);
309 irq_set_chip(i, &no_irq_chip);
310 irq_set_chip_data(i, NULL);
311 irq_modify_status(i, clr, set);
312 }
313}
314
315#ifdef CONFIG_PM
316static int irq_gc_suspend(void)
317{
318 struct irq_chip_generic *gc;
319
320 list_for_each_entry(gc, &gc_list, list) {
321 struct irq_chip_type *ct = gc->chip_types;
322
323 if (ct->chip.irq_suspend)
324 ct->chip.irq_suspend(irq_get_irq_data(gc->irq_base));
325 }
326 return 0;
327}
328
329static void irq_gc_resume(void)
330{
331 struct irq_chip_generic *gc;
332
333 list_for_each_entry(gc, &gc_list, list) {
334 struct irq_chip_type *ct = gc->chip_types;
335
336 if (ct->chip.irq_resume)
337 ct->chip.irq_resume(irq_get_irq_data(gc->irq_base));
338 }
339}
340#else
341#define irq_gc_suspend NULL
342#define irq_gc_resume NULL
343#endif
344
345static void irq_gc_shutdown(void)
346{
347 struct irq_chip_generic *gc;
348
349 list_for_each_entry(gc, &gc_list, list) {
350 struct irq_chip_type *ct = gc->chip_types;
351
352 if (ct->chip.irq_pm_shutdown)
353 ct->chip.irq_pm_shutdown(irq_get_irq_data(gc->irq_base));
354 }
355}
356
357static struct syscore_ops irq_gc_syscore_ops = {
358 .suspend = irq_gc_suspend,
359 .resume = irq_gc_resume,
360 .shutdown = irq_gc_shutdown,
361};
362
363static int __init irq_gc_init_ops(void)
364{
365 register_syscore_ops(&irq_gc_syscore_ops);
366 return 0;
367}
368device_initcall(irq_gc_init_ops);