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1/*
2 * xHCI host controller driver PCI Bus Glue.
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26
27#include "xhci.h"
28#include "xhci-trace.h"
29
30/* Device for a quirk */
31#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
32#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
33#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
34
35#define PCI_VENDOR_ID_ETRON 0x1b6f
36#define PCI_DEVICE_ID_ASROCK_P67 0x7023
37
38#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
39#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
40
41static const char hcd_name[] = "xhci_hcd";
42
43/* called after powerup, by probe or system-pm "wakeup" */
44static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
45{
46 /*
47 * TODO: Implement finding debug ports later.
48 * TODO: see if there are any quirks that need to be added to handle
49 * new extended capabilities.
50 */
51
52 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
53 if (!pci_set_mwi(pdev))
54 xhci_dbg(xhci, "MWI active\n");
55
56 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
57 return 0;
58}
59
60static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
61{
62 struct pci_dev *pdev = to_pci_dev(dev);
63
64 /* Look for vendor-specific quirks */
65 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
66 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
67 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
68 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
69 pdev->revision == 0x0) {
70 xhci->quirks |= XHCI_RESET_EP_QUIRK;
71 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
72 "QUIRK: Fresco Logic xHC needs configure"
73 " endpoint cmd after reset endpoint");
74 }
75 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
76 pdev->revision == 0x4) {
77 xhci->quirks |= XHCI_SLOW_SUSPEND;
78 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
79 "QUIRK: Fresco Logic xHC revision %u"
80 "must be suspended extra slowly",
81 pdev->revision);
82 }
83 /* Fresco Logic confirms: all revisions of this chip do not
84 * support MSI, even though some of them claim to in their PCI
85 * capabilities.
86 */
87 xhci->quirks |= XHCI_BROKEN_MSI;
88 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
89 "QUIRK: Fresco Logic revision %u "
90 "has broken MSI implementation",
91 pdev->revision);
92 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
93 }
94
95 if (pdev->vendor == PCI_VENDOR_ID_NEC)
96 xhci->quirks |= XHCI_NEC_HOST;
97
98 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
99 xhci->quirks |= XHCI_AMD_0x96_HOST;
100
101 /* AMD PLL quirk */
102 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
103 xhci->quirks |= XHCI_AMD_PLL_FIX;
104 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
105 xhci->quirks |= XHCI_LPM_SUPPORT;
106 xhci->quirks |= XHCI_INTEL_HOST;
107 }
108 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
109 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
110 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
111 xhci->limit_active_eps = 64;
112 xhci->quirks |= XHCI_SW_BW_CHECKING;
113 /*
114 * PPT desktop boards DH77EB and DH77DF will power back on after
115 * a few seconds of being shutdown. The fix for this is to
116 * switch the ports from xHCI to EHCI on shutdown. We can't use
117 * DMI information to find those particular boards (since each
118 * vendor will change the board name), so we have to key off all
119 * PPT chipsets.
120 */
121 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
122 xhci->quirks |= XHCI_AVOID_BEI;
123 }
124 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
125 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI ||
126 pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI)) {
127 /* Workaround for occasional spurious wakeups from S5 (or
128 * any other sleep) on Haswell machines with LPT and LPT-LP
129 * with the new Intel BIOS
130 */
131 /* Limit the quirk to only known vendors, as this triggers
132 * yet another BIOS bug on some other machines
133 * https://bugzilla.kernel.org/show_bug.cgi?id=66171
134 */
135 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)
136 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
137
138 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
139 }
140 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
141 pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
142 xhci->quirks |= XHCI_RESET_ON_RESUME;
143 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
144 "QUIRK: Resetting on resume");
145 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
146 }
147 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
148 pdev->device == 0x0015)
149 xhci->quirks |= XHCI_RESET_ON_RESUME;
150 if (pdev->vendor == PCI_VENDOR_ID_VIA)
151 xhci->quirks |= XHCI_RESET_ON_RESUME;
152}
153
154/* called during probe() after chip reset completes */
155static int xhci_pci_setup(struct usb_hcd *hcd)
156{
157 struct xhci_hcd *xhci;
158 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
159 int retval;
160
161 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
162 if (retval)
163 return retval;
164
165 xhci = hcd_to_xhci(hcd);
166 if (!usb_hcd_is_primary_hcd(hcd))
167 return 0;
168
169 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
170 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
171
172 /* Find any debug ports */
173 retval = xhci_pci_reinit(xhci, pdev);
174 if (!retval)
175 return retval;
176
177 kfree(xhci);
178 return retval;
179}
180
181/*
182 * We need to register our own PCI probe function (instead of the USB core's
183 * function) in order to create a second roothub under xHCI.
184 */
185static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
186{
187 int retval;
188 struct xhci_hcd *xhci;
189 struct hc_driver *driver;
190 struct usb_hcd *hcd;
191
192 driver = (struct hc_driver *)id->driver_data;
193
194 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
195 pm_runtime_get_noresume(&dev->dev);
196
197 /* Register the USB 2.0 roothub.
198 * FIXME: USB core must know to register the USB 2.0 roothub first.
199 * This is sort of silly, because we could just set the HCD driver flags
200 * to say USB 2.0, but I'm not sure what the implications would be in
201 * the other parts of the HCD code.
202 */
203 retval = usb_hcd_pci_probe(dev, id);
204
205 if (retval)
206 goto put_runtime_pm;
207
208 /* USB 2.0 roothub is stored in the PCI device now. */
209 hcd = dev_get_drvdata(&dev->dev);
210 xhci = hcd_to_xhci(hcd);
211 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
212 pci_name(dev), hcd);
213 if (!xhci->shared_hcd) {
214 retval = -ENOMEM;
215 goto dealloc_usb2_hcd;
216 }
217
218 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
219 * is called by usb_add_hcd().
220 */
221 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
222
223 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
224 IRQF_SHARED);
225 if (retval)
226 goto put_usb3_hcd;
227 /* Roothub already marked as USB 3.0 speed */
228
229 if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
230 xhci->shared_hcd->can_do_streams = 1;
231
232 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
233 pm_runtime_put_noidle(&dev->dev);
234
235 return 0;
236
237put_usb3_hcd:
238 usb_put_hcd(xhci->shared_hcd);
239dealloc_usb2_hcd:
240 usb_hcd_pci_remove(dev);
241put_runtime_pm:
242 pm_runtime_put_noidle(&dev->dev);
243 return retval;
244}
245
246static void xhci_pci_remove(struct pci_dev *dev)
247{
248 struct xhci_hcd *xhci;
249
250 xhci = hcd_to_xhci(pci_get_drvdata(dev));
251 if (xhci->shared_hcd) {
252 usb_remove_hcd(xhci->shared_hcd);
253 usb_put_hcd(xhci->shared_hcd);
254 }
255 usb_hcd_pci_remove(dev);
256
257 /* Workaround for spurious wakeups at shutdown with HSW */
258 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
259 pci_set_power_state(dev, PCI_D3hot);
260
261 kfree(xhci);
262}
263
264#ifdef CONFIG_PM
265static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
266{
267 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
268 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
269
270 /*
271 * Systems with the TI redriver that loses port status change events
272 * need to have the registers polled during D3, so avoid D3cold.
273 */
274 if (xhci_compliance_mode_recovery_timer_quirk_check())
275 pdev->no_d3cold = true;
276
277 return xhci_suspend(xhci);
278}
279
280static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
281{
282 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
283 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
284 int retval = 0;
285
286 /* The BIOS on systems with the Intel Panther Point chipset may or may
287 * not support xHCI natively. That means that during system resume, it
288 * may switch the ports back to EHCI so that users can use their
289 * keyboard to select a kernel from GRUB after resume from hibernate.
290 *
291 * The BIOS is supposed to remember whether the OS had xHCI ports
292 * enabled before resume, and switch the ports back to xHCI when the
293 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
294 * writers.
295 *
296 * Unconditionally switch the ports back to xHCI after a system resume.
297 * It should not matter whether the EHCI or xHCI controller is
298 * resumed first. It's enough to do the switchover in xHCI because
299 * USB core won't notice anything as the hub driver doesn't start
300 * running again until after all the devices (including both EHCI and
301 * xHCI host controllers) have been resumed.
302 */
303
304 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
305 usb_enable_intel_xhci_ports(pdev);
306
307 retval = xhci_resume(xhci, hibernated);
308 return retval;
309}
310#endif /* CONFIG_PM */
311
312static const struct hc_driver xhci_pci_hc_driver = {
313 .description = hcd_name,
314 .product_desc = "xHCI Host Controller",
315 .hcd_priv_size = sizeof(struct xhci_hcd *),
316
317 /*
318 * generic hardware linkage
319 */
320 .irq = xhci_irq,
321 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
322
323 /*
324 * basic lifecycle operations
325 */
326 .reset = xhci_pci_setup,
327 .start = xhci_run,
328#ifdef CONFIG_PM
329 .pci_suspend = xhci_pci_suspend,
330 .pci_resume = xhci_pci_resume,
331#endif
332 .stop = xhci_stop,
333 .shutdown = xhci_shutdown,
334
335 /*
336 * managing i/o requests and associated device resources
337 */
338 .urb_enqueue = xhci_urb_enqueue,
339 .urb_dequeue = xhci_urb_dequeue,
340 .alloc_dev = xhci_alloc_dev,
341 .free_dev = xhci_free_dev,
342 .alloc_streams = xhci_alloc_streams,
343 .free_streams = xhci_free_streams,
344 .add_endpoint = xhci_add_endpoint,
345 .drop_endpoint = xhci_drop_endpoint,
346 .endpoint_reset = xhci_endpoint_reset,
347 .check_bandwidth = xhci_check_bandwidth,
348 .reset_bandwidth = xhci_reset_bandwidth,
349 .address_device = xhci_address_device,
350 .enable_device = xhci_enable_device,
351 .update_hub_device = xhci_update_hub_device,
352 .reset_device = xhci_discover_or_reset_device,
353
354 /*
355 * scheduling support
356 */
357 .get_frame_number = xhci_get_frame,
358
359 /* Root hub support */
360 .hub_control = xhci_hub_control,
361 .hub_status_data = xhci_hub_status_data,
362 .bus_suspend = xhci_bus_suspend,
363 .bus_resume = xhci_bus_resume,
364 /*
365 * call back when device connected and addressed
366 */
367 .update_device = xhci_update_device,
368 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
369 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
370 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
371 .find_raw_port_number = xhci_find_raw_port_number,
372};
373
374/*-------------------------------------------------------------------------*/
375
376/* PCI driver selection metadata; PCI hotplugging uses this */
377static const struct pci_device_id pci_ids[] = { {
378 /* handle any USB 3.0 xHCI controller */
379 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
380 .driver_data = (unsigned long) &xhci_pci_hc_driver,
381 },
382 { /* end: all zeroes */ }
383};
384MODULE_DEVICE_TABLE(pci, pci_ids);
385
386/* pci driver glue; this is a "new style" PCI driver module */
387static struct pci_driver xhci_pci_driver = {
388 .name = (char *) hcd_name,
389 .id_table = pci_ids,
390
391 .probe = xhci_pci_probe,
392 .remove = xhci_pci_remove,
393 /* suspend and resume implemented later */
394
395 .shutdown = usb_hcd_pci_shutdown,
396#ifdef CONFIG_PM
397 .driver = {
398 .pm = &usb_hcd_pci_pm_ops
399 },
400#endif
401};
402
403int __init xhci_register_pci(void)
404{
405 return pci_register_driver(&xhci_pci_driver);
406}
407
408void xhci_unregister_pci(void)
409{
410 pci_unregister_driver(&xhci_pci_driver);
411}
1/*
2 * xHCI host controller driver PCI Bus Glue.
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
24#include <linux/slab.h>
25
26#include "xhci.h"
27
28/* Device for a quirk */
29#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
30#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
31
32#define PCI_VENDOR_ID_ETRON 0x1b6f
33#define PCI_DEVICE_ID_ASROCK_P67 0x7023
34
35static const char hcd_name[] = "xhci_hcd";
36
37/* called after powerup, by probe or system-pm "wakeup" */
38static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
39{
40 /*
41 * TODO: Implement finding debug ports later.
42 * TODO: see if there are any quirks that need to be added to handle
43 * new extended capabilities.
44 */
45
46 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
47 if (!pci_set_mwi(pdev))
48 xhci_dbg(xhci, "MWI active\n");
49
50 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
51 return 0;
52}
53
54/* called during probe() after chip reset completes */
55static int xhci_pci_setup(struct usb_hcd *hcd)
56{
57 struct xhci_hcd *xhci;
58 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
59 int retval;
60 u32 temp;
61
62 hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
63
64 if (usb_hcd_is_primary_hcd(hcd)) {
65 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
66 if (!xhci)
67 return -ENOMEM;
68 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
69 xhci->main_hcd = hcd;
70 /* Mark the first roothub as being USB 2.0.
71 * The xHCI driver will register the USB 3.0 roothub.
72 */
73 hcd->speed = HCD_USB2;
74 hcd->self.root_hub->speed = USB_SPEED_HIGH;
75 /*
76 * USB 2.0 roothub under xHCI has an integrated TT,
77 * (rate matching hub) as opposed to having an OHCI/UHCI
78 * companion controller.
79 */
80 hcd->has_tt = 1;
81 } else {
82 /* xHCI private pointer was set in xhci_pci_probe for the second
83 * registered roothub.
84 */
85 xhci = hcd_to_xhci(hcd);
86 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
87 if (HCC_64BIT_ADDR(temp)) {
88 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
89 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
90 } else {
91 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
92 }
93 return 0;
94 }
95
96 xhci->cap_regs = hcd->regs;
97 xhci->op_regs = hcd->regs +
98 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
99 xhci->run_regs = hcd->regs +
100 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
101 /* Cache read-only capability registers */
102 xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
103 xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
104 xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
105 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
106 xhci->hci_version = HC_VERSION(xhci->hcc_params);
107 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
108 xhci_print_registers(xhci);
109
110 /* Look for vendor-specific quirks */
111 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
112 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) {
113 if (pdev->revision == 0x0) {
114 xhci->quirks |= XHCI_RESET_EP_QUIRK;
115 xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
116 " endpoint cmd after reset endpoint\n");
117 }
118 /* Fresco Logic confirms: all revisions of this chip do not
119 * support MSI, even though some of them claim to in their PCI
120 * capabilities.
121 */
122 xhci->quirks |= XHCI_BROKEN_MSI;
123 xhci_dbg(xhci, "QUIRK: Fresco Logic revision %u "
124 "has broken MSI implementation\n",
125 pdev->revision);
126 }
127
128 if (pdev->vendor == PCI_VENDOR_ID_NEC)
129 xhci->quirks |= XHCI_NEC_HOST;
130
131 /* AMD PLL quirk */
132 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
133 xhci->quirks |= XHCI_AMD_PLL_FIX;
134 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
135 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
136 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
137 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
138 xhci->limit_active_eps = 64;
139 }
140 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
141 pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
142 xhci->quirks |= XHCI_RESET_ON_RESUME;
143 xhci_dbg(xhci, "QUIRK: Resetting on resume\n");
144 }
145
146 /* Make sure the HC is halted. */
147 retval = xhci_halt(xhci);
148 if (retval)
149 goto error;
150
151 xhci_dbg(xhci, "Resetting HCD\n");
152 /* Reset the internal HC memory state and registers. */
153 retval = xhci_reset(xhci);
154 if (retval)
155 goto error;
156 xhci_dbg(xhci, "Reset complete\n");
157
158 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
159 if (HCC_64BIT_ADDR(temp)) {
160 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
161 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
162 } else {
163 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
164 }
165
166 xhci_dbg(xhci, "Calling HCD init\n");
167 /* Initialize HCD and host controller data structures. */
168 retval = xhci_init(hcd);
169 if (retval)
170 goto error;
171 xhci_dbg(xhci, "Called HCD init\n");
172
173 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
174 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
175
176 /* Find any debug ports */
177 retval = xhci_pci_reinit(xhci, pdev);
178 if (!retval)
179 return retval;
180
181error:
182 kfree(xhci);
183 return retval;
184}
185
186/*
187 * We need to register our own PCI probe function (instead of the USB core's
188 * function) in order to create a second roothub under xHCI.
189 */
190static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
191{
192 int retval;
193 struct xhci_hcd *xhci;
194 struct hc_driver *driver;
195 struct usb_hcd *hcd;
196
197 driver = (struct hc_driver *)id->driver_data;
198 /* Register the USB 2.0 roothub.
199 * FIXME: USB core must know to register the USB 2.0 roothub first.
200 * This is sort of silly, because we could just set the HCD driver flags
201 * to say USB 2.0, but I'm not sure what the implications would be in
202 * the other parts of the HCD code.
203 */
204 retval = usb_hcd_pci_probe(dev, id);
205
206 if (retval)
207 return retval;
208
209 /* USB 2.0 roothub is stored in the PCI device now. */
210 hcd = dev_get_drvdata(&dev->dev);
211 xhci = hcd_to_xhci(hcd);
212 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
213 pci_name(dev), hcd);
214 if (!xhci->shared_hcd) {
215 retval = -ENOMEM;
216 goto dealloc_usb2_hcd;
217 }
218
219 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
220 * is called by usb_add_hcd().
221 */
222 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
223
224 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
225 IRQF_DISABLED | IRQF_SHARED);
226 if (retval)
227 goto put_usb3_hcd;
228 /* Roothub already marked as USB 3.0 speed */
229 return 0;
230
231put_usb3_hcd:
232 usb_put_hcd(xhci->shared_hcd);
233dealloc_usb2_hcd:
234 usb_hcd_pci_remove(dev);
235 return retval;
236}
237
238static void xhci_pci_remove(struct pci_dev *dev)
239{
240 struct xhci_hcd *xhci;
241
242 xhci = hcd_to_xhci(pci_get_drvdata(dev));
243 if (xhci->shared_hcd) {
244 usb_remove_hcd(xhci->shared_hcd);
245 usb_put_hcd(xhci->shared_hcd);
246 }
247 usb_hcd_pci_remove(dev);
248 kfree(xhci);
249}
250
251#ifdef CONFIG_PM
252static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
253{
254 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
255 int retval = 0;
256
257 if (hcd->state != HC_STATE_SUSPENDED ||
258 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
259 return -EINVAL;
260
261 retval = xhci_suspend(xhci);
262
263 return retval;
264}
265
266static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
267{
268 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
269 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
270 int retval = 0;
271
272 /* The BIOS on systems with the Intel Panther Point chipset may or may
273 * not support xHCI natively. That means that during system resume, it
274 * may switch the ports back to EHCI so that users can use their
275 * keyboard to select a kernel from GRUB after resume from hibernate.
276 *
277 * The BIOS is supposed to remember whether the OS had xHCI ports
278 * enabled before resume, and switch the ports back to xHCI when the
279 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
280 * writers.
281 *
282 * Unconditionally switch the ports back to xHCI after a system resume.
283 * We can't tell whether the EHCI or xHCI controller will be resumed
284 * first, so we have to do the port switchover in both drivers. Writing
285 * a '1' to the port switchover registers should have no effect if the
286 * port was already switched over.
287 */
288 if (usb_is_intel_switchable_xhci(pdev))
289 usb_enable_xhci_ports(pdev);
290
291 retval = xhci_resume(xhci, hibernated);
292 return retval;
293}
294#endif /* CONFIG_PM */
295
296static const struct hc_driver xhci_pci_hc_driver = {
297 .description = hcd_name,
298 .product_desc = "xHCI Host Controller",
299 .hcd_priv_size = sizeof(struct xhci_hcd *),
300
301 /*
302 * generic hardware linkage
303 */
304 .irq = xhci_irq,
305 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
306
307 /*
308 * basic lifecycle operations
309 */
310 .reset = xhci_pci_setup,
311 .start = xhci_run,
312#ifdef CONFIG_PM
313 .pci_suspend = xhci_pci_suspend,
314 .pci_resume = xhci_pci_resume,
315#endif
316 .stop = xhci_stop,
317 .shutdown = xhci_shutdown,
318
319 /*
320 * managing i/o requests and associated device resources
321 */
322 .urb_enqueue = xhci_urb_enqueue,
323 .urb_dequeue = xhci_urb_dequeue,
324 .alloc_dev = xhci_alloc_dev,
325 .free_dev = xhci_free_dev,
326 .alloc_streams = xhci_alloc_streams,
327 .free_streams = xhci_free_streams,
328 .add_endpoint = xhci_add_endpoint,
329 .drop_endpoint = xhci_drop_endpoint,
330 .endpoint_reset = xhci_endpoint_reset,
331 .check_bandwidth = xhci_check_bandwidth,
332 .reset_bandwidth = xhci_reset_bandwidth,
333 .address_device = xhci_address_device,
334 .update_hub_device = xhci_update_hub_device,
335 .reset_device = xhci_discover_or_reset_device,
336
337 /*
338 * scheduling support
339 */
340 .get_frame_number = xhci_get_frame,
341
342 /* Root hub support */
343 .hub_control = xhci_hub_control,
344 .hub_status_data = xhci_hub_status_data,
345 .bus_suspend = xhci_bus_suspend,
346 .bus_resume = xhci_bus_resume,
347};
348
349/*-------------------------------------------------------------------------*/
350
351/* PCI driver selection metadata; PCI hotplugging uses this */
352static const struct pci_device_id pci_ids[] = { {
353 /* handle any USB 3.0 xHCI controller */
354 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
355 .driver_data = (unsigned long) &xhci_pci_hc_driver,
356 },
357 { /* end: all zeroes */ }
358};
359MODULE_DEVICE_TABLE(pci, pci_ids);
360
361/* pci driver glue; this is a "new style" PCI driver module */
362static struct pci_driver xhci_pci_driver = {
363 .name = (char *) hcd_name,
364 .id_table = pci_ids,
365
366 .probe = xhci_pci_probe,
367 .remove = xhci_pci_remove,
368 /* suspend and resume implemented later */
369
370 .shutdown = usb_hcd_pci_shutdown,
371#ifdef CONFIG_PM_SLEEP
372 .driver = {
373 .pm = &usb_hcd_pci_pm_ops
374 },
375#endif
376};
377
378int xhci_register_pci(void)
379{
380 return pci_register_driver(&xhci_pci_driver);
381}
382
383void xhci_unregister_pci(void)
384{
385 pci_unregister_driver(&xhci_pci_driver);
386}