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1/*
2 * Renesas - AP-325RXA
3 * (Compatible with Algo System ., LTD. - AP-320A)
4 *
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 * Author : Yusuke Goda <goda.yuske@renesas.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/device.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/mmc/host.h>
18#include <linux/mmc/sh_mobile_sdhi.h>
19#include <linux/mtd/physmap.h>
20#include <linux/mtd/sh_flctl.h>
21#include <linux/delay.h>
22#include <linux/i2c.h>
23#include <linux/regulator/fixed.h>
24#include <linux/regulator/machine.h>
25#include <linux/smsc911x.h>
26#include <linux/gpio.h>
27#include <linux/videodev2.h>
28#include <linux/sh_intc.h>
29#include <media/ov772x.h>
30#include <media/soc_camera.h>
31#include <media/soc_camera_platform.h>
32#include <media/sh_mobile_ceu.h>
33#include <video/sh_mobile_lcdc.h>
34#include <asm/io.h>
35#include <asm/clock.h>
36#include <asm/suspend.h>
37#include <cpu/sh7723.h>
38
39/* Dummy supplies, where voltage doesn't matter */
40static struct regulator_consumer_supply dummy_supplies[] = {
41 REGULATOR_SUPPLY("vddvario", "smsc911x"),
42 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
43};
44
45static struct smsc911x_platform_config smsc911x_config = {
46 .phy_interface = PHY_INTERFACE_MODE_MII,
47 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
48 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
49 .flags = SMSC911X_USE_32BIT,
50};
51
52static struct resource smsc9118_resources[] = {
53 [0] = {
54 .start = 0xb6080000,
55 .end = 0xb60fffff,
56 .flags = IORESOURCE_MEM,
57 },
58 [1] = {
59 .start = evt2irq(0x660),
60 .end = evt2irq(0x660),
61 .flags = IORESOURCE_IRQ,
62 }
63};
64
65static struct platform_device smsc9118_device = {
66 .name = "smsc911x",
67 .id = -1,
68 .num_resources = ARRAY_SIZE(smsc9118_resources),
69 .resource = smsc9118_resources,
70 .dev = {
71 .platform_data = &smsc911x_config,
72 },
73};
74
75/*
76 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
77 * If this area erased, this board can not boot.
78 */
79static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
80 {
81 .name = "uboot",
82 .offset = 0,
83 .size = (1 * 1024 * 1024),
84 .mask_flags = MTD_WRITEABLE, /* Read-only */
85 }, {
86 .name = "kernel",
87 .offset = MTDPART_OFS_APPEND,
88 .size = (2 * 1024 * 1024),
89 }, {
90 .name = "free-area0",
91 .offset = MTDPART_OFS_APPEND,
92 .size = ((7 * 1024 * 1024) + (512 * 1024)),
93 }, {
94 .name = "CPLD-Data",
95 .offset = MTDPART_OFS_APPEND,
96 .mask_flags = MTD_WRITEABLE, /* Read-only */
97 .size = (1024 * 128 * 2),
98 }, {
99 .name = "free-area1",
100 .offset = MTDPART_OFS_APPEND,
101 .size = MTDPART_SIZ_FULL,
102 },
103};
104
105static struct physmap_flash_data ap325rxa_nor_flash_data = {
106 .width = 2,
107 .parts = ap325rxa_nor_flash_partitions,
108 .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
109};
110
111static struct resource ap325rxa_nor_flash_resources[] = {
112 [0] = {
113 .name = "NOR Flash",
114 .start = 0x00000000,
115 .end = 0x00ffffff,
116 .flags = IORESOURCE_MEM,
117 }
118};
119
120static struct platform_device ap325rxa_nor_flash_device = {
121 .name = "physmap-flash",
122 .resource = ap325rxa_nor_flash_resources,
123 .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
124 .dev = {
125 .platform_data = &ap325rxa_nor_flash_data,
126 },
127};
128
129static struct mtd_partition nand_partition_info[] = {
130 {
131 .name = "nand_data",
132 .offset = 0,
133 .size = MTDPART_SIZ_FULL,
134 },
135};
136
137static struct resource nand_flash_resources[] = {
138 [0] = {
139 .start = 0xa4530000,
140 .end = 0xa45300ff,
141 .flags = IORESOURCE_MEM,
142 }
143};
144
145static struct sh_flctl_platform_data nand_flash_data = {
146 .parts = nand_partition_info,
147 .nr_parts = ARRAY_SIZE(nand_partition_info),
148 .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
149 .has_hwecc = 1,
150};
151
152static struct platform_device nand_flash_device = {
153 .name = "sh_flctl",
154 .resource = nand_flash_resources,
155 .num_resources = ARRAY_SIZE(nand_flash_resources),
156 .dev = {
157 .platform_data = &nand_flash_data,
158 },
159};
160
161#define FPGA_LCDREG 0xB4100180
162#define FPGA_BKLREG 0xB4100212
163#define FPGA_LCDREG_VAL 0x0018
164#define PORT_MSELCRB 0xA4050182
165#define PORT_HIZCRC 0xA405015C
166#define PORT_DRVCRA 0xA405018A
167#define PORT_DRVCRB 0xA405018C
168
169static int ap320_wvga_set_brightness(int brightness)
170{
171 if (brightness) {
172 gpio_set_value(GPIO_PTS3, 0);
173 __raw_writew(0x100, FPGA_BKLREG);
174 } else {
175 __raw_writew(0, FPGA_BKLREG);
176 gpio_set_value(GPIO_PTS3, 1);
177 }
178
179 return 0;
180}
181
182static void ap320_wvga_power_on(void)
183{
184 msleep(100);
185
186 /* ASD AP-320/325 LCD ON */
187 __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
188}
189
190static void ap320_wvga_power_off(void)
191{
192 /* ASD AP-320/325 LCD OFF */
193 __raw_writew(0, FPGA_LCDREG);
194}
195
196static const struct fb_videomode ap325rxa_lcdc_modes[] = {
197 {
198 .name = "LB070WV1",
199 .xres = 800,
200 .yres = 480,
201 .left_margin = 32,
202 .right_margin = 160,
203 .hsync_len = 8,
204 .upper_margin = 63,
205 .lower_margin = 80,
206 .vsync_len = 1,
207 .sync = 0, /* hsync and vsync are active low */
208 },
209};
210
211static struct sh_mobile_lcdc_info lcdc_info = {
212 .clock_source = LCDC_CLK_EXTERNAL,
213 .ch[0] = {
214 .chan = LCDC_CHAN_MAINLCD,
215 .fourcc = V4L2_PIX_FMT_RGB565,
216 .interface_type = RGB18,
217 .clock_divider = 1,
218 .lcd_modes = ap325rxa_lcdc_modes,
219 .num_modes = ARRAY_SIZE(ap325rxa_lcdc_modes),
220 .panel_cfg = {
221 .width = 152, /* 7.0 inch */
222 .height = 91,
223 .display_on = ap320_wvga_power_on,
224 .display_off = ap320_wvga_power_off,
225 },
226 .bl_info = {
227 .name = "sh_mobile_lcdc_bl",
228 .max_brightness = 1,
229 .set_brightness = ap320_wvga_set_brightness,
230 },
231 }
232};
233
234static struct resource lcdc_resources[] = {
235 [0] = {
236 .name = "LCDC",
237 .start = 0xfe940000, /* P4-only space */
238 .end = 0xfe942fff,
239 .flags = IORESOURCE_MEM,
240 },
241 [1] = {
242 .start = evt2irq(0x580),
243 .flags = IORESOURCE_IRQ,
244 },
245};
246
247static struct platform_device lcdc_device = {
248 .name = "sh_mobile_lcdc_fb",
249 .num_resources = ARRAY_SIZE(lcdc_resources),
250 .resource = lcdc_resources,
251 .dev = {
252 .platform_data = &lcdc_info,
253 },
254};
255
256static void camera_power(int val)
257{
258 gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
259 mdelay(10);
260}
261
262#ifdef CONFIG_I2C
263/* support for the old ncm03j camera */
264static unsigned char camera_ncm03j_magic[] =
265{
266 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
267 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
268 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
269 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
270 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
271 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
272 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
273 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
274 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
275 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
276 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
277 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
278 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
279 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
280 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
281 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
282};
283
284static int camera_probe(void)
285{
286 struct i2c_adapter *a = i2c_get_adapter(0);
287 struct i2c_msg msg;
288 int ret;
289
290 if (!a)
291 return -ENODEV;
292
293 camera_power(1);
294 msg.addr = 0x6e;
295 msg.buf = camera_ncm03j_magic;
296 msg.len = 2;
297 msg.flags = 0;
298 ret = i2c_transfer(a, &msg, 1);
299 camera_power(0);
300
301 return ret;
302}
303
304static int camera_set_capture(struct soc_camera_platform_info *info,
305 int enable)
306{
307 struct i2c_adapter *a = i2c_get_adapter(0);
308 struct i2c_msg msg;
309 int ret = 0;
310 int i;
311
312 camera_power(0);
313 if (!enable)
314 return 0; /* no disable for now */
315
316 camera_power(1);
317 for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
318 u_int8_t buf[8];
319
320 msg.addr = 0x6e;
321 msg.buf = buf;
322 msg.len = 2;
323 msg.flags = 0;
324
325 buf[0] = camera_ncm03j_magic[i];
326 buf[1] = camera_ncm03j_magic[i + 1];
327
328 ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
329 }
330
331 return ret;
332}
333
334static int ap325rxa_camera_add(struct soc_camera_device *icd);
335static void ap325rxa_camera_del(struct soc_camera_device *icd);
336
337static struct soc_camera_platform_info camera_info = {
338 .format_name = "UYVY",
339 .format_depth = 16,
340 .format = {
341 .code = V4L2_MBUS_FMT_UYVY8_2X8,
342 .colorspace = V4L2_COLORSPACE_SMPTE170M,
343 .field = V4L2_FIELD_NONE,
344 .width = 640,
345 .height = 480,
346 },
347 .mbus_param = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
348 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
349 V4L2_MBUS_DATA_ACTIVE_HIGH,
350 .mbus_type = V4L2_MBUS_PARALLEL,
351 .set_capture = camera_set_capture,
352};
353
354static struct soc_camera_link camera_link = {
355 .bus_id = 0,
356 .add_device = ap325rxa_camera_add,
357 .del_device = ap325rxa_camera_del,
358 .module_name = "soc_camera_platform",
359 .priv = &camera_info,
360};
361
362static struct platform_device *camera_device;
363
364static void ap325rxa_camera_release(struct device *dev)
365{
366 soc_camera_platform_release(&camera_device);
367}
368
369static int ap325rxa_camera_add(struct soc_camera_device *icd)
370{
371 int ret = soc_camera_platform_add(icd, &camera_device, &camera_link,
372 ap325rxa_camera_release, 0);
373 if (ret < 0)
374 return ret;
375
376 ret = camera_probe();
377 if (ret < 0)
378 soc_camera_platform_del(icd, camera_device, &camera_link);
379
380 return ret;
381}
382
383static void ap325rxa_camera_del(struct soc_camera_device *icd)
384{
385 soc_camera_platform_del(icd, camera_device, &camera_link);
386}
387#endif /* CONFIG_I2C */
388
389static int ov7725_power(struct device *dev, int mode)
390{
391 camera_power(0);
392 if (mode)
393 camera_power(1);
394
395 return 0;
396}
397
398static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
399 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
400};
401
402static struct resource ceu_resources[] = {
403 [0] = {
404 .name = "CEU",
405 .start = 0xfe910000,
406 .end = 0xfe91009f,
407 .flags = IORESOURCE_MEM,
408 },
409 [1] = {
410 .start = evt2irq(0x880),
411 .flags = IORESOURCE_IRQ,
412 },
413 [2] = {
414 /* place holder for contiguous memory */
415 },
416};
417
418static struct platform_device ceu_device = {
419 .name = "sh_mobile_ceu",
420 .id = 0, /* "ceu0" clock */
421 .num_resources = ARRAY_SIZE(ceu_resources),
422 .resource = ceu_resources,
423 .dev = {
424 .platform_data = &sh_mobile_ceu_info,
425 },
426};
427
428/* Fixed 3.3V regulators to be used by SDHI0, SDHI1 */
429static struct regulator_consumer_supply fixed3v3_power_consumers[] =
430{
431 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
432 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
433 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
434 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
435};
436
437static struct resource sdhi0_cn3_resources[] = {
438 [0] = {
439 .name = "SDHI0",
440 .start = 0x04ce0000,
441 .end = 0x04ce00ff,
442 .flags = IORESOURCE_MEM,
443 },
444 [1] = {
445 .start = evt2irq(0xe80),
446 .flags = IORESOURCE_IRQ,
447 },
448};
449
450static struct sh_mobile_sdhi_info sdhi0_cn3_data = {
451 .tmio_caps = MMC_CAP_SDIO_IRQ,
452};
453
454static struct platform_device sdhi0_cn3_device = {
455 .name = "sh_mobile_sdhi",
456 .id = 0, /* "sdhi0" clock */
457 .num_resources = ARRAY_SIZE(sdhi0_cn3_resources),
458 .resource = sdhi0_cn3_resources,
459 .dev = {
460 .platform_data = &sdhi0_cn3_data,
461 },
462};
463
464static struct resource sdhi1_cn7_resources[] = {
465 [0] = {
466 .name = "SDHI1",
467 .start = 0x04cf0000,
468 .end = 0x04cf00ff,
469 .flags = IORESOURCE_MEM,
470 },
471 [1] = {
472 .start = evt2irq(0x4e0),
473 .flags = IORESOURCE_IRQ,
474 },
475};
476
477static struct sh_mobile_sdhi_info sdhi1_cn7_data = {
478 .tmio_caps = MMC_CAP_SDIO_IRQ,
479};
480
481static struct platform_device sdhi1_cn7_device = {
482 .name = "sh_mobile_sdhi",
483 .id = 1, /* "sdhi1" clock */
484 .num_resources = ARRAY_SIZE(sdhi1_cn7_resources),
485 .resource = sdhi1_cn7_resources,
486 .dev = {
487 .platform_data = &sdhi1_cn7_data,
488 },
489};
490
491static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
492 {
493 I2C_BOARD_INFO("pcf8563", 0x51),
494 },
495};
496
497static struct i2c_board_info ap325rxa_i2c_camera[] = {
498 {
499 I2C_BOARD_INFO("ov772x", 0x21),
500 },
501};
502
503static struct ov772x_camera_info ov7725_info = {
504 .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
505 .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
506};
507
508static struct soc_camera_link ov7725_link = {
509 .bus_id = 0,
510 .power = ov7725_power,
511 .board_info = &ap325rxa_i2c_camera[0],
512 .i2c_adapter_id = 0,
513 .priv = &ov7725_info,
514};
515
516static struct platform_device ap325rxa_camera[] = {
517 {
518 .name = "soc-camera-pdrv",
519 .id = 0,
520 .dev = {
521 .platform_data = &ov7725_link,
522 },
523 }, {
524 .name = "soc-camera-pdrv",
525 .id = 1,
526 .dev = {
527 .platform_data = &camera_link,
528 },
529 },
530};
531
532static struct platform_device *ap325rxa_devices[] __initdata = {
533 &smsc9118_device,
534 &ap325rxa_nor_flash_device,
535 &lcdc_device,
536 &ceu_device,
537 &nand_flash_device,
538 &sdhi0_cn3_device,
539 &sdhi1_cn7_device,
540 &ap325rxa_camera[0],
541 &ap325rxa_camera[1],
542};
543
544extern char ap325rxa_sdram_enter_start;
545extern char ap325rxa_sdram_enter_end;
546extern char ap325rxa_sdram_leave_start;
547extern char ap325rxa_sdram_leave_end;
548
549static int __init ap325rxa_devices_setup(void)
550{
551 /* register board specific self-refresh code */
552 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
553 &ap325rxa_sdram_enter_start,
554 &ap325rxa_sdram_enter_end,
555 &ap325rxa_sdram_leave_start,
556 &ap325rxa_sdram_leave_end);
557
558 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
559 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
560 regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies));
561
562 /* LD3 and LD4 LEDs */
563 gpio_request(GPIO_PTX5, NULL); /* RUN */
564 gpio_direction_output(GPIO_PTX5, 1);
565 gpio_export(GPIO_PTX5, 0);
566
567 gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
568 gpio_direction_output(GPIO_PTX4, 0);
569 gpio_export(GPIO_PTX4, 0);
570
571 /* SW1 input */
572 gpio_request(GPIO_PTF7, NULL); /* MODE */
573 gpio_direction_input(GPIO_PTF7);
574 gpio_export(GPIO_PTF7, 0);
575
576 /* LCDC */
577 gpio_request(GPIO_FN_LCDD15, NULL);
578 gpio_request(GPIO_FN_LCDD14, NULL);
579 gpio_request(GPIO_FN_LCDD13, NULL);
580 gpio_request(GPIO_FN_LCDD12, NULL);
581 gpio_request(GPIO_FN_LCDD11, NULL);
582 gpio_request(GPIO_FN_LCDD10, NULL);
583 gpio_request(GPIO_FN_LCDD9, NULL);
584 gpio_request(GPIO_FN_LCDD8, NULL);
585 gpio_request(GPIO_FN_LCDD7, NULL);
586 gpio_request(GPIO_FN_LCDD6, NULL);
587 gpio_request(GPIO_FN_LCDD5, NULL);
588 gpio_request(GPIO_FN_LCDD4, NULL);
589 gpio_request(GPIO_FN_LCDD3, NULL);
590 gpio_request(GPIO_FN_LCDD2, NULL);
591 gpio_request(GPIO_FN_LCDD1, NULL);
592 gpio_request(GPIO_FN_LCDD0, NULL);
593 gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
594 gpio_request(GPIO_FN_LCDDCK, NULL);
595 gpio_request(GPIO_FN_LCDVEPWC, NULL);
596 gpio_request(GPIO_FN_LCDVCPWC, NULL);
597 gpio_request(GPIO_FN_LCDVSYN, NULL);
598 gpio_request(GPIO_FN_LCDHSYN, NULL);
599 gpio_request(GPIO_FN_LCDDISP, NULL);
600 gpio_request(GPIO_FN_LCDDON, NULL);
601
602 /* LCD backlight */
603 gpio_request(GPIO_PTS3, NULL);
604 gpio_direction_output(GPIO_PTS3, 1);
605
606 /* CEU */
607 gpio_request(GPIO_FN_VIO_CLK2, NULL);
608 gpio_request(GPIO_FN_VIO_VD2, NULL);
609 gpio_request(GPIO_FN_VIO_HD2, NULL);
610 gpio_request(GPIO_FN_VIO_FLD, NULL);
611 gpio_request(GPIO_FN_VIO_CKO, NULL);
612 gpio_request(GPIO_FN_VIO_D15, NULL);
613 gpio_request(GPIO_FN_VIO_D14, NULL);
614 gpio_request(GPIO_FN_VIO_D13, NULL);
615 gpio_request(GPIO_FN_VIO_D12, NULL);
616 gpio_request(GPIO_FN_VIO_D11, NULL);
617 gpio_request(GPIO_FN_VIO_D10, NULL);
618 gpio_request(GPIO_FN_VIO_D9, NULL);
619 gpio_request(GPIO_FN_VIO_D8, NULL);
620
621 gpio_request(GPIO_PTZ7, NULL);
622 gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
623 gpio_request(GPIO_PTZ6, NULL);
624 gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
625 gpio_request(GPIO_PTZ5, NULL);
626 gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
627 gpio_request(GPIO_PTZ4, NULL);
628 gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
629
630 __raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
631
632 /* FLCTL */
633 gpio_request(GPIO_FN_FCE, NULL);
634 gpio_request(GPIO_FN_NAF7, NULL);
635 gpio_request(GPIO_FN_NAF6, NULL);
636 gpio_request(GPIO_FN_NAF5, NULL);
637 gpio_request(GPIO_FN_NAF4, NULL);
638 gpio_request(GPIO_FN_NAF3, NULL);
639 gpio_request(GPIO_FN_NAF2, NULL);
640 gpio_request(GPIO_FN_NAF1, NULL);
641 gpio_request(GPIO_FN_NAF0, NULL);
642 gpio_request(GPIO_FN_FCDE, NULL);
643 gpio_request(GPIO_FN_FOE, NULL);
644 gpio_request(GPIO_FN_FSC, NULL);
645 gpio_request(GPIO_FN_FWE, NULL);
646 gpio_request(GPIO_FN_FRB, NULL);
647
648 __raw_writew(0, PORT_HIZCRC);
649 __raw_writew(0xFFFF, PORT_DRVCRA);
650 __raw_writew(0xFFFF, PORT_DRVCRB);
651
652 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
653
654 /* SDHI0 - CN3 - SD CARD */
655 gpio_request(GPIO_FN_SDHI0CD_PTD, NULL);
656 gpio_request(GPIO_FN_SDHI0WP_PTD, NULL);
657 gpio_request(GPIO_FN_SDHI0D3_PTD, NULL);
658 gpio_request(GPIO_FN_SDHI0D2_PTD, NULL);
659 gpio_request(GPIO_FN_SDHI0D1_PTD, NULL);
660 gpio_request(GPIO_FN_SDHI0D0_PTD, NULL);
661 gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL);
662 gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL);
663
664 /* SDHI1 - CN7 - MICRO SD CARD */
665 gpio_request(GPIO_FN_SDHI1CD, NULL);
666 gpio_request(GPIO_FN_SDHI1D3, NULL);
667 gpio_request(GPIO_FN_SDHI1D2, NULL);
668 gpio_request(GPIO_FN_SDHI1D1, NULL);
669 gpio_request(GPIO_FN_SDHI1D0, NULL);
670 gpio_request(GPIO_FN_SDHI1CMD, NULL);
671 gpio_request(GPIO_FN_SDHI1CLK, NULL);
672
673 i2c_register_board_info(0, ap325rxa_i2c_devices,
674 ARRAY_SIZE(ap325rxa_i2c_devices));
675
676 return platform_add_devices(ap325rxa_devices,
677 ARRAY_SIZE(ap325rxa_devices));
678}
679arch_initcall(ap325rxa_devices_setup);
680
681/* Return the board specific boot mode pin configuration */
682static int ap325rxa_mode_pins(void)
683{
684 /* MD0=0, MD1=0, MD2=0: Clock Mode 0
685 * MD3=0: 16-bit Area0 Bus Width
686 * MD5=1: Little Endian
687 * TSTMD=1, MD8=1: Test Mode Disabled
688 */
689 return MODE_PIN5 | MODE_PIN8;
690}
691
692static struct sh_machine_vector mv_ap325rxa __initmv = {
693 .mv_name = "AP-325RXA",
694 .mv_mode_pins = ap325rxa_mode_pins,
695};
1/*
2 * Renesas - AP-325RXA
3 * (Compatible with Algo System ., LTD. - AP-320A)
4 *
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 * Author : Yusuke Goda <goda.yuske@renesas.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/device.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/mmc/host.h>
18#include <linux/mmc/sh_mobile_sdhi.h>
19#include <linux/mtd/physmap.h>
20#include <linux/mtd/sh_flctl.h>
21#include <linux/delay.h>
22#include <linux/i2c.h>
23#include <linux/smsc911x.h>
24#include <linux/gpio.h>
25#include <media/ov772x.h>
26#include <media/soc_camera.h>
27#include <media/soc_camera_platform.h>
28#include <media/sh_mobile_ceu.h>
29#include <video/sh_mobile_lcdc.h>
30#include <asm/io.h>
31#include <asm/clock.h>
32#include <asm/suspend.h>
33#include <cpu/sh7723.h>
34
35static struct smsc911x_platform_config smsc911x_config = {
36 .phy_interface = PHY_INTERFACE_MODE_MII,
37 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
38 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
39 .flags = SMSC911X_USE_32BIT,
40};
41
42static struct resource smsc9118_resources[] = {
43 [0] = {
44 .start = 0xb6080000,
45 .end = 0xb60fffff,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = 35,
50 .end = 35,
51 .flags = IORESOURCE_IRQ,
52 }
53};
54
55static struct platform_device smsc9118_device = {
56 .name = "smsc911x",
57 .id = -1,
58 .num_resources = ARRAY_SIZE(smsc9118_resources),
59 .resource = smsc9118_resources,
60 .dev = {
61 .platform_data = &smsc911x_config,
62 },
63};
64
65/*
66 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
67 * If this area erased, this board can not boot.
68 */
69static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
70 {
71 .name = "uboot",
72 .offset = 0,
73 .size = (1 * 1024 * 1024),
74 .mask_flags = MTD_WRITEABLE, /* Read-only */
75 }, {
76 .name = "kernel",
77 .offset = MTDPART_OFS_APPEND,
78 .size = (2 * 1024 * 1024),
79 }, {
80 .name = "free-area0",
81 .offset = MTDPART_OFS_APPEND,
82 .size = ((7 * 1024 * 1024) + (512 * 1024)),
83 }, {
84 .name = "CPLD-Data",
85 .offset = MTDPART_OFS_APPEND,
86 .mask_flags = MTD_WRITEABLE, /* Read-only */
87 .size = (1024 * 128 * 2),
88 }, {
89 .name = "free-area1",
90 .offset = MTDPART_OFS_APPEND,
91 .size = MTDPART_SIZ_FULL,
92 },
93};
94
95static struct physmap_flash_data ap325rxa_nor_flash_data = {
96 .width = 2,
97 .parts = ap325rxa_nor_flash_partitions,
98 .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
99};
100
101static struct resource ap325rxa_nor_flash_resources[] = {
102 [0] = {
103 .name = "NOR Flash",
104 .start = 0x00000000,
105 .end = 0x00ffffff,
106 .flags = IORESOURCE_MEM,
107 }
108};
109
110static struct platform_device ap325rxa_nor_flash_device = {
111 .name = "physmap-flash",
112 .resource = ap325rxa_nor_flash_resources,
113 .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
114 .dev = {
115 .platform_data = &ap325rxa_nor_flash_data,
116 },
117};
118
119static struct mtd_partition nand_partition_info[] = {
120 {
121 .name = "nand_data",
122 .offset = 0,
123 .size = MTDPART_SIZ_FULL,
124 },
125};
126
127static struct resource nand_flash_resources[] = {
128 [0] = {
129 .start = 0xa4530000,
130 .end = 0xa45300ff,
131 .flags = IORESOURCE_MEM,
132 }
133};
134
135static struct sh_flctl_platform_data nand_flash_data = {
136 .parts = nand_partition_info,
137 .nr_parts = ARRAY_SIZE(nand_partition_info),
138 .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
139 .has_hwecc = 1,
140};
141
142static struct platform_device nand_flash_device = {
143 .name = "sh_flctl",
144 .resource = nand_flash_resources,
145 .num_resources = ARRAY_SIZE(nand_flash_resources),
146 .dev = {
147 .platform_data = &nand_flash_data,
148 },
149};
150
151#define FPGA_LCDREG 0xB4100180
152#define FPGA_BKLREG 0xB4100212
153#define FPGA_LCDREG_VAL 0x0018
154#define PORT_MSELCRB 0xA4050182
155#define PORT_HIZCRC 0xA405015C
156#define PORT_DRVCRA 0xA405018A
157#define PORT_DRVCRB 0xA405018C
158
159static int ap320_wvga_set_brightness(void *board_data, int brightness)
160{
161 if (brightness) {
162 gpio_set_value(GPIO_PTS3, 0);
163 __raw_writew(0x100, FPGA_BKLREG);
164 } else {
165 __raw_writew(0, FPGA_BKLREG);
166 gpio_set_value(GPIO_PTS3, 1);
167 }
168
169 return 0;
170}
171
172static int ap320_wvga_get_brightness(void *board_data)
173{
174 return gpio_get_value(GPIO_PTS3);
175}
176
177static void ap320_wvga_power_on(void *board_data, struct fb_info *info)
178{
179 msleep(100);
180
181 /* ASD AP-320/325 LCD ON */
182 __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
183}
184
185static void ap320_wvga_power_off(void *board_data)
186{
187 /* ASD AP-320/325 LCD OFF */
188 __raw_writew(0, FPGA_LCDREG);
189}
190
191static const struct fb_videomode ap325rxa_lcdc_modes[] = {
192 {
193 .name = "LB070WV1",
194 .xres = 800,
195 .yres = 480,
196 .left_margin = 32,
197 .right_margin = 160,
198 .hsync_len = 8,
199 .upper_margin = 63,
200 .lower_margin = 80,
201 .vsync_len = 1,
202 .sync = 0, /* hsync and vsync are active low */
203 },
204};
205
206static struct sh_mobile_lcdc_info lcdc_info = {
207 .clock_source = LCDC_CLK_EXTERNAL,
208 .ch[0] = {
209 .chan = LCDC_CHAN_MAINLCD,
210 .bpp = 16,
211 .interface_type = RGB18,
212 .clock_divider = 1,
213 .lcd_cfg = ap325rxa_lcdc_modes,
214 .num_cfg = ARRAY_SIZE(ap325rxa_lcdc_modes),
215 .lcd_size_cfg = { /* 7.0 inch */
216 .width = 152,
217 .height = 91,
218 },
219 .board_cfg = {
220 .display_on = ap320_wvga_power_on,
221 .display_off = ap320_wvga_power_off,
222 .set_brightness = ap320_wvga_set_brightness,
223 .get_brightness = ap320_wvga_get_brightness,
224 },
225 .bl_info = {
226 .name = "sh_mobile_lcdc_bl",
227 .max_brightness = 1,
228 },
229 }
230};
231
232static struct resource lcdc_resources[] = {
233 [0] = {
234 .name = "LCDC",
235 .start = 0xfe940000, /* P4-only space */
236 .end = 0xfe942fff,
237 .flags = IORESOURCE_MEM,
238 },
239 [1] = {
240 .start = 28,
241 .flags = IORESOURCE_IRQ,
242 },
243};
244
245static struct platform_device lcdc_device = {
246 .name = "sh_mobile_lcdc_fb",
247 .num_resources = ARRAY_SIZE(lcdc_resources),
248 .resource = lcdc_resources,
249 .dev = {
250 .platform_data = &lcdc_info,
251 },
252 .archdata = {
253 .hwblk_id = HWBLK_LCDC,
254 },
255};
256
257static void camera_power(int val)
258{
259 gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
260 mdelay(10);
261}
262
263#ifdef CONFIG_I2C
264/* support for the old ncm03j camera */
265static unsigned char camera_ncm03j_magic[] =
266{
267 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
268 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
269 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
270 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
271 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
272 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
273 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
274 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
275 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
276 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
277 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
278 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
279 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
280 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
281 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
282 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
283};
284
285static int camera_probe(void)
286{
287 struct i2c_adapter *a = i2c_get_adapter(0);
288 struct i2c_msg msg;
289 int ret;
290
291 if (!a)
292 return -ENODEV;
293
294 camera_power(1);
295 msg.addr = 0x6e;
296 msg.buf = camera_ncm03j_magic;
297 msg.len = 2;
298 msg.flags = 0;
299 ret = i2c_transfer(a, &msg, 1);
300 camera_power(0);
301
302 return ret;
303}
304
305static int camera_set_capture(struct soc_camera_platform_info *info,
306 int enable)
307{
308 struct i2c_adapter *a = i2c_get_adapter(0);
309 struct i2c_msg msg;
310 int ret = 0;
311 int i;
312
313 camera_power(0);
314 if (!enable)
315 return 0; /* no disable for now */
316
317 camera_power(1);
318 for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
319 u_int8_t buf[8];
320
321 msg.addr = 0x6e;
322 msg.buf = buf;
323 msg.len = 2;
324 msg.flags = 0;
325
326 buf[0] = camera_ncm03j_magic[i];
327 buf[1] = camera_ncm03j_magic[i + 1];
328
329 ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
330 }
331
332 return ret;
333}
334
335static int ap325rxa_camera_add(struct soc_camera_device *icd);
336static void ap325rxa_camera_del(struct soc_camera_device *icd);
337
338static struct soc_camera_platform_info camera_info = {
339 .format_name = "UYVY",
340 .format_depth = 16,
341 .format = {
342 .code = V4L2_MBUS_FMT_UYVY8_2X8,
343 .colorspace = V4L2_COLORSPACE_SMPTE170M,
344 .field = V4L2_FIELD_NONE,
345 .width = 640,
346 .height = 480,
347 },
348 .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
349 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 |
350 SOCAM_DATA_ACTIVE_HIGH,
351 .set_capture = camera_set_capture,
352};
353
354static struct soc_camera_link camera_link = {
355 .bus_id = 0,
356 .add_device = ap325rxa_camera_add,
357 .del_device = ap325rxa_camera_del,
358 .module_name = "soc_camera_platform",
359 .priv = &camera_info,
360};
361
362static struct platform_device *camera_device;
363
364static void ap325rxa_camera_release(struct device *dev)
365{
366 soc_camera_platform_release(&camera_device);
367}
368
369static int ap325rxa_camera_add(struct soc_camera_device *icd)
370{
371 int ret = soc_camera_platform_add(icd, &camera_device, &camera_link,
372 ap325rxa_camera_release, 0);
373 if (ret < 0)
374 return ret;
375
376 ret = camera_probe();
377 if (ret < 0)
378 soc_camera_platform_del(icd, camera_device, &camera_link);
379
380 return ret;
381}
382
383static void ap325rxa_camera_del(struct soc_camera_device *icd)
384{
385 soc_camera_platform_del(icd, camera_device, &camera_link);
386}
387#endif /* CONFIG_I2C */
388
389static int ov7725_power(struct device *dev, int mode)
390{
391 camera_power(0);
392 if (mode)
393 camera_power(1);
394
395 return 0;
396}
397
398static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
399 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
400};
401
402static struct resource ceu_resources[] = {
403 [0] = {
404 .name = "CEU",
405 .start = 0xfe910000,
406 .end = 0xfe91009f,
407 .flags = IORESOURCE_MEM,
408 },
409 [1] = {
410 .start = 52,
411 .flags = IORESOURCE_IRQ,
412 },
413 [2] = {
414 /* place holder for contiguous memory */
415 },
416};
417
418static struct platform_device ceu_device = {
419 .name = "sh_mobile_ceu",
420 .id = 0, /* "ceu0" clock */
421 .num_resources = ARRAY_SIZE(ceu_resources),
422 .resource = ceu_resources,
423 .dev = {
424 .platform_data = &sh_mobile_ceu_info,
425 },
426 .archdata = {
427 .hwblk_id = HWBLK_CEU,
428 },
429};
430
431static struct resource sdhi0_cn3_resources[] = {
432 [0] = {
433 .name = "SDHI0",
434 .start = 0x04ce0000,
435 .end = 0x04ce00ff,
436 .flags = IORESOURCE_MEM,
437 },
438 [1] = {
439 .start = 100,
440 .flags = IORESOURCE_IRQ,
441 },
442};
443
444static struct sh_mobile_sdhi_info sdhi0_cn3_data = {
445 .tmio_caps = MMC_CAP_SDIO_IRQ,
446};
447
448static struct platform_device sdhi0_cn3_device = {
449 .name = "sh_mobile_sdhi",
450 .id = 0, /* "sdhi0" clock */
451 .num_resources = ARRAY_SIZE(sdhi0_cn3_resources),
452 .resource = sdhi0_cn3_resources,
453 .dev = {
454 .platform_data = &sdhi0_cn3_data,
455 },
456 .archdata = {
457 .hwblk_id = HWBLK_SDHI0,
458 },
459};
460
461static struct resource sdhi1_cn7_resources[] = {
462 [0] = {
463 .name = "SDHI1",
464 .start = 0x04cf0000,
465 .end = 0x04cf00ff,
466 .flags = IORESOURCE_MEM,
467 },
468 [1] = {
469 .start = 23,
470 .flags = IORESOURCE_IRQ,
471 },
472};
473
474static struct sh_mobile_sdhi_info sdhi1_cn7_data = {
475 .tmio_caps = MMC_CAP_SDIO_IRQ,
476};
477
478static struct platform_device sdhi1_cn7_device = {
479 .name = "sh_mobile_sdhi",
480 .id = 1, /* "sdhi1" clock */
481 .num_resources = ARRAY_SIZE(sdhi1_cn7_resources),
482 .resource = sdhi1_cn7_resources,
483 .dev = {
484 .platform_data = &sdhi1_cn7_data,
485 },
486 .archdata = {
487 .hwblk_id = HWBLK_SDHI1,
488 },
489};
490
491static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
492 {
493 I2C_BOARD_INFO("pcf8563", 0x51),
494 },
495};
496
497static struct i2c_board_info ap325rxa_i2c_camera[] = {
498 {
499 I2C_BOARD_INFO("ov772x", 0x21),
500 },
501};
502
503static struct ov772x_camera_info ov7725_info = {
504 .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP | \
505 OV772X_FLAG_8BIT,
506 .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
507};
508
509static struct soc_camera_link ov7725_link = {
510 .bus_id = 0,
511 .power = ov7725_power,
512 .board_info = &ap325rxa_i2c_camera[0],
513 .i2c_adapter_id = 0,
514 .priv = &ov7725_info,
515};
516
517static struct platform_device ap325rxa_camera[] = {
518 {
519 .name = "soc-camera-pdrv",
520 .id = 0,
521 .dev = {
522 .platform_data = &ov7725_link,
523 },
524 }, {
525 .name = "soc-camera-pdrv",
526 .id = 1,
527 .dev = {
528 .platform_data = &camera_link,
529 },
530 },
531};
532
533static struct platform_device *ap325rxa_devices[] __initdata = {
534 &smsc9118_device,
535 &ap325rxa_nor_flash_device,
536 &lcdc_device,
537 &ceu_device,
538 &nand_flash_device,
539 &sdhi0_cn3_device,
540 &sdhi1_cn7_device,
541 &ap325rxa_camera[0],
542 &ap325rxa_camera[1],
543};
544
545extern char ap325rxa_sdram_enter_start;
546extern char ap325rxa_sdram_enter_end;
547extern char ap325rxa_sdram_leave_start;
548extern char ap325rxa_sdram_leave_end;
549
550static int __init ap325rxa_devices_setup(void)
551{
552 /* register board specific self-refresh code */
553 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
554 &ap325rxa_sdram_enter_start,
555 &ap325rxa_sdram_enter_end,
556 &ap325rxa_sdram_leave_start,
557 &ap325rxa_sdram_leave_end);
558
559 /* LD3 and LD4 LEDs */
560 gpio_request(GPIO_PTX5, NULL); /* RUN */
561 gpio_direction_output(GPIO_PTX5, 1);
562 gpio_export(GPIO_PTX5, 0);
563
564 gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
565 gpio_direction_output(GPIO_PTX4, 0);
566 gpio_export(GPIO_PTX4, 0);
567
568 /* SW1 input */
569 gpio_request(GPIO_PTF7, NULL); /* MODE */
570 gpio_direction_input(GPIO_PTF7);
571 gpio_export(GPIO_PTF7, 0);
572
573 /* LCDC */
574 gpio_request(GPIO_FN_LCDD15, NULL);
575 gpio_request(GPIO_FN_LCDD14, NULL);
576 gpio_request(GPIO_FN_LCDD13, NULL);
577 gpio_request(GPIO_FN_LCDD12, NULL);
578 gpio_request(GPIO_FN_LCDD11, NULL);
579 gpio_request(GPIO_FN_LCDD10, NULL);
580 gpio_request(GPIO_FN_LCDD9, NULL);
581 gpio_request(GPIO_FN_LCDD8, NULL);
582 gpio_request(GPIO_FN_LCDD7, NULL);
583 gpio_request(GPIO_FN_LCDD6, NULL);
584 gpio_request(GPIO_FN_LCDD5, NULL);
585 gpio_request(GPIO_FN_LCDD4, NULL);
586 gpio_request(GPIO_FN_LCDD3, NULL);
587 gpio_request(GPIO_FN_LCDD2, NULL);
588 gpio_request(GPIO_FN_LCDD1, NULL);
589 gpio_request(GPIO_FN_LCDD0, NULL);
590 gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
591 gpio_request(GPIO_FN_LCDDCK, NULL);
592 gpio_request(GPIO_FN_LCDVEPWC, NULL);
593 gpio_request(GPIO_FN_LCDVCPWC, NULL);
594 gpio_request(GPIO_FN_LCDVSYN, NULL);
595 gpio_request(GPIO_FN_LCDHSYN, NULL);
596 gpio_request(GPIO_FN_LCDDISP, NULL);
597 gpio_request(GPIO_FN_LCDDON, NULL);
598
599 /* LCD backlight */
600 gpio_request(GPIO_PTS3, NULL);
601 gpio_direction_output(GPIO_PTS3, 1);
602
603 /* CEU */
604 gpio_request(GPIO_FN_VIO_CLK2, NULL);
605 gpio_request(GPIO_FN_VIO_VD2, NULL);
606 gpio_request(GPIO_FN_VIO_HD2, NULL);
607 gpio_request(GPIO_FN_VIO_FLD, NULL);
608 gpio_request(GPIO_FN_VIO_CKO, NULL);
609 gpio_request(GPIO_FN_VIO_D15, NULL);
610 gpio_request(GPIO_FN_VIO_D14, NULL);
611 gpio_request(GPIO_FN_VIO_D13, NULL);
612 gpio_request(GPIO_FN_VIO_D12, NULL);
613 gpio_request(GPIO_FN_VIO_D11, NULL);
614 gpio_request(GPIO_FN_VIO_D10, NULL);
615 gpio_request(GPIO_FN_VIO_D9, NULL);
616 gpio_request(GPIO_FN_VIO_D8, NULL);
617
618 gpio_request(GPIO_PTZ7, NULL);
619 gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
620 gpio_request(GPIO_PTZ6, NULL);
621 gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
622 gpio_request(GPIO_PTZ5, NULL);
623 gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
624 gpio_request(GPIO_PTZ4, NULL);
625 gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
626
627 __raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
628
629 /* FLCTL */
630 gpio_request(GPIO_FN_FCE, NULL);
631 gpio_request(GPIO_FN_NAF7, NULL);
632 gpio_request(GPIO_FN_NAF6, NULL);
633 gpio_request(GPIO_FN_NAF5, NULL);
634 gpio_request(GPIO_FN_NAF4, NULL);
635 gpio_request(GPIO_FN_NAF3, NULL);
636 gpio_request(GPIO_FN_NAF2, NULL);
637 gpio_request(GPIO_FN_NAF1, NULL);
638 gpio_request(GPIO_FN_NAF0, NULL);
639 gpio_request(GPIO_FN_FCDE, NULL);
640 gpio_request(GPIO_FN_FOE, NULL);
641 gpio_request(GPIO_FN_FSC, NULL);
642 gpio_request(GPIO_FN_FWE, NULL);
643 gpio_request(GPIO_FN_FRB, NULL);
644
645 __raw_writew(0, PORT_HIZCRC);
646 __raw_writew(0xFFFF, PORT_DRVCRA);
647 __raw_writew(0xFFFF, PORT_DRVCRB);
648
649 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
650
651 /* SDHI0 - CN3 - SD CARD */
652 gpio_request(GPIO_FN_SDHI0CD_PTD, NULL);
653 gpio_request(GPIO_FN_SDHI0WP_PTD, NULL);
654 gpio_request(GPIO_FN_SDHI0D3_PTD, NULL);
655 gpio_request(GPIO_FN_SDHI0D2_PTD, NULL);
656 gpio_request(GPIO_FN_SDHI0D1_PTD, NULL);
657 gpio_request(GPIO_FN_SDHI0D0_PTD, NULL);
658 gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL);
659 gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL);
660
661 /* SDHI1 - CN7 - MICRO SD CARD */
662 gpio_request(GPIO_FN_SDHI1CD, NULL);
663 gpio_request(GPIO_FN_SDHI1D3, NULL);
664 gpio_request(GPIO_FN_SDHI1D2, NULL);
665 gpio_request(GPIO_FN_SDHI1D1, NULL);
666 gpio_request(GPIO_FN_SDHI1D0, NULL);
667 gpio_request(GPIO_FN_SDHI1CMD, NULL);
668 gpio_request(GPIO_FN_SDHI1CLK, NULL);
669
670 i2c_register_board_info(0, ap325rxa_i2c_devices,
671 ARRAY_SIZE(ap325rxa_i2c_devices));
672
673 return platform_add_devices(ap325rxa_devices,
674 ARRAY_SIZE(ap325rxa_devices));
675}
676arch_initcall(ap325rxa_devices_setup);
677
678/* Return the board specific boot mode pin configuration */
679static int ap325rxa_mode_pins(void)
680{
681 /* MD0=0, MD1=0, MD2=0: Clock Mode 0
682 * MD3=0: 16-bit Area0 Bus Width
683 * MD5=1: Little Endian
684 * TSTMD=1, MD8=1: Test Mode Disabled
685 */
686 return MODE_PIN5 | MODE_PIN8;
687}
688
689static struct sh_machine_vector mv_ap325rxa __initmv = {
690 .mv_name = "AP-325RXA",
691 .mv_mode_pins = ap325rxa_mode_pins,
692};