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1/*
2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
3 *
4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
6 *
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/delay.h>
23#include <linux/string.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/bootmem.h>
27#include <linux/memblock.h>
28#include <linux/log2.h>
29#include <linux/slab.h>
30#include <linux/suspend.h>
31#include <linux/syscore_ops.h>
32#include <linux/uaccess.h>
33
34#include <asm/io.h>
35#include <asm/prom.h>
36#include <asm/pci-bridge.h>
37#include <asm/ppc-pci.h>
38#include <asm/machdep.h>
39#include <asm/disassemble.h>
40#include <asm/ppc-opcode.h>
41#include <sysdev/fsl_soc.h>
42#include <sysdev/fsl_pci.h>
43
44static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
45
46static void quirk_fsl_pcie_early(struct pci_dev *dev)
47{
48 u8 hdr_type;
49
50 /* if we aren't a PCIe don't bother */
51 if (!pci_is_pcie(dev))
52 return;
53
54 /* if we aren't in host mode don't bother */
55 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
56 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
57 return;
58
59 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
60 fsl_pcie_bus_fixup = 1;
61 return;
62}
63
64static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
65 int, int, u32 *);
66
67static int fsl_pcie_check_link(struct pci_controller *hose)
68{
69 u32 val = 0;
70
71 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
72 if (hose->ops->read == fsl_indirect_read_config) {
73 struct pci_bus bus;
74 bus.number = hose->first_busno;
75 bus.sysdata = hose;
76 bus.ops = hose->ops;
77 indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
78 } else
79 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
80 if (val < PCIE_LTSSM_L0)
81 return 1;
82 } else {
83 struct ccsr_pci __iomem *pci = hose->private_data;
84 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
85 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
86 >> PEX_CSR0_LTSSM_SHIFT;
87 if (val != PEX_CSR0_LTSSM_L0)
88 return 1;
89 }
90
91 return 0;
92}
93
94static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
95 int offset, int len, u32 *val)
96{
97 struct pci_controller *hose = pci_bus_to_host(bus);
98
99 if (fsl_pcie_check_link(hose))
100 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
101 else
102 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
103
104 return indirect_read_config(bus, devfn, offset, len, val);
105}
106
107#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
108
109static struct pci_ops fsl_indirect_pcie_ops =
110{
111 .read = fsl_indirect_read_config,
112 .write = indirect_write_config,
113};
114
115#define MAX_PHYS_ADDR_BITS 40
116static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
117
118static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
119{
120 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
121 return -EIO;
122
123 /*
124 * Fixup PCI devices that are able to DMA to above the physical
125 * address width of the SoC such that we can address any internal
126 * SoC address from across PCI if needed
127 */
128 if ((dev_is_pci(dev)) &&
129 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
130 set_dma_ops(dev, &dma_direct_ops);
131 set_dma_offset(dev, pci64_dma_offset);
132 }
133
134 *dev->dma_mask = dma_mask;
135 return 0;
136}
137
138static int setup_one_atmu(struct ccsr_pci __iomem *pci,
139 unsigned int index, const struct resource *res,
140 resource_size_t offset)
141{
142 resource_size_t pci_addr = res->start - offset;
143 resource_size_t phys_addr = res->start;
144 resource_size_t size = resource_size(res);
145 u32 flags = 0x80044000; /* enable & mem R/W */
146 unsigned int i;
147
148 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
149 (u64)res->start, (u64)size);
150
151 if (res->flags & IORESOURCE_PREFETCH)
152 flags |= 0x10000000; /* enable relaxed ordering */
153
154 for (i = 0; size > 0; i++) {
155 unsigned int bits = min(ilog2(size),
156 __ffs(pci_addr | phys_addr));
157
158 if (index + i >= 5)
159 return -1;
160
161 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
162 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
163 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
164 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
165
166 pci_addr += (resource_size_t)1U << bits;
167 phys_addr += (resource_size_t)1U << bits;
168 size -= (resource_size_t)1U << bits;
169 }
170
171 return i;
172}
173
174/* atmu setup for fsl pci/pcie controller */
175static void setup_pci_atmu(struct pci_controller *hose)
176{
177 struct ccsr_pci __iomem *pci = hose->private_data;
178 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
179 u64 mem, sz, paddr_hi = 0;
180 u64 offset = 0, paddr_lo = ULLONG_MAX;
181 u32 pcicsrbar = 0, pcicsrbar_sz;
182 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
183 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
184 const char *name = hose->dn->full_name;
185 const u64 *reg;
186 int len;
187
188 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
189 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
190 win_idx = 2;
191 start_idx = 0;
192 end_idx = 3;
193 }
194 }
195
196 /* Disable all windows (except powar0 since it's ignored) */
197 for(i = 1; i < 5; i++)
198 out_be32(&pci->pow[i].powar, 0);
199 for (i = start_idx; i < end_idx; i++)
200 out_be32(&pci->piw[i].piwar, 0);
201
202 /* Setup outbound MEM window */
203 for(i = 0, j = 1; i < 3; i++) {
204 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
205 continue;
206
207 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
208 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
209
210 /* We assume all memory resources have the same offset */
211 offset = hose->mem_offset[i];
212 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
213
214 if (n < 0 || j >= 5) {
215 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
216 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
217 } else
218 j += n;
219 }
220
221 /* Setup outbound IO window */
222 if (hose->io_resource.flags & IORESOURCE_IO) {
223 if (j >= 5) {
224 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
225 } else {
226 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
227 "phy base 0x%016llx.\n",
228 (u64)hose->io_resource.start,
229 (u64)resource_size(&hose->io_resource),
230 (u64)hose->io_base_phys);
231 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
232 out_be32(&pci->pow[j].potear, 0);
233 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
234 /* Enable, IO R/W */
235 out_be32(&pci->pow[j].powar, 0x80088000
236 | (ilog2(hose->io_resource.end
237 - hose->io_resource.start + 1) - 1));
238 }
239 }
240
241 /* convert to pci address space */
242 paddr_hi -= offset;
243 paddr_lo -= offset;
244
245 if (paddr_hi == paddr_lo) {
246 pr_err("%s: No outbound window space\n", name);
247 return;
248 }
249
250 if (paddr_lo == 0) {
251 pr_err("%s: No space for inbound window\n", name);
252 return;
253 }
254
255 /* setup PCSRBAR/PEXCSRBAR */
256 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
257 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
258 pcicsrbar_sz = ~pcicsrbar_sz + 1;
259
260 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
261 (paddr_lo > 0x100000000ull))
262 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
263 else
264 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
265 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
266
267 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
268
269 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
270
271 /* Setup inbound mem window */
272 mem = memblock_end_of_DRAM();
273
274 /*
275 * The msi-address-64 property, if it exists, indicates the physical
276 * address of the MSIIR register. Normally, this register is located
277 * inside CCSR, so the ATMU that covers all of CCSR is used. But if
278 * this property exists, then we normally need to create a new ATMU
279 * for it. For now, however, we cheat. The only entity that creates
280 * this property is the Freescale hypervisor, and the address is
281 * specified in the partition configuration. Typically, the address
282 * is located in the page immediately after the end of DDR. If so, we
283 * can avoid allocating a new ATMU by extending the DDR ATMU by one
284 * page.
285 */
286 reg = of_get_property(hose->dn, "msi-address-64", &len);
287 if (reg && (len == sizeof(u64))) {
288 u64 address = be64_to_cpup(reg);
289
290 if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
291 pr_info("%s: extending DDR ATMU to cover MSIIR", name);
292 mem += PAGE_SIZE;
293 } else {
294 /* TODO: Create a new ATMU for MSIIR */
295 pr_warn("%s: msi-address-64 address of %llx is "
296 "unsupported\n", name, address);
297 }
298 }
299
300 sz = min(mem, paddr_lo);
301 mem_log = ilog2(sz);
302
303 /* PCIe can overmap inbound & outbound since RX & TX are separated */
304 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
305 /* Size window to exact size if power-of-two or one size up */
306 if ((1ull << mem_log) != mem) {
307 mem_log++;
308 if ((1ull << mem_log) > mem)
309 pr_info("%s: Setting PCI inbound window "
310 "greater than memory size\n", name);
311 }
312
313 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
314
315 /* Setup inbound memory window */
316 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
317 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
318 out_be32(&pci->piw[win_idx].piwar, piwar);
319 win_idx--;
320
321 hose->dma_window_base_cur = 0x00000000;
322 hose->dma_window_size = (resource_size_t)sz;
323
324 /*
325 * if we have >4G of memory setup second PCI inbound window to
326 * let devices that are 64-bit address capable to work w/o
327 * SWIOTLB and access the full range of memory
328 */
329 if (sz != mem) {
330 mem_log = ilog2(mem);
331
332 /* Size window up if we dont fit in exact power-of-2 */
333 if ((1ull << mem_log) != mem)
334 mem_log++;
335
336 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
337
338 /* Setup inbound memory window */
339 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
340 out_be32(&pci->piw[win_idx].piwbear,
341 pci64_dma_offset >> 44);
342 out_be32(&pci->piw[win_idx].piwbar,
343 pci64_dma_offset >> 12);
344 out_be32(&pci->piw[win_idx].piwar, piwar);
345
346 /*
347 * install our own dma_set_mask handler to fixup dma_ops
348 * and dma_offset
349 */
350 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
351
352 pr_info("%s: Setup 64-bit PCI DMA window\n", name);
353 }
354 } else {
355 u64 paddr = 0;
356
357 /* Setup inbound memory window */
358 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
359 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
360 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
361 win_idx--;
362
363 paddr += 1ull << mem_log;
364 sz -= 1ull << mem_log;
365
366 if (sz) {
367 mem_log = ilog2(sz);
368 piwar |= (mem_log - 1);
369
370 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
371 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
372 out_be32(&pci->piw[win_idx].piwar, piwar);
373 win_idx--;
374
375 paddr += 1ull << mem_log;
376 }
377
378 hose->dma_window_base_cur = 0x00000000;
379 hose->dma_window_size = (resource_size_t)paddr;
380 }
381
382 if (hose->dma_window_size < mem) {
383#ifdef CONFIG_SWIOTLB
384 ppc_swiotlb_enable = 1;
385#else
386 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
387 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
388 name);
389#endif
390 /* adjusting outbound windows could reclaim space in mem map */
391 if (paddr_hi < 0xffffffffull)
392 pr_warning("%s: WARNING: Outbound window cfg leaves "
393 "gaps in memory map. Adjusting the memory map "
394 "could reduce unnecessary bounce buffering.\n",
395 name);
396
397 pr_info("%s: DMA window size is 0x%llx\n", name,
398 (u64)hose->dma_window_size);
399 }
400}
401
402static void __init setup_pci_cmd(struct pci_controller *hose)
403{
404 u16 cmd;
405 int cap_x;
406
407 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
408 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
409 | PCI_COMMAND_IO;
410 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
411
412 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
413 if (cap_x) {
414 int pci_x_cmd = cap_x + PCI_X_CMD;
415 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
416 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
417 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
418 } else {
419 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
420 }
421}
422
423void fsl_pcibios_fixup_bus(struct pci_bus *bus)
424{
425 struct pci_controller *hose = pci_bus_to_host(bus);
426 int i, is_pcie = 0, no_link;
427
428 /* The root complex bridge comes up with bogus resources,
429 * we copy the PHB ones in.
430 *
431 * With the current generic PCI code, the PHB bus no longer
432 * has bus->resource[0..4] set, so things are a bit more
433 * tricky.
434 */
435
436 if (fsl_pcie_bus_fixup)
437 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
438 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
439
440 if (bus->parent == hose->bus && (is_pcie || no_link)) {
441 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
442 struct resource *res = bus->resource[i];
443 struct resource *par;
444
445 if (!res)
446 continue;
447 if (i == 0)
448 par = &hose->io_resource;
449 else if (i < 4)
450 par = &hose->mem_resources[i-1];
451 else par = NULL;
452
453 res->start = par ? par->start : 0;
454 res->end = par ? par->end : 0;
455 res->flags = par ? par->flags : 0;
456 }
457 }
458}
459
460int fsl_add_bridge(struct platform_device *pdev, int is_primary)
461{
462 int len;
463 struct pci_controller *hose;
464 struct resource rsrc;
465 const int *bus_range;
466 u8 hdr_type, progif;
467 struct device_node *dev;
468 struct ccsr_pci __iomem *pci;
469
470 dev = pdev->dev.of_node;
471
472 if (!of_device_is_available(dev)) {
473 pr_warning("%s: disabled\n", dev->full_name);
474 return -ENODEV;
475 }
476
477 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
478
479 /* Fetch host bridge registers address */
480 if (of_address_to_resource(dev, 0, &rsrc)) {
481 printk(KERN_WARNING "Can't get pci register base!");
482 return -ENOMEM;
483 }
484
485 /* Get bus range if any */
486 bus_range = of_get_property(dev, "bus-range", &len);
487 if (bus_range == NULL || len < 2 * sizeof(int))
488 printk(KERN_WARNING "Can't get bus-range for %s, assume"
489 " bus 0\n", dev->full_name);
490
491 pci_add_flags(PCI_REASSIGN_ALL_BUS);
492 hose = pcibios_alloc_controller(dev);
493 if (!hose)
494 return -ENOMEM;
495
496 /* set platform device as the parent */
497 hose->parent = &pdev->dev;
498 hose->first_busno = bus_range ? bus_range[0] : 0x0;
499 hose->last_busno = bus_range ? bus_range[1] : 0xff;
500
501 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
502 (u64)rsrc.start, (u64)resource_size(&rsrc));
503
504 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
505 if (!hose->private_data)
506 goto no_bridge;
507
508 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
509 PPC_INDIRECT_TYPE_BIG_ENDIAN);
510
511 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
512 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
513
514 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
515 /* use fsl_indirect_read_config for PCIe */
516 hose->ops = &fsl_indirect_pcie_ops;
517 /* For PCIE read HEADER_TYPE to identify controler mode */
518 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
519 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
520 goto no_bridge;
521
522 } else {
523 /* For PCI read PROG to identify controller mode */
524 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
525 if ((progif & 1) == 1)
526 goto no_bridge;
527 }
528
529 setup_pci_cmd(hose);
530
531 /* check PCI express link status */
532 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
533 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
534 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
535 if (fsl_pcie_check_link(hose))
536 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
537 }
538
539 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
540 "Firmware bus number: %d->%d\n",
541 (unsigned long long)rsrc.start, hose->first_busno,
542 hose->last_busno);
543
544 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
545 hose, hose->cfg_addr, hose->cfg_data);
546
547 /* Interpret the "ranges" property */
548 /* This also maps the I/O region and sets isa_io/mem_base */
549 pci_process_bridge_OF_ranges(hose, dev, is_primary);
550
551 /* Setup PEX window registers */
552 setup_pci_atmu(hose);
553
554 return 0;
555
556no_bridge:
557 iounmap(hose->private_data);
558 /* unmap cfg_data & cfg_addr separately if not on same page */
559 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
560 ((unsigned long)hose->cfg_addr & PAGE_MASK))
561 iounmap(hose->cfg_data);
562 iounmap(hose->cfg_addr);
563 pcibios_free_controller(hose);
564 return -ENODEV;
565}
566#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
567
568DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
569 quirk_fsl_pcie_early);
570
571#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
572struct mpc83xx_pcie_priv {
573 void __iomem *cfg_type0;
574 void __iomem *cfg_type1;
575 u32 dev_base;
576};
577
578struct pex_inbound_window {
579 u32 ar;
580 u32 tar;
581 u32 barl;
582 u32 barh;
583};
584
585/*
586 * With the convention of u-boot, the PCIE outbound window 0 serves
587 * as configuration transactions outbound.
588 */
589#define PEX_OUTWIN0_BAR 0xCA4
590#define PEX_OUTWIN0_TAL 0xCA8
591#define PEX_OUTWIN0_TAH 0xCAC
592#define PEX_RC_INWIN_BASE 0xE60
593#define PEX_RCIWARn_EN 0x1
594
595static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
596{
597 struct pci_controller *hose = pci_bus_to_host(bus);
598
599 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
600 return PCIBIOS_DEVICE_NOT_FOUND;
601 /*
602 * Workaround for the HW bug: for Type 0 configure transactions the
603 * PCI-E controller does not check the device number bits and just
604 * assumes that the device number bits are 0.
605 */
606 if (bus->number == hose->first_busno ||
607 bus->primary == hose->first_busno) {
608 if (devfn & 0xf8)
609 return PCIBIOS_DEVICE_NOT_FOUND;
610 }
611
612 if (ppc_md.pci_exclude_device) {
613 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
614 return PCIBIOS_DEVICE_NOT_FOUND;
615 }
616
617 return PCIBIOS_SUCCESSFUL;
618}
619
620static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
621 unsigned int devfn, int offset)
622{
623 struct pci_controller *hose = pci_bus_to_host(bus);
624 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
625 u32 dev_base = bus->number << 24 | devfn << 16;
626 int ret;
627
628 ret = mpc83xx_pcie_exclude_device(bus, devfn);
629 if (ret)
630 return NULL;
631
632 offset &= 0xfff;
633
634 /* Type 0 */
635 if (bus->number == hose->first_busno)
636 return pcie->cfg_type0 + offset;
637
638 if (pcie->dev_base == dev_base)
639 goto mapped;
640
641 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
642
643 pcie->dev_base = dev_base;
644mapped:
645 return pcie->cfg_type1 + offset;
646}
647
648static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
649 int offset, int len, u32 *val)
650{
651 void __iomem *cfg_addr;
652
653 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
654 if (!cfg_addr)
655 return PCIBIOS_DEVICE_NOT_FOUND;
656
657 switch (len) {
658 case 1:
659 *val = in_8(cfg_addr);
660 break;
661 case 2:
662 *val = in_le16(cfg_addr);
663 break;
664 default:
665 *val = in_le32(cfg_addr);
666 break;
667 }
668
669 return PCIBIOS_SUCCESSFUL;
670}
671
672static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
673 int offset, int len, u32 val)
674{
675 struct pci_controller *hose = pci_bus_to_host(bus);
676 void __iomem *cfg_addr;
677
678 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
679 if (!cfg_addr)
680 return PCIBIOS_DEVICE_NOT_FOUND;
681
682 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
683 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
684 val &= 0xffffff00;
685
686 switch (len) {
687 case 1:
688 out_8(cfg_addr, val);
689 break;
690 case 2:
691 out_le16(cfg_addr, val);
692 break;
693 default:
694 out_le32(cfg_addr, val);
695 break;
696 }
697
698 return PCIBIOS_SUCCESSFUL;
699}
700
701static struct pci_ops mpc83xx_pcie_ops = {
702 .read = mpc83xx_pcie_read_config,
703 .write = mpc83xx_pcie_write_config,
704};
705
706static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
707 struct resource *reg)
708{
709 struct mpc83xx_pcie_priv *pcie;
710 u32 cfg_bar;
711 int ret = -ENOMEM;
712
713 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
714 if (!pcie)
715 return ret;
716
717 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
718 if (!pcie->cfg_type0)
719 goto err0;
720
721 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
722 if (!cfg_bar) {
723 /* PCI-E isn't configured. */
724 ret = -ENODEV;
725 goto err1;
726 }
727
728 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
729 if (!pcie->cfg_type1)
730 goto err1;
731
732 WARN_ON(hose->dn->data);
733 hose->dn->data = pcie;
734 hose->ops = &mpc83xx_pcie_ops;
735 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
736
737 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
738 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
739
740 if (fsl_pcie_check_link(hose))
741 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
742
743 return 0;
744err1:
745 iounmap(pcie->cfg_type0);
746err0:
747 kfree(pcie);
748 return ret;
749
750}
751
752int __init mpc83xx_add_bridge(struct device_node *dev)
753{
754 int ret;
755 int len;
756 struct pci_controller *hose;
757 struct resource rsrc_reg;
758 struct resource rsrc_cfg;
759 const int *bus_range;
760 int primary;
761
762 is_mpc83xx_pci = 1;
763
764 if (!of_device_is_available(dev)) {
765 pr_warning("%s: disabled by the firmware.\n",
766 dev->full_name);
767 return -ENODEV;
768 }
769 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
770
771 /* Fetch host bridge registers address */
772 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
773 printk(KERN_WARNING "Can't get pci register base!\n");
774 return -ENOMEM;
775 }
776
777 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
778
779 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
780 printk(KERN_WARNING
781 "No pci config register base in dev tree, "
782 "using default\n");
783 /*
784 * MPC83xx supports up to two host controllers
785 * one at 0x8500 has config space registers at 0x8300
786 * one at 0x8600 has config space registers at 0x8380
787 */
788 if ((rsrc_reg.start & 0xfffff) == 0x8500)
789 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
790 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
791 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
792 }
793 /*
794 * Controller at offset 0x8500 is primary
795 */
796 if ((rsrc_reg.start & 0xfffff) == 0x8500)
797 primary = 1;
798 else
799 primary = 0;
800
801 /* Get bus range if any */
802 bus_range = of_get_property(dev, "bus-range", &len);
803 if (bus_range == NULL || len < 2 * sizeof(int)) {
804 printk(KERN_WARNING "Can't get bus-range for %s, assume"
805 " bus 0\n", dev->full_name);
806 }
807
808 pci_add_flags(PCI_REASSIGN_ALL_BUS);
809 hose = pcibios_alloc_controller(dev);
810 if (!hose)
811 return -ENOMEM;
812
813 hose->first_busno = bus_range ? bus_range[0] : 0;
814 hose->last_busno = bus_range ? bus_range[1] : 0xff;
815
816 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
817 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
818 if (ret)
819 goto err0;
820 } else {
821 setup_indirect_pci(hose, rsrc_cfg.start,
822 rsrc_cfg.start + 4, 0);
823 }
824
825 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
826 "Firmware bus number: %d->%d\n",
827 (unsigned long long)rsrc_reg.start, hose->first_busno,
828 hose->last_busno);
829
830 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
831 hose, hose->cfg_addr, hose->cfg_data);
832
833 /* Interpret the "ranges" property */
834 /* This also maps the I/O region and sets isa_io/mem_base */
835 pci_process_bridge_OF_ranges(hose, dev, primary);
836
837 return 0;
838err0:
839 pcibios_free_controller(hose);
840 return ret;
841}
842#endif /* CONFIG_PPC_83xx */
843
844u64 fsl_pci_immrbar_base(struct pci_controller *hose)
845{
846#ifdef CONFIG_PPC_83xx
847 if (is_mpc83xx_pci) {
848 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
849 struct pex_inbound_window *in;
850 int i;
851
852 /* Walk the Root Complex Inbound windows to match IMMR base */
853 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
854 for (i = 0; i < 4; i++) {
855 /* not enabled, skip */
856 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
857 continue;
858
859 if (get_immrbase() == in_le32(&in[i].tar))
860 return (u64)in_le32(&in[i].barh) << 32 |
861 in_le32(&in[i].barl);
862 }
863
864 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
865 }
866#endif
867
868#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
869 if (!is_mpc83xx_pci) {
870 u32 base;
871
872 pci_bus_read_config_dword(hose->bus,
873 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
874
875 /*
876 * For PEXCSRBAR, bit 3-0 indicate prefetchable and
877 * address type. So when getting base address, these
878 * bits should be masked
879 */
880 base &= PCI_BASE_ADDRESS_MEM_MASK;
881
882 return base;
883 }
884#endif
885
886 return 0;
887}
888
889#ifdef CONFIG_E500
890static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
891{
892 unsigned int rd, ra, rb, d;
893
894 rd = get_rt(inst);
895 ra = get_ra(inst);
896 rb = get_rb(inst);
897 d = get_d(inst);
898
899 switch (get_op(inst)) {
900 case 31:
901 switch (get_xop(inst)) {
902 case OP_31_XOP_LWZX:
903 case OP_31_XOP_LWBRX:
904 regs->gpr[rd] = 0xffffffff;
905 break;
906
907 case OP_31_XOP_LWZUX:
908 regs->gpr[rd] = 0xffffffff;
909 regs->gpr[ra] += regs->gpr[rb];
910 break;
911
912 case OP_31_XOP_LBZX:
913 regs->gpr[rd] = 0xff;
914 break;
915
916 case OP_31_XOP_LBZUX:
917 regs->gpr[rd] = 0xff;
918 regs->gpr[ra] += regs->gpr[rb];
919 break;
920
921 case OP_31_XOP_LHZX:
922 case OP_31_XOP_LHBRX:
923 regs->gpr[rd] = 0xffff;
924 break;
925
926 case OP_31_XOP_LHZUX:
927 regs->gpr[rd] = 0xffff;
928 regs->gpr[ra] += regs->gpr[rb];
929 break;
930
931 case OP_31_XOP_LHAX:
932 regs->gpr[rd] = ~0UL;
933 break;
934
935 case OP_31_XOP_LHAUX:
936 regs->gpr[rd] = ~0UL;
937 regs->gpr[ra] += regs->gpr[rb];
938 break;
939
940 default:
941 return 0;
942 }
943 break;
944
945 case OP_LWZ:
946 regs->gpr[rd] = 0xffffffff;
947 break;
948
949 case OP_LWZU:
950 regs->gpr[rd] = 0xffffffff;
951 regs->gpr[ra] += (s16)d;
952 break;
953
954 case OP_LBZ:
955 regs->gpr[rd] = 0xff;
956 break;
957
958 case OP_LBZU:
959 regs->gpr[rd] = 0xff;
960 regs->gpr[ra] += (s16)d;
961 break;
962
963 case OP_LHZ:
964 regs->gpr[rd] = 0xffff;
965 break;
966
967 case OP_LHZU:
968 regs->gpr[rd] = 0xffff;
969 regs->gpr[ra] += (s16)d;
970 break;
971
972 case OP_LHA:
973 regs->gpr[rd] = ~0UL;
974 break;
975
976 case OP_LHAU:
977 regs->gpr[rd] = ~0UL;
978 regs->gpr[ra] += (s16)d;
979 break;
980
981 default:
982 return 0;
983 }
984
985 return 1;
986}
987
988static int is_in_pci_mem_space(phys_addr_t addr)
989{
990 struct pci_controller *hose;
991 struct resource *res;
992 int i;
993
994 list_for_each_entry(hose, &hose_list, list_node) {
995 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
996 continue;
997
998 for (i = 0; i < 3; i++) {
999 res = &hose->mem_resources[i];
1000 if ((res->flags & IORESOURCE_MEM) &&
1001 addr >= res->start && addr <= res->end)
1002 return 1;
1003 }
1004 }
1005 return 0;
1006}
1007
1008int fsl_pci_mcheck_exception(struct pt_regs *regs)
1009{
1010 u32 inst;
1011 int ret;
1012 phys_addr_t addr = 0;
1013
1014 /* Let KVM/QEMU deal with the exception */
1015 if (regs->msr & MSR_GS)
1016 return 0;
1017
1018#ifdef CONFIG_PHYS_64BIT
1019 addr = mfspr(SPRN_MCARU);
1020 addr <<= 32;
1021#endif
1022 addr += mfspr(SPRN_MCAR);
1023
1024 if (is_in_pci_mem_space(addr)) {
1025 if (user_mode(regs)) {
1026 pagefault_disable();
1027 ret = get_user(regs->nip, &inst);
1028 pagefault_enable();
1029 } else {
1030 ret = probe_kernel_address(regs->nip, inst);
1031 }
1032
1033 if (mcheck_handle_load(regs, inst)) {
1034 regs->nip += 4;
1035 return 1;
1036 }
1037 }
1038
1039 return 0;
1040}
1041#endif
1042
1043#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
1044static const struct of_device_id pci_ids[] = {
1045 { .compatible = "fsl,mpc8540-pci", },
1046 { .compatible = "fsl,mpc8548-pcie", },
1047 { .compatible = "fsl,mpc8610-pci", },
1048 { .compatible = "fsl,mpc8641-pcie", },
1049 { .compatible = "fsl,qoriq-pcie", },
1050 { .compatible = "fsl,qoriq-pcie-v2.1", },
1051 { .compatible = "fsl,qoriq-pcie-v2.2", },
1052 { .compatible = "fsl,qoriq-pcie-v2.3", },
1053 { .compatible = "fsl,qoriq-pcie-v2.4", },
1054 { .compatible = "fsl,qoriq-pcie-v3.0", },
1055
1056 /*
1057 * The following entries are for compatibility with older device
1058 * trees.
1059 */
1060 { .compatible = "fsl,p1022-pcie", },
1061 { .compatible = "fsl,p4080-pcie", },
1062
1063 {},
1064};
1065
1066struct device_node *fsl_pci_primary;
1067
1068void fsl_pci_assign_primary(void)
1069{
1070 struct device_node *np;
1071
1072 /* Callers can specify the primary bus using other means. */
1073 if (fsl_pci_primary)
1074 return;
1075
1076 /* If a PCI host bridge contains an ISA node, it's primary. */
1077 np = of_find_node_by_type(NULL, "isa");
1078 while ((fsl_pci_primary = of_get_parent(np))) {
1079 of_node_put(np);
1080 np = fsl_pci_primary;
1081
1082 if (of_match_node(pci_ids, np) && of_device_is_available(np))
1083 return;
1084 }
1085
1086 /*
1087 * If there's no PCI host bridge with ISA, arbitrarily
1088 * designate one as primary. This can go away once
1089 * various bugs with primary-less systems are fixed.
1090 */
1091 for_each_matching_node(np, pci_ids) {
1092 if (of_device_is_available(np)) {
1093 fsl_pci_primary = np;
1094 of_node_put(np);
1095 return;
1096 }
1097 }
1098}
1099
1100#ifdef CONFIG_PM_SLEEP
1101static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id)
1102{
1103 struct pci_controller *hose = dev_id;
1104 struct ccsr_pci __iomem *pci = hose->private_data;
1105 u32 dr;
1106
1107 dr = in_be32(&pci->pex_pme_mes_dr);
1108 if (!dr)
1109 return IRQ_NONE;
1110
1111 out_be32(&pci->pex_pme_mes_dr, dr);
1112
1113 return IRQ_HANDLED;
1114}
1115
1116static int fsl_pci_pme_probe(struct pci_controller *hose)
1117{
1118 struct ccsr_pci __iomem *pci;
1119 struct pci_dev *dev;
1120 int pme_irq;
1121 int res;
1122 u16 pms;
1123
1124 /* Get hose's pci_dev */
1125 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list);
1126
1127 /* PME Disable */
1128 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
1129 pms &= ~PCI_PM_CTRL_PME_ENABLE;
1130 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
1131
1132 pme_irq = irq_of_parse_and_map(hose->dn, 0);
1133 if (!pme_irq) {
1134 dev_err(&dev->dev, "Failed to map PME interrupt.\n");
1135
1136 return -ENXIO;
1137 }
1138
1139 res = devm_request_irq(hose->parent, pme_irq,
1140 fsl_pci_pme_handle,
1141 IRQF_SHARED,
1142 "[PCI] PME", hose);
1143 if (res < 0) {
1144 dev_err(&dev->dev, "Unable to requiest irq %d for PME\n", pme_irq);
1145 irq_dispose_mapping(pme_irq);
1146
1147 return -ENODEV;
1148 }
1149
1150 pci = hose->private_data;
1151
1152 /* Enable PTOD, ENL23D & EXL23D */
1153 out_be32(&pci->pex_pme_mes_disr, 0);
1154 setbits32(&pci->pex_pme_mes_disr,
1155 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
1156
1157 out_be32(&pci->pex_pme_mes_ier, 0);
1158 setbits32(&pci->pex_pme_mes_ier,
1159 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
1160
1161 /* PME Enable */
1162 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
1163 pms |= PCI_PM_CTRL_PME_ENABLE;
1164 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
1165
1166 return 0;
1167}
1168
1169static void send_pme_turnoff_message(struct pci_controller *hose)
1170{
1171 struct ccsr_pci __iomem *pci = hose->private_data;
1172 u32 dr;
1173 int i;
1174
1175 /* Send PME_Turn_Off Message Request */
1176 setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
1177
1178 /* Wait trun off done */
1179 for (i = 0; i < 150; i++) {
1180 dr = in_be32(&pci->pex_pme_mes_dr);
1181 if (dr) {
1182 out_be32(&pci->pex_pme_mes_dr, dr);
1183 break;
1184 }
1185
1186 udelay(1000);
1187 }
1188}
1189
1190static void fsl_pci_syscore_do_suspend(struct pci_controller *hose)
1191{
1192 send_pme_turnoff_message(hose);
1193}
1194
1195static int fsl_pci_syscore_suspend(void)
1196{
1197 struct pci_controller *hose, *tmp;
1198
1199 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1200 fsl_pci_syscore_do_suspend(hose);
1201
1202 return 0;
1203}
1204
1205static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
1206{
1207 struct ccsr_pci __iomem *pci = hose->private_data;
1208 u32 dr;
1209 int i;
1210
1211 /* Send Exit L2 State Message */
1212 setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
1213
1214 /* Wait exit done */
1215 for (i = 0; i < 150; i++) {
1216 dr = in_be32(&pci->pex_pme_mes_dr);
1217 if (dr) {
1218 out_be32(&pci->pex_pme_mes_dr, dr);
1219 break;
1220 }
1221
1222 udelay(1000);
1223 }
1224
1225 setup_pci_atmu(hose);
1226}
1227
1228static void fsl_pci_syscore_resume(void)
1229{
1230 struct pci_controller *hose, *tmp;
1231
1232 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1233 fsl_pci_syscore_do_resume(hose);
1234}
1235
1236static struct syscore_ops pci_syscore_pm_ops = {
1237 .suspend = fsl_pci_syscore_suspend,
1238 .resume = fsl_pci_syscore_resume,
1239};
1240#endif
1241
1242void fsl_pcibios_fixup_phb(struct pci_controller *phb)
1243{
1244#ifdef CONFIG_PM_SLEEP
1245 fsl_pci_pme_probe(phb);
1246#endif
1247}
1248
1249static int fsl_pci_probe(struct platform_device *pdev)
1250{
1251 struct device_node *node;
1252 int ret;
1253
1254 node = pdev->dev.of_node;
1255 ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
1256
1257 mpc85xx_pci_err_probe(pdev);
1258
1259 return 0;
1260}
1261
1262static struct platform_driver fsl_pci_driver = {
1263 .driver = {
1264 .name = "fsl-pci",
1265 .of_match_table = pci_ids,
1266 },
1267 .probe = fsl_pci_probe,
1268};
1269
1270static int __init fsl_pci_init(void)
1271{
1272#ifdef CONFIG_PM_SLEEP
1273 register_syscore_ops(&pci_syscore_pm_ops);
1274#endif
1275 return platform_driver_register(&fsl_pci_driver);
1276}
1277arch_initcall(fsl_pci_init);
1278#endif
1/*
2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
3 *
4 * Copyright 2007-2011 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
6 *
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/delay.h>
23#include <linux/string.h>
24#include <linux/init.h>
25#include <linux/bootmem.h>
26#include <linux/memblock.h>
27#include <linux/log2.h>
28#include <linux/slab.h>
29
30#include <asm/io.h>
31#include <asm/prom.h>
32#include <asm/pci-bridge.h>
33#include <asm/machdep.h>
34#include <sysdev/fsl_soc.h>
35#include <sysdev/fsl_pci.h>
36
37static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
38
39static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
40{
41 u8 progif;
42
43 /* if we aren't a PCIe don't bother */
44 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
45 return;
46
47 /* if we aren't in host mode don't bother */
48 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
49 if (progif & 0x1)
50 return;
51
52 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
53 fsl_pcie_bus_fixup = 1;
54 return;
55}
56
57static int __init fsl_pcie_check_link(struct pci_controller *hose)
58{
59 u32 val;
60
61 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
62 if (val < PCIE_LTSSM_L0)
63 return 1;
64 return 0;
65}
66
67#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
68static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
69 unsigned int index, const struct resource *res,
70 resource_size_t offset)
71{
72 resource_size_t pci_addr = res->start - offset;
73 resource_size_t phys_addr = res->start;
74 resource_size_t size = resource_size(res);
75 u32 flags = 0x80044000; /* enable & mem R/W */
76 unsigned int i;
77
78 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
79 (u64)res->start, (u64)size);
80
81 if (res->flags & IORESOURCE_PREFETCH)
82 flags |= 0x10000000; /* enable relaxed ordering */
83
84 for (i = 0; size > 0; i++) {
85 unsigned int bits = min(__ilog2(size),
86 __ffs(pci_addr | phys_addr));
87
88 if (index + i >= 5)
89 return -1;
90
91 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
92 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
93 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
94 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
95
96 pci_addr += (resource_size_t)1U << bits;
97 phys_addr += (resource_size_t)1U << bits;
98 size -= (resource_size_t)1U << bits;
99 }
100
101 return i;
102}
103
104/* atmu setup for fsl pci/pcie controller */
105static void __init setup_pci_atmu(struct pci_controller *hose,
106 struct resource *rsrc)
107{
108 struct ccsr_pci __iomem *pci;
109 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
110 u64 mem, sz, paddr_hi = 0;
111 u64 paddr_lo = ULLONG_MAX;
112 u32 pcicsrbar = 0, pcicsrbar_sz;
113 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
114 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
115 char *name = hose->dn->full_name;
116
117 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
118 (u64)rsrc->start, (u64)resource_size(rsrc));
119
120 if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) {
121 win_idx = 2;
122 start_idx = 0;
123 end_idx = 3;
124 }
125
126 pci = ioremap(rsrc->start, resource_size(rsrc));
127 if (!pci) {
128 dev_err(hose->parent, "Unable to map ATMU registers\n");
129 return;
130 }
131
132 /* Disable all windows (except powar0 since it's ignored) */
133 for(i = 1; i < 5; i++)
134 out_be32(&pci->pow[i].powar, 0);
135 for (i = start_idx; i < end_idx; i++)
136 out_be32(&pci->piw[i].piwar, 0);
137
138 /* Setup outbound MEM window */
139 for(i = 0, j = 1; i < 3; i++) {
140 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
141 continue;
142
143 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
144 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
145
146 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
147 hose->pci_mem_offset);
148
149 if (n < 0 || j >= 5) {
150 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
151 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
152 } else
153 j += n;
154 }
155
156 /* Setup outbound IO window */
157 if (hose->io_resource.flags & IORESOURCE_IO) {
158 if (j >= 5) {
159 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
160 } else {
161 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
162 "phy base 0x%016llx.\n",
163 (u64)hose->io_resource.start,
164 (u64)resource_size(&hose->io_resource),
165 (u64)hose->io_base_phys);
166 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
167 out_be32(&pci->pow[j].potear, 0);
168 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
169 /* Enable, IO R/W */
170 out_be32(&pci->pow[j].powar, 0x80088000
171 | (__ilog2(hose->io_resource.end
172 - hose->io_resource.start + 1) - 1));
173 }
174 }
175
176 /* convert to pci address space */
177 paddr_hi -= hose->pci_mem_offset;
178 paddr_lo -= hose->pci_mem_offset;
179
180 if (paddr_hi == paddr_lo) {
181 pr_err("%s: No outbound window space\n", name);
182 return ;
183 }
184
185 if (paddr_lo == 0) {
186 pr_err("%s: No space for inbound window\n", name);
187 return ;
188 }
189
190 /* setup PCSRBAR/PEXCSRBAR */
191 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
192 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
193 pcicsrbar_sz = ~pcicsrbar_sz + 1;
194
195 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
196 (paddr_lo > 0x100000000ull))
197 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
198 else
199 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
200 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
201
202 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
203
204 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
205
206 /* Setup inbound mem window */
207 mem = memblock_end_of_DRAM();
208 sz = min(mem, paddr_lo);
209 mem_log = __ilog2_u64(sz);
210
211 /* PCIe can overmap inbound & outbound since RX & TX are separated */
212 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
213 /* Size window to exact size if power-of-two or one size up */
214 if ((1ull << mem_log) != mem) {
215 if ((1ull << mem_log) > mem)
216 pr_info("%s: Setting PCI inbound window "
217 "greater than memory size\n", name);
218 mem_log++;
219 }
220
221 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
222
223 /* Setup inbound memory window */
224 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
225 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
226 out_be32(&pci->piw[win_idx].piwar, piwar);
227 win_idx--;
228
229 hose->dma_window_base_cur = 0x00000000;
230 hose->dma_window_size = (resource_size_t)sz;
231 } else {
232 u64 paddr = 0;
233
234 /* Setup inbound memory window */
235 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
236 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
237 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
238 win_idx--;
239
240 paddr += 1ull << mem_log;
241 sz -= 1ull << mem_log;
242
243 if (sz) {
244 mem_log = __ilog2_u64(sz);
245 piwar |= (mem_log - 1);
246
247 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
248 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
249 out_be32(&pci->piw[win_idx].piwar, piwar);
250 win_idx--;
251
252 paddr += 1ull << mem_log;
253 }
254
255 hose->dma_window_base_cur = 0x00000000;
256 hose->dma_window_size = (resource_size_t)paddr;
257 }
258
259 if (hose->dma_window_size < mem) {
260#ifndef CONFIG_SWIOTLB
261 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
262 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
263 name);
264#endif
265 /* adjusting outbound windows could reclaim space in mem map */
266 if (paddr_hi < 0xffffffffull)
267 pr_warning("%s: WARNING: Outbound window cfg leaves "
268 "gaps in memory map. Adjusting the memory map "
269 "could reduce unnecessary bounce buffering.\n",
270 name);
271
272 pr_info("%s: DMA window size is 0x%llx\n", name,
273 (u64)hose->dma_window_size);
274 }
275
276 iounmap(pci);
277}
278
279static void __init setup_pci_cmd(struct pci_controller *hose)
280{
281 u16 cmd;
282 int cap_x;
283
284 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
285 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
286 | PCI_COMMAND_IO;
287 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
288
289 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
290 if (cap_x) {
291 int pci_x_cmd = cap_x + PCI_X_CMD;
292 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
293 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
294 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
295 } else {
296 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
297 }
298}
299
300void fsl_pcibios_fixup_bus(struct pci_bus *bus)
301{
302 struct pci_controller *hose = pci_bus_to_host(bus);
303 int i;
304
305 if ((bus->parent == hose->bus) &&
306 ((fsl_pcie_bus_fixup &&
307 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
308 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
309 {
310 for (i = 0; i < 4; ++i) {
311 struct resource *res = bus->resource[i];
312 struct resource *par = bus->parent->resource[i];
313 if (res) {
314 res->start = 0;
315 res->end = 0;
316 res->flags = 0;
317 }
318 if (res && par) {
319 res->start = par->start;
320 res->end = par->end;
321 res->flags = par->flags;
322 }
323 }
324 }
325}
326
327int __init fsl_add_bridge(struct device_node *dev, int is_primary)
328{
329 int len;
330 struct pci_controller *hose;
331 struct resource rsrc;
332 const int *bus_range;
333 u8 progif;
334
335 if (!of_device_is_available(dev)) {
336 pr_warning("%s: disabled\n", dev->full_name);
337 return -ENODEV;
338 }
339
340 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
341
342 /* Fetch host bridge registers address */
343 if (of_address_to_resource(dev, 0, &rsrc)) {
344 printk(KERN_WARNING "Can't get pci register base!");
345 return -ENOMEM;
346 }
347
348 /* Get bus range if any */
349 bus_range = of_get_property(dev, "bus-range", &len);
350 if (bus_range == NULL || len < 2 * sizeof(int))
351 printk(KERN_WARNING "Can't get bus-range for %s, assume"
352 " bus 0\n", dev->full_name);
353
354 pci_add_flags(PCI_REASSIGN_ALL_BUS);
355 hose = pcibios_alloc_controller(dev);
356 if (!hose)
357 return -ENOMEM;
358
359 hose->first_busno = bus_range ? bus_range[0] : 0x0;
360 hose->last_busno = bus_range ? bus_range[1] : 0xff;
361
362 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
363 PPC_INDIRECT_TYPE_BIG_ENDIAN);
364
365 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
366 if ((progif & 1) == 1) {
367 /* unmap cfg_data & cfg_addr separately if not on same page */
368 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
369 ((unsigned long)hose->cfg_addr & PAGE_MASK))
370 iounmap(hose->cfg_data);
371 iounmap(hose->cfg_addr);
372 pcibios_free_controller(hose);
373 return 0;
374 }
375
376 setup_pci_cmd(hose);
377
378 /* check PCI express link status */
379 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
380 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
381 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
382 if (fsl_pcie_check_link(hose))
383 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
384 }
385
386 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
387 "Firmware bus number: %d->%d\n",
388 (unsigned long long)rsrc.start, hose->first_busno,
389 hose->last_busno);
390
391 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
392 hose, hose->cfg_addr, hose->cfg_data);
393
394 /* Interpret the "ranges" property */
395 /* This also maps the I/O region and sets isa_io/mem_base */
396 pci_process_bridge_OF_ranges(hose, dev, is_primary);
397
398 /* Setup PEX window registers */
399 setup_pci_atmu(hose, &rsrc);
400
401 return 0;
402}
403#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
404
405DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
406
407#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
408struct mpc83xx_pcie_priv {
409 void __iomem *cfg_type0;
410 void __iomem *cfg_type1;
411 u32 dev_base;
412};
413
414struct pex_inbound_window {
415 u32 ar;
416 u32 tar;
417 u32 barl;
418 u32 barh;
419};
420
421/*
422 * With the convention of u-boot, the PCIE outbound window 0 serves
423 * as configuration transactions outbound.
424 */
425#define PEX_OUTWIN0_BAR 0xCA4
426#define PEX_OUTWIN0_TAL 0xCA8
427#define PEX_OUTWIN0_TAH 0xCAC
428#define PEX_RC_INWIN_BASE 0xE60
429#define PEX_RCIWARn_EN 0x1
430
431static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
432{
433 struct pci_controller *hose = pci_bus_to_host(bus);
434
435 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
436 return PCIBIOS_DEVICE_NOT_FOUND;
437 /*
438 * Workaround for the HW bug: for Type 0 configure transactions the
439 * PCI-E controller does not check the device number bits and just
440 * assumes that the device number bits are 0.
441 */
442 if (bus->number == hose->first_busno ||
443 bus->primary == hose->first_busno) {
444 if (devfn & 0xf8)
445 return PCIBIOS_DEVICE_NOT_FOUND;
446 }
447
448 if (ppc_md.pci_exclude_device) {
449 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
450 return PCIBIOS_DEVICE_NOT_FOUND;
451 }
452
453 return PCIBIOS_SUCCESSFUL;
454}
455
456static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
457 unsigned int devfn, int offset)
458{
459 struct pci_controller *hose = pci_bus_to_host(bus);
460 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
461 u32 dev_base = bus->number << 24 | devfn << 16;
462 int ret;
463
464 ret = mpc83xx_pcie_exclude_device(bus, devfn);
465 if (ret)
466 return NULL;
467
468 offset &= 0xfff;
469
470 /* Type 0 */
471 if (bus->number == hose->first_busno)
472 return pcie->cfg_type0 + offset;
473
474 if (pcie->dev_base == dev_base)
475 goto mapped;
476
477 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
478
479 pcie->dev_base = dev_base;
480mapped:
481 return pcie->cfg_type1 + offset;
482}
483
484static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
485 int offset, int len, u32 *val)
486{
487 void __iomem *cfg_addr;
488
489 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
490 if (!cfg_addr)
491 return PCIBIOS_DEVICE_NOT_FOUND;
492
493 switch (len) {
494 case 1:
495 *val = in_8(cfg_addr);
496 break;
497 case 2:
498 *val = in_le16(cfg_addr);
499 break;
500 default:
501 *val = in_le32(cfg_addr);
502 break;
503 }
504
505 return PCIBIOS_SUCCESSFUL;
506}
507
508static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
509 int offset, int len, u32 val)
510{
511 struct pci_controller *hose = pci_bus_to_host(bus);
512 void __iomem *cfg_addr;
513
514 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
515 if (!cfg_addr)
516 return PCIBIOS_DEVICE_NOT_FOUND;
517
518 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
519 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
520 val &= 0xffffff00;
521
522 switch (len) {
523 case 1:
524 out_8(cfg_addr, val);
525 break;
526 case 2:
527 out_le16(cfg_addr, val);
528 break;
529 default:
530 out_le32(cfg_addr, val);
531 break;
532 }
533
534 return PCIBIOS_SUCCESSFUL;
535}
536
537static struct pci_ops mpc83xx_pcie_ops = {
538 .read = mpc83xx_pcie_read_config,
539 .write = mpc83xx_pcie_write_config,
540};
541
542static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
543 struct resource *reg)
544{
545 struct mpc83xx_pcie_priv *pcie;
546 u32 cfg_bar;
547 int ret = -ENOMEM;
548
549 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
550 if (!pcie)
551 return ret;
552
553 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
554 if (!pcie->cfg_type0)
555 goto err0;
556
557 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
558 if (!cfg_bar) {
559 /* PCI-E isn't configured. */
560 ret = -ENODEV;
561 goto err1;
562 }
563
564 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
565 if (!pcie->cfg_type1)
566 goto err1;
567
568 WARN_ON(hose->dn->data);
569 hose->dn->data = pcie;
570 hose->ops = &mpc83xx_pcie_ops;
571
572 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
573 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
574
575 if (fsl_pcie_check_link(hose))
576 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
577
578 return 0;
579err1:
580 iounmap(pcie->cfg_type0);
581err0:
582 kfree(pcie);
583 return ret;
584
585}
586
587int __init mpc83xx_add_bridge(struct device_node *dev)
588{
589 int ret;
590 int len;
591 struct pci_controller *hose;
592 struct resource rsrc_reg;
593 struct resource rsrc_cfg;
594 const int *bus_range;
595 int primary;
596
597 is_mpc83xx_pci = 1;
598
599 if (!of_device_is_available(dev)) {
600 pr_warning("%s: disabled by the firmware.\n",
601 dev->full_name);
602 return -ENODEV;
603 }
604 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
605
606 /* Fetch host bridge registers address */
607 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
608 printk(KERN_WARNING "Can't get pci register base!\n");
609 return -ENOMEM;
610 }
611
612 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
613
614 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
615 printk(KERN_WARNING
616 "No pci config register base in dev tree, "
617 "using default\n");
618 /*
619 * MPC83xx supports up to two host controllers
620 * one at 0x8500 has config space registers at 0x8300
621 * one at 0x8600 has config space registers at 0x8380
622 */
623 if ((rsrc_reg.start & 0xfffff) == 0x8500)
624 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
625 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
626 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
627 }
628 /*
629 * Controller at offset 0x8500 is primary
630 */
631 if ((rsrc_reg.start & 0xfffff) == 0x8500)
632 primary = 1;
633 else
634 primary = 0;
635
636 /* Get bus range if any */
637 bus_range = of_get_property(dev, "bus-range", &len);
638 if (bus_range == NULL || len < 2 * sizeof(int)) {
639 printk(KERN_WARNING "Can't get bus-range for %s, assume"
640 " bus 0\n", dev->full_name);
641 }
642
643 pci_add_flags(PCI_REASSIGN_ALL_BUS);
644 hose = pcibios_alloc_controller(dev);
645 if (!hose)
646 return -ENOMEM;
647
648 hose->first_busno = bus_range ? bus_range[0] : 0;
649 hose->last_busno = bus_range ? bus_range[1] : 0xff;
650
651 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
652 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
653 if (ret)
654 goto err0;
655 } else {
656 setup_indirect_pci(hose, rsrc_cfg.start,
657 rsrc_cfg.start + 4, 0);
658 }
659
660 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
661 "Firmware bus number: %d->%d\n",
662 (unsigned long long)rsrc_reg.start, hose->first_busno,
663 hose->last_busno);
664
665 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
666 hose, hose->cfg_addr, hose->cfg_data);
667
668 /* Interpret the "ranges" property */
669 /* This also maps the I/O region and sets isa_io/mem_base */
670 pci_process_bridge_OF_ranges(hose, dev, primary);
671
672 return 0;
673err0:
674 pcibios_free_controller(hose);
675 return ret;
676}
677#endif /* CONFIG_PPC_83xx */
678
679u64 fsl_pci_immrbar_base(struct pci_controller *hose)
680{
681#ifdef CONFIG_PPC_83xx
682 if (is_mpc83xx_pci) {
683 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
684 struct pex_inbound_window *in;
685 int i;
686
687 /* Walk the Root Complex Inbound windows to match IMMR base */
688 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
689 for (i = 0; i < 4; i++) {
690 /* not enabled, skip */
691 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
692 continue;
693
694 if (get_immrbase() == in_le32(&in[i].tar))
695 return (u64)in_le32(&in[i].barh) << 32 |
696 in_le32(&in[i].barl);
697 }
698
699 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
700 }
701#endif
702
703#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
704 if (!is_mpc83xx_pci) {
705 u32 base;
706
707 pci_bus_read_config_dword(hose->bus,
708 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
709 return base;
710 }
711#endif
712
713 return 0;
714}