Loading...
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform GPIO support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <linux/delay.h>
23#include <linux/interrupt.h>
24#include <linux/bitops.h>
25
26#include <linux/debugfs.h>
27#include <linux/seq_file.h>
28
29#include <asm/mach-jz4740/base.h>
30
31#include "irq.h"
32
33#define JZ4740_GPIO_BASE_A (32*0)
34#define JZ4740_GPIO_BASE_B (32*1)
35#define JZ4740_GPIO_BASE_C (32*2)
36#define JZ4740_GPIO_BASE_D (32*3)
37
38#define JZ4740_GPIO_NUM_A 32
39#define JZ4740_GPIO_NUM_B 32
40#define JZ4740_GPIO_NUM_C 31
41#define JZ4740_GPIO_NUM_D 32
42
43#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
44#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
45#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
46#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
47
48#define JZ_REG_GPIO_PIN 0x00
49#define JZ_REG_GPIO_DATA 0x10
50#define JZ_REG_GPIO_DATA_SET 0x14
51#define JZ_REG_GPIO_DATA_CLEAR 0x18
52#define JZ_REG_GPIO_MASK 0x20
53#define JZ_REG_GPIO_MASK_SET 0x24
54#define JZ_REG_GPIO_MASK_CLEAR 0x28
55#define JZ_REG_GPIO_PULL 0x30
56#define JZ_REG_GPIO_PULL_SET 0x34
57#define JZ_REG_GPIO_PULL_CLEAR 0x38
58#define JZ_REG_GPIO_FUNC 0x40
59#define JZ_REG_GPIO_FUNC_SET 0x44
60#define JZ_REG_GPIO_FUNC_CLEAR 0x48
61#define JZ_REG_GPIO_SELECT 0x50
62#define JZ_REG_GPIO_SELECT_SET 0x54
63#define JZ_REG_GPIO_SELECT_CLEAR 0x58
64#define JZ_REG_GPIO_DIRECTION 0x60
65#define JZ_REG_GPIO_DIRECTION_SET 0x64
66#define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
67#define JZ_REG_GPIO_TRIGGER 0x70
68#define JZ_REG_GPIO_TRIGGER_SET 0x74
69#define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
70#define JZ_REG_GPIO_FLAG 0x80
71#define JZ_REG_GPIO_FLAG_CLEAR 0x14
72
73#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
74#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
75#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
76
77struct jz_gpio_chip {
78 unsigned int irq;
79 unsigned int irq_base;
80 uint32_t edge_trigger_both;
81
82 void __iomem *base;
83
84 struct gpio_chip gpio_chip;
85};
86
87static struct jz_gpio_chip jz4740_gpio_chips[];
88
89static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
90{
91 return &jz4740_gpio_chips[gpio >> 5];
92}
93
94static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip)
95{
96 return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
97}
98
99static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data)
100{
101 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
102 return gc->private;
103}
104
105static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
106{
107 writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
108}
109
110int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
111{
112 if (function == JZ_GPIO_FUNC_NONE) {
113 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
114 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
115 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
116 } else {
117 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
118 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
119 switch (function) {
120 case JZ_GPIO_FUNC1:
121 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
122 break;
123 case JZ_GPIO_FUNC3:
124 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
125 case JZ_GPIO_FUNC2: /* Falltrough */
126 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
127 break;
128 default:
129 BUG();
130 break;
131 }
132 }
133
134 return 0;
135}
136EXPORT_SYMBOL_GPL(jz_gpio_set_function);
137
138int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
139{
140 size_t i;
141 int ret;
142
143 for (i = 0; i < num; ++i, ++request) {
144 ret = gpio_request(request->gpio, request->name);
145 if (ret)
146 goto err;
147 jz_gpio_set_function(request->gpio, request->function);
148 }
149
150 return 0;
151
152err:
153 for (--request; i > 0; --i, --request) {
154 gpio_free(request->gpio);
155 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
156 }
157
158 return ret;
159}
160EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
161
162void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
163{
164 size_t i;
165
166 for (i = 0; i < num; ++i, ++request) {
167 gpio_free(request->gpio);
168 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
169 }
170
171}
172EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
173
174void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
175{
176 size_t i;
177
178 for (i = 0; i < num; ++i, ++request) {
179 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
180 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
181 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
182 }
183}
184EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
185
186void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
187{
188 size_t i;
189
190 for (i = 0; i < num; ++i, ++request)
191 jz_gpio_set_function(request->gpio, request->function);
192}
193EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
194
195void jz_gpio_enable_pullup(unsigned gpio)
196{
197 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
198}
199EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
200
201void jz_gpio_disable_pullup(unsigned gpio)
202{
203 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
204}
205EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
206
207static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
208{
209 return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
210}
211
212static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
213{
214 uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
215 reg += !value;
216 writel(BIT(gpio), reg);
217}
218
219static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
220 int value)
221{
222 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
223 jz_gpio_set_value(chip, gpio, value);
224
225 return 0;
226}
227
228static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
229{
230 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
231
232 return 0;
233}
234
235int jz_gpio_port_direction_input(int port, uint32_t mask)
236{
237 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
238
239 return 0;
240}
241EXPORT_SYMBOL(jz_gpio_port_direction_input);
242
243int jz_gpio_port_direction_output(int port, uint32_t mask)
244{
245 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
246
247 return 0;
248}
249EXPORT_SYMBOL(jz_gpio_port_direction_output);
250
251void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
252{
253 writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
254 writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
255}
256EXPORT_SYMBOL(jz_gpio_port_set_value);
257
258uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
259{
260 uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
261
262 return value & mask;
263}
264EXPORT_SYMBOL(jz_gpio_port_get_value);
265
266int gpio_to_irq(unsigned gpio)
267{
268 return JZ4740_IRQ_GPIO(0) + gpio;
269}
270EXPORT_SYMBOL_GPL(gpio_to_irq);
271
272int irq_to_gpio(unsigned irq)
273{
274 return irq - JZ4740_IRQ_GPIO(0);
275}
276EXPORT_SYMBOL_GPL(irq_to_gpio);
277
278#define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f)
279
280static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
281{
282 uint32_t value;
283 void __iomem *reg;
284 uint32_t mask = IRQ_TO_BIT(irq);
285
286 if (!(chip->edge_trigger_both & mask))
287 return;
288
289 reg = chip->base;
290
291 value = readl(chip->base + JZ_REG_GPIO_PIN);
292 if (value & mask)
293 reg += JZ_REG_GPIO_DIRECTION_CLEAR;
294 else
295 reg += JZ_REG_GPIO_DIRECTION_SET;
296
297 writel(mask, reg);
298}
299
300static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
301{
302 uint32_t flag;
303 unsigned int gpio_irq;
304 struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
305
306 flag = readl(chip->base + JZ_REG_GPIO_FLAG);
307 if (!flag)
308 return;
309
310 gpio_irq = chip->irq_base + __fls(flag);
311
312 jz_gpio_check_trigger_both(chip, gpio_irq);
313
314 generic_handle_irq(gpio_irq);
315};
316
317static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg)
318{
319 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
320 writel(IRQ_TO_BIT(data->irq), chip->base + reg);
321}
322
323static void jz_gpio_irq_unmask(struct irq_data *data)
324{
325 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
326
327 jz_gpio_check_trigger_both(chip, data->irq);
328 irq_gc_unmask_enable_reg(data);
329};
330
331/* TODO: Check if function is gpio */
332static unsigned int jz_gpio_irq_startup(struct irq_data *data)
333{
334 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET);
335 jz_gpio_irq_unmask(data);
336 return 0;
337}
338
339static void jz_gpio_irq_shutdown(struct irq_data *data)
340{
341 irq_gc_mask_disable_reg(data);
342
343 /* Set direction to input */
344 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
345 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR);
346}
347
348static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
349{
350 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
351 unsigned int irq = data->irq;
352
353 if (flow_type == IRQ_TYPE_EDGE_BOTH) {
354 uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
355 if (value & IRQ_TO_BIT(irq))
356 flow_type = IRQ_TYPE_EDGE_FALLING;
357 else
358 flow_type = IRQ_TYPE_EDGE_RISING;
359 chip->edge_trigger_both |= IRQ_TO_BIT(irq);
360 } else {
361 chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
362 }
363
364 switch (flow_type) {
365 case IRQ_TYPE_EDGE_RISING:
366 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
367 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
368 break;
369 case IRQ_TYPE_EDGE_FALLING:
370 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
371 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
372 break;
373 case IRQ_TYPE_LEVEL_HIGH:
374 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
375 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
376 break;
377 case IRQ_TYPE_LEVEL_LOW:
378 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
379 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
380 break;
381 default:
382 return -EINVAL;
383 }
384
385 return 0;
386}
387
388static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
389{
390 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
391
392 irq_gc_set_wake(data, on);
393 irq_set_irq_wake(chip->irq, on);
394
395 return 0;
396}
397
398#define JZ4740_GPIO_CHIP(_bank) { \
399 .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
400 .gpio_chip = { \
401 .label = "Bank " # _bank, \
402 .owner = THIS_MODULE, \
403 .set = jz_gpio_set_value, \
404 .get = jz_gpio_get_value, \
405 .direction_output = jz_gpio_direction_output, \
406 .direction_input = jz_gpio_direction_input, \
407 .base = JZ4740_GPIO_BASE_ ## _bank, \
408 .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
409 }, \
410}
411
412static struct jz_gpio_chip jz4740_gpio_chips[] = {
413 JZ4740_GPIO_CHIP(A),
414 JZ4740_GPIO_CHIP(B),
415 JZ4740_GPIO_CHIP(C),
416 JZ4740_GPIO_CHIP(D),
417};
418
419static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
420{
421 struct irq_chip_generic *gc;
422 struct irq_chip_type *ct;
423
424 chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
425
426 chip->irq = JZ4740_IRQ_INTC_GPIO(id);
427 irq_set_handler_data(chip->irq, chip);
428 irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
429
430 gc = irq_alloc_generic_chip(chip->gpio_chip.label, 1, chip->irq_base,
431 chip->base, handle_level_irq);
432
433 gc->wake_enabled = IRQ_MSK(chip->gpio_chip.ngpio);
434 gc->private = chip;
435
436 ct = gc->chip_types;
437 ct->regs.enable = JZ_REG_GPIO_MASK_CLEAR;
438 ct->regs.disable = JZ_REG_GPIO_MASK_SET;
439 ct->regs.ack = JZ_REG_GPIO_FLAG_CLEAR;
440
441 ct->chip.name = "GPIO";
442 ct->chip.irq_mask = irq_gc_mask_disable_reg;
443 ct->chip.irq_unmask = jz_gpio_irq_unmask;
444 ct->chip.irq_ack = irq_gc_ack_set_bit;
445 ct->chip.irq_suspend = jz4740_irq_suspend;
446 ct->chip.irq_resume = jz4740_irq_resume;
447 ct->chip.irq_startup = jz_gpio_irq_startup;
448 ct->chip.irq_shutdown = jz_gpio_irq_shutdown;
449 ct->chip.irq_set_type = jz_gpio_irq_set_type;
450 ct->chip.irq_set_wake = jz_gpio_irq_set_wake;
451 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
452
453 irq_setup_generic_chip(gc, IRQ_MSK(chip->gpio_chip.ngpio),
454 IRQ_GC_INIT_NESTED_LOCK, 0, IRQ_NOPROBE | IRQ_LEVEL);
455
456 gpiochip_add(&chip->gpio_chip);
457}
458
459static int __init jz4740_gpio_init(void)
460{
461 unsigned int i;
462
463 for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
464 jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
465
466 printk(KERN_INFO "JZ4740 GPIO initialized\n");
467
468 return 0;
469}
470arch_initcall(jz4740_gpio_init);
471
472#ifdef CONFIG_DEBUG_FS
473
474static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,
475 const char *name, unsigned int reg)
476{
477 seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
478}
479
480static int gpio_regs_show(struct seq_file *s, void *unused)
481{
482 struct jz_gpio_chip *chip = jz4740_gpio_chips;
483 int i;
484
485 for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
486 seq_printf(s, "==GPIO %d==\n", i);
487 gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
488 gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
489 gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
490 gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
491 gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
492 gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
493 gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
494 gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
495 gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
496 }
497
498 return 0;
499}
500
501static int gpio_regs_open(struct inode *inode, struct file *file)
502{
503 return single_open(file, gpio_regs_show, NULL);
504}
505
506static const struct file_operations gpio_regs_operations = {
507 .open = gpio_regs_open,
508 .read = seq_read,
509 .llseek = seq_lseek,
510 .release = single_release,
511};
512
513static int __init gpio_debugfs_init(void)
514{
515 (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
516 NULL, NULL, &gpio_regs_operations);
517 return 0;
518}
519subsys_initcall(gpio_debugfs_init);
520
521#endif
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform GPIO support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19
20#include <linux/spinlock.h>
21#include <linux/syscore_ops.h>
22#include <linux/io.h>
23#include <linux/gpio.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/bitops.h>
27
28#include <linux/debugfs.h>
29#include <linux/seq_file.h>
30
31#include <asm/mach-jz4740/base.h>
32
33#define JZ4740_GPIO_BASE_A (32*0)
34#define JZ4740_GPIO_BASE_B (32*1)
35#define JZ4740_GPIO_BASE_C (32*2)
36#define JZ4740_GPIO_BASE_D (32*3)
37
38#define JZ4740_GPIO_NUM_A 32
39#define JZ4740_GPIO_NUM_B 32
40#define JZ4740_GPIO_NUM_C 31
41#define JZ4740_GPIO_NUM_D 32
42
43#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
44#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
45#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
46#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
47
48#define JZ_REG_GPIO_PIN 0x00
49#define JZ_REG_GPIO_DATA 0x10
50#define JZ_REG_GPIO_DATA_SET 0x14
51#define JZ_REG_GPIO_DATA_CLEAR 0x18
52#define JZ_REG_GPIO_MASK 0x20
53#define JZ_REG_GPIO_MASK_SET 0x24
54#define JZ_REG_GPIO_MASK_CLEAR 0x28
55#define JZ_REG_GPIO_PULL 0x30
56#define JZ_REG_GPIO_PULL_SET 0x34
57#define JZ_REG_GPIO_PULL_CLEAR 0x38
58#define JZ_REG_GPIO_FUNC 0x40
59#define JZ_REG_GPIO_FUNC_SET 0x44
60#define JZ_REG_GPIO_FUNC_CLEAR 0x48
61#define JZ_REG_GPIO_SELECT 0x50
62#define JZ_REG_GPIO_SELECT_SET 0x54
63#define JZ_REG_GPIO_SELECT_CLEAR 0x58
64#define JZ_REG_GPIO_DIRECTION 0x60
65#define JZ_REG_GPIO_DIRECTION_SET 0x64
66#define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
67#define JZ_REG_GPIO_TRIGGER 0x70
68#define JZ_REG_GPIO_TRIGGER_SET 0x74
69#define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
70#define JZ_REG_GPIO_FLAG 0x80
71#define JZ_REG_GPIO_FLAG_CLEAR 0x14
72
73#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
74#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
75#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
76
77struct jz_gpio_chip {
78 unsigned int irq;
79 unsigned int irq_base;
80 uint32_t wakeup;
81 uint32_t suspend_mask;
82 uint32_t edge_trigger_both;
83
84 void __iomem *base;
85
86 spinlock_t lock;
87
88 struct gpio_chip gpio_chip;
89};
90
91static struct jz_gpio_chip jz4740_gpio_chips[];
92
93static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
94{
95 return &jz4740_gpio_chips[gpio >> 5];
96}
97
98static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip)
99{
100 return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
101}
102
103static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data)
104{
105 return irq_data_get_irq_chip_data(data);
106}
107
108static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
109{
110 writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
111}
112
113int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
114{
115 if (function == JZ_GPIO_FUNC_NONE) {
116 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
117 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
118 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
119 } else {
120 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
121 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
122 switch (function) {
123 case JZ_GPIO_FUNC1:
124 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
125 break;
126 case JZ_GPIO_FUNC3:
127 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
128 case JZ_GPIO_FUNC2: /* Falltrough */
129 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
130 break;
131 default:
132 BUG();
133 break;
134 }
135 }
136
137 return 0;
138}
139EXPORT_SYMBOL_GPL(jz_gpio_set_function);
140
141int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
142{
143 size_t i;
144 int ret;
145
146 for (i = 0; i < num; ++i, ++request) {
147 ret = gpio_request(request->gpio, request->name);
148 if (ret)
149 goto err;
150 jz_gpio_set_function(request->gpio, request->function);
151 }
152
153 return 0;
154
155err:
156 for (--request; i > 0; --i, --request) {
157 gpio_free(request->gpio);
158 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
159 }
160
161 return ret;
162}
163EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
164
165void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
166{
167 size_t i;
168
169 for (i = 0; i < num; ++i, ++request) {
170 gpio_free(request->gpio);
171 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
172 }
173
174}
175EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
176
177void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
178{
179 size_t i;
180
181 for (i = 0; i < num; ++i, ++request) {
182 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
183 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
184 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
185 }
186}
187EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
188
189void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
190{
191 size_t i;
192
193 for (i = 0; i < num; ++i, ++request)
194 jz_gpio_set_function(request->gpio, request->function);
195}
196EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
197
198void jz_gpio_enable_pullup(unsigned gpio)
199{
200 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
201}
202EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
203
204void jz_gpio_disable_pullup(unsigned gpio)
205{
206 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
207}
208EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
209
210static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
211{
212 return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
213}
214
215static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
216{
217 uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
218 reg += !value;
219 writel(BIT(gpio), reg);
220}
221
222static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
223 int value)
224{
225 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
226 jz_gpio_set_value(chip, gpio, value);
227
228 return 0;
229}
230
231static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
232{
233 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
234
235 return 0;
236}
237
238int jz_gpio_port_direction_input(int port, uint32_t mask)
239{
240 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
241
242 return 0;
243}
244EXPORT_SYMBOL(jz_gpio_port_direction_input);
245
246int jz_gpio_port_direction_output(int port, uint32_t mask)
247{
248 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
249
250 return 0;
251}
252EXPORT_SYMBOL(jz_gpio_port_direction_output);
253
254void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
255{
256 writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
257 writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
258}
259EXPORT_SYMBOL(jz_gpio_port_set_value);
260
261uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
262{
263 uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
264
265 return value & mask;
266}
267EXPORT_SYMBOL(jz_gpio_port_get_value);
268
269int gpio_to_irq(unsigned gpio)
270{
271 return JZ4740_IRQ_GPIO(0) + gpio;
272}
273EXPORT_SYMBOL_GPL(gpio_to_irq);
274
275int irq_to_gpio(unsigned irq)
276{
277 return irq - JZ4740_IRQ_GPIO(0);
278}
279EXPORT_SYMBOL_GPL(irq_to_gpio);
280
281#define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f)
282
283static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
284{
285 uint32_t value;
286 void __iomem *reg;
287 uint32_t mask = IRQ_TO_BIT(irq);
288
289 if (!(chip->edge_trigger_both & mask))
290 return;
291
292 reg = chip->base;
293
294 value = readl(chip->base + JZ_REG_GPIO_PIN);
295 if (value & mask)
296 reg += JZ_REG_GPIO_DIRECTION_CLEAR;
297 else
298 reg += JZ_REG_GPIO_DIRECTION_SET;
299
300 writel(mask, reg);
301}
302
303static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
304{
305 uint32_t flag;
306 unsigned int gpio_irq;
307 unsigned int gpio_bank;
308 struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
309
310 gpio_bank = JZ4740_IRQ_GPIO0 - irq;
311
312 flag = readl(chip->base + JZ_REG_GPIO_FLAG);
313
314 if (!flag)
315 return;
316
317 gpio_irq = __fls(flag);
318
319 jz_gpio_check_trigger_both(chip, irq);
320
321 gpio_irq += (gpio_bank << 5) + JZ4740_IRQ_GPIO(0);
322
323 generic_handle_irq(gpio_irq);
324};
325
326static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg)
327{
328 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
329 writel(IRQ_TO_BIT(data->irq), chip->base + reg);
330}
331
332static void jz_gpio_irq_mask(struct irq_data *data)
333{
334 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_SET);
335};
336
337static void jz_gpio_irq_unmask(struct irq_data *data)
338{
339 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
340
341 jz_gpio_check_trigger_both(chip, data->irq);
342
343 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_CLEAR);
344};
345
346/* TODO: Check if function is gpio */
347static unsigned int jz_gpio_irq_startup(struct irq_data *data)
348{
349 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET);
350 jz_gpio_irq_unmask(data);
351 return 0;
352}
353
354static void jz_gpio_irq_shutdown(struct irq_data *data)
355{
356 jz_gpio_irq_mask(data);
357
358 /* Set direction to input */
359 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
360 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR);
361}
362
363static void jz_gpio_irq_ack(struct irq_data *data)
364{
365 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_FLAG_CLEAR);
366};
367
368static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
369{
370 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
371 unsigned int irq = data->irq;
372
373 if (flow_type == IRQ_TYPE_EDGE_BOTH) {
374 uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
375 if (value & IRQ_TO_BIT(irq))
376 flow_type = IRQ_TYPE_EDGE_FALLING;
377 else
378 flow_type = IRQ_TYPE_EDGE_RISING;
379 chip->edge_trigger_both |= IRQ_TO_BIT(irq);
380 } else {
381 chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
382 }
383
384 switch (flow_type) {
385 case IRQ_TYPE_EDGE_RISING:
386 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
387 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
388 break;
389 case IRQ_TYPE_EDGE_FALLING:
390 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
391 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
392 break;
393 case IRQ_TYPE_LEVEL_HIGH:
394 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
395 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
396 break;
397 case IRQ_TYPE_LEVEL_LOW:
398 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
399 jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
400 break;
401 default:
402 return -EINVAL;
403 }
404
405 return 0;
406}
407
408static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
409{
410 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
411 spin_lock(&chip->lock);
412 if (on)
413 chip->wakeup |= IRQ_TO_BIT(data->irq);
414 else
415 chip->wakeup &= ~IRQ_TO_BIT(data->irq);
416 spin_unlock(&chip->lock);
417
418 irq_set_irq_wake(chip->irq, on);
419 return 0;
420}
421
422static struct irq_chip jz_gpio_irq_chip = {
423 .name = "GPIO",
424 .irq_mask = jz_gpio_irq_mask,
425 .irq_unmask = jz_gpio_irq_unmask,
426 .irq_ack = jz_gpio_irq_ack,
427 .irq_startup = jz_gpio_irq_startup,
428 .irq_shutdown = jz_gpio_irq_shutdown,
429 .irq_set_type = jz_gpio_irq_set_type,
430 .irq_set_wake = jz_gpio_irq_set_wake,
431 .flags = IRQCHIP_SET_TYPE_MASKED,
432};
433
434/*
435 * This lock class tells lockdep that GPIO irqs are in a different
436 * category than their parents, so it won't report false recursion.
437 */
438static struct lock_class_key gpio_lock_class;
439
440#define JZ4740_GPIO_CHIP(_bank) { \
441 .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
442 .gpio_chip = { \
443 .label = "Bank " # _bank, \
444 .owner = THIS_MODULE, \
445 .set = jz_gpio_set_value, \
446 .get = jz_gpio_get_value, \
447 .direction_output = jz_gpio_direction_output, \
448 .direction_input = jz_gpio_direction_input, \
449 .base = JZ4740_GPIO_BASE_ ## _bank, \
450 .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
451 }, \
452}
453
454static struct jz_gpio_chip jz4740_gpio_chips[] = {
455 JZ4740_GPIO_CHIP(A),
456 JZ4740_GPIO_CHIP(B),
457 JZ4740_GPIO_CHIP(C),
458 JZ4740_GPIO_CHIP(D),
459};
460
461static void jz4740_gpio_suspend_chip(struct jz_gpio_chip *chip)
462{
463 chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
464 writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
465 writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
466}
467
468static int jz4740_gpio_suspend(void)
469{
470 int i;
471
472 for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); i++)
473 jz4740_gpio_suspend_chip(&jz4740_gpio_chips[i]);
474
475 return 0;
476}
477
478static void jz4740_gpio_resume_chip(struct jz_gpio_chip *chip)
479{
480 uint32_t mask = chip->suspend_mask;
481
482 writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR);
483 writel(mask, chip->base + JZ_REG_GPIO_MASK_SET);
484}
485
486static void jz4740_gpio_resume(void)
487{
488 int i;
489
490 for (i = ARRAY_SIZE(jz4740_gpio_chips) - 1; i >= 0 ; i--)
491 jz4740_gpio_resume_chip(&jz4740_gpio_chips[i]);
492}
493
494static struct syscore_ops jz4740_gpio_syscore_ops = {
495 .suspend = jz4740_gpio_suspend,
496 .resume = jz4740_gpio_resume,
497};
498
499static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
500{
501 int irq;
502
503 spin_lock_init(&chip->lock);
504
505 chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
506
507 gpiochip_add(&chip->gpio_chip);
508
509 chip->irq = JZ4740_IRQ_INTC_GPIO(id);
510 irq_set_handler_data(chip->irq, chip);
511 irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
512
513 for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
514 irq_set_lockdep_class(irq, &gpio_lock_class);
515 irq_set_chip_data(irq, chip);
516 irq_set_chip_and_handler(irq, &jz_gpio_irq_chip,
517 handle_level_irq);
518 }
519}
520
521static int __init jz4740_gpio_init(void)
522{
523 unsigned int i;
524
525 for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
526 jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
527
528 register_syscore_ops(&jz4740_gpio_syscore_ops);
529
530 printk(KERN_INFO "JZ4740 GPIO initialized\n");
531
532 return 0;
533}
534arch_initcall(jz4740_gpio_init);
535
536#ifdef CONFIG_DEBUG_FS
537
538static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,
539 const char *name, unsigned int reg)
540{
541 seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
542}
543
544static int gpio_regs_show(struct seq_file *s, void *unused)
545{
546 struct jz_gpio_chip *chip = jz4740_gpio_chips;
547 int i;
548
549 for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
550 seq_printf(s, "==GPIO %d==\n", i);
551 gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
552 gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
553 gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
554 gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
555 gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
556 gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
557 gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
558 gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
559 gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
560 }
561
562 return 0;
563}
564
565static int gpio_regs_open(struct inode *inode, struct file *file)
566{
567 return single_open(file, gpio_regs_show, NULL);
568}
569
570static const struct file_operations gpio_regs_operations = {
571 .open = gpio_regs_open,
572 .read = seq_read,
573 .llseek = seq_lseek,
574 .release = single_release,
575};
576
577static int __init gpio_debugfs_init(void)
578{
579 (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
580 NULL, NULL, &gpio_regs_operations);
581 return 0;
582}
583subsys_initcall(gpio_debugfs_init);
584
585#endif