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1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NLM_MIPS_EXTS_H
36#define _ASM_NLM_MIPS_EXTS_H
37
38/*
39 * XLR and XLP interrupt request and interrupt mask registers
40 */
41/*
42 * NOTE: Do not save/restore flags around write_c0_eimr().
43 * On non-R2 platforms the flags has part of EIMR that is shadowed in STATUS
44 * register. Restoring flags will overwrite the lower 8 bits of EIMR.
45 *
46 * Call with interrupts disabled.
47 */
48#define write_c0_eimr(val) \
49do { \
50 if (sizeof(unsigned long) == 4) { \
51 __asm__ __volatile__( \
52 ".set\tmips64\n\t" \
53 "dsll\t%L0, %L0, 32\n\t" \
54 "dsrl\t%L0, %L0, 32\n\t" \
55 "dsll\t%M0, %M0, 32\n\t" \
56 "or\t%L0, %L0, %M0\n\t" \
57 "dmtc0\t%L0, $9, 7\n\t" \
58 ".set\tmips0" \
59 : : "r" (val)); \
60 } else \
61 __write_64bit_c0_register($9, 7, (val)); \
62} while (0)
63
64/*
65 * Handling the 64 bit EIMR and EIRR registers in 32-bit mode with
66 * standard functions will be very inefficient. This provides
67 * optimized functions for the normal operations on the registers.
68 *
69 * Call with interrupts disabled.
70 */
71static inline void ack_c0_eirr(int irq)
72{
73 __asm__ __volatile__(
74 ".set push\n\t"
75 ".set mips64\n\t"
76 ".set noat\n\t"
77 "li $1, 1\n\t"
78 "dsllv $1, $1, %0\n\t"
79 "dmtc0 $1, $9, 6\n\t"
80 ".set pop"
81 : : "r" (irq));
82}
83
84static inline void set_c0_eimr(int irq)
85{
86 __asm__ __volatile__(
87 ".set push\n\t"
88 ".set mips64\n\t"
89 ".set noat\n\t"
90 "li $1, 1\n\t"
91 "dsllv %0, $1, %0\n\t"
92 "dmfc0 $1, $9, 7\n\t"
93 "or $1, %0\n\t"
94 "dmtc0 $1, $9, 7\n\t"
95 ".set pop"
96 : "+r" (irq));
97}
98
99static inline void clear_c0_eimr(int irq)
100{
101 __asm__ __volatile__(
102 ".set push\n\t"
103 ".set mips64\n\t"
104 ".set noat\n\t"
105 "li $1, 1\n\t"
106 "dsllv %0, $1, %0\n\t"
107 "dmfc0 $1, $9, 7\n\t"
108 "or $1, %0\n\t"
109 "xor $1, %0\n\t"
110 "dmtc0 $1, $9, 7\n\t"
111 ".set pop"
112 : "+r" (irq));
113}
114
115/*
116 * Read c0 eimr and c0 eirr, do AND of the two values, the result is
117 * the interrupts which are raised and are not masked.
118 */
119static inline uint64_t read_c0_eirr_and_eimr(void)
120{
121 uint64_t val;
122
123#ifdef CONFIG_64BIT
124 val = __read_64bit_c0_register($9, 6) & __read_64bit_c0_register($9, 7);
125#else
126 __asm__ __volatile__(
127 ".set push\n\t"
128 ".set mips64\n\t"
129 ".set noat\n\t"
130 "dmfc0 %M0, $9, 6\n\t"
131 "dmfc0 %L0, $9, 7\n\t"
132 "and %M0, %L0\n\t"
133 "dsll %L0, %M0, 32\n\t"
134 "dsra %M0, %M0, 32\n\t"
135 "dsra %L0, %L0, 32\n\t"
136 ".set pop"
137 : "=r" (val));
138#endif
139 return val;
140}
141
142static inline int hard_smp_processor_id(void)
143{
144 return __read_32bit_c0_register($15, 1) & 0x3ff;
145}
146
147static inline int nlm_nodeid(void)
148{
149 uint32_t prid = read_c0_prid();
150
151 if ((prid & 0xff00) == PRID_IMP_NETLOGIC_XLP9XX)
152 return (__read_32bit_c0_register($15, 1) >> 7) & 0x7;
153 else
154 return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
155}
156
157static inline unsigned int nlm_core_id(void)
158{
159 return (read_c0_ebase() & 0x1c) >> 2;
160}
161
162static inline unsigned int nlm_thread_id(void)
163{
164 return read_c0_ebase() & 0x3;
165}
166
167#define __read_64bit_c2_split(source, sel) \
168({ \
169 unsigned long long __val; \
170 unsigned long __flags; \
171 \
172 local_irq_save(__flags); \
173 if (sel == 0) \
174 __asm__ __volatile__( \
175 ".set\tmips64\n\t" \
176 "dmfc2\t%M0, " #source "\n\t" \
177 "dsll\t%L0, %M0, 32\n\t" \
178 "dsra\t%M0, %M0, 32\n\t" \
179 "dsra\t%L0, %L0, 32\n\t" \
180 ".set\tmips0\n\t" \
181 : "=r" (__val)); \
182 else \
183 __asm__ __volatile__( \
184 ".set\tmips64\n\t" \
185 "dmfc2\t%M0, " #source ", " #sel "\n\t" \
186 "dsll\t%L0, %M0, 32\n\t" \
187 "dsra\t%M0, %M0, 32\n\t" \
188 "dsra\t%L0, %L0, 32\n\t" \
189 ".set\tmips0\n\t" \
190 : "=r" (__val)); \
191 local_irq_restore(__flags); \
192 \
193 __val; \
194})
195
196#define __write_64bit_c2_split(source, sel, val) \
197do { \
198 unsigned long __flags; \
199 \
200 local_irq_save(__flags); \
201 if (sel == 0) \
202 __asm__ __volatile__( \
203 ".set\tmips64\n\t" \
204 "dsll\t%L0, %L0, 32\n\t" \
205 "dsrl\t%L0, %L0, 32\n\t" \
206 "dsll\t%M0, %M0, 32\n\t" \
207 "or\t%L0, %L0, %M0\n\t" \
208 "dmtc2\t%L0, " #source "\n\t" \
209 ".set\tmips0\n\t" \
210 : : "r" (val)); \
211 else \
212 __asm__ __volatile__( \
213 ".set\tmips64\n\t" \
214 "dsll\t%L0, %L0, 32\n\t" \
215 "dsrl\t%L0, %L0, 32\n\t" \
216 "dsll\t%M0, %M0, 32\n\t" \
217 "or\t%L0, %L0, %M0\n\t" \
218 "dmtc2\t%L0, " #source ", " #sel "\n\t" \
219 ".set\tmips0\n\t" \
220 : : "r" (val)); \
221 local_irq_restore(__flags); \
222} while (0)
223
224#define __read_32bit_c2_register(source, sel) \
225({ uint32_t __res; \
226 if (sel == 0) \
227 __asm__ __volatile__( \
228 ".set\tmips32\n\t" \
229 "mfc2\t%0, " #source "\n\t" \
230 ".set\tmips0\n\t" \
231 : "=r" (__res)); \
232 else \
233 __asm__ __volatile__( \
234 ".set\tmips32\n\t" \
235 "mfc2\t%0, " #source ", " #sel "\n\t" \
236 ".set\tmips0\n\t" \
237 : "=r" (__res)); \
238 __res; \
239})
240
241#define __read_64bit_c2_register(source, sel) \
242({ unsigned long long __res; \
243 if (sizeof(unsigned long) == 4) \
244 __res = __read_64bit_c2_split(source, sel); \
245 else if (sel == 0) \
246 __asm__ __volatile__( \
247 ".set\tmips64\n\t" \
248 "dmfc2\t%0, " #source "\n\t" \
249 ".set\tmips0\n\t" \
250 : "=r" (__res)); \
251 else \
252 __asm__ __volatile__( \
253 ".set\tmips64\n\t" \
254 "dmfc2\t%0, " #source ", " #sel "\n\t" \
255 ".set\tmips0\n\t" \
256 : "=r" (__res)); \
257 __res; \
258})
259
260#define __write_64bit_c2_register(register, sel, value) \
261do { \
262 if (sizeof(unsigned long) == 4) \
263 __write_64bit_c2_split(register, sel, value); \
264 else if (sel == 0) \
265 __asm__ __volatile__( \
266 ".set\tmips64\n\t" \
267 "dmtc2\t%z0, " #register "\n\t" \
268 ".set\tmips0\n\t" \
269 : : "Jr" (value)); \
270 else \
271 __asm__ __volatile__( \
272 ".set\tmips64\n\t" \
273 "dmtc2\t%z0, " #register ", " #sel "\n\t" \
274 ".set\tmips0\n\t" \
275 : : "Jr" (value)); \
276} while (0)
277
278#define __write_32bit_c2_register(reg, sel, value) \
279({ \
280 if (sel == 0) \
281 __asm__ __volatile__( \
282 ".set\tmips32\n\t" \
283 "mtc2\t%z0, " #reg "\n\t" \
284 ".set\tmips0\n\t" \
285 : : "Jr" (value)); \
286 else \
287 __asm__ __volatile__( \
288 ".set\tmips32\n\t" \
289 "mtc2\t%z0, " #reg ", " #sel "\n\t" \
290 ".set\tmips0\n\t" \
291 : : "Jr" (value)); \
292})
293
294#endif /*_ASM_NLM_MIPS_EXTS_H */
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _ASM_NLM_MIPS_EXTS_H
36#define _ASM_NLM_MIPS_EXTS_H
37
38/*
39 * XLR and XLP interrupt request and interrupt mask registers
40 */
41#define read_c0_eirr() __read_64bit_c0_register($9, 6)
42#define read_c0_eimr() __read_64bit_c0_register($9, 7)
43#define write_c0_eirr(val) __write_64bit_c0_register($9, 6, val)
44
45/*
46 * Writing EIMR in 32 bit is a special case, the lower 8 bit of the
47 * EIMR is shadowed in the status register, so we cannot save and
48 * restore status register for split read.
49 */
50#define write_c0_eimr(val) \
51do { \
52 if (sizeof(unsigned long) == 4) { \
53 unsigned long __flags; \
54 \
55 local_irq_save(__flags); \
56 __asm__ __volatile__( \
57 ".set\tmips64\n\t" \
58 "dsll\t%L0, %L0, 32\n\t" \
59 "dsrl\t%L0, %L0, 32\n\t" \
60 "dsll\t%M0, %M0, 32\n\t" \
61 "or\t%L0, %L0, %M0\n\t" \
62 "dmtc0\t%L0, $9, 7\n\t" \
63 ".set\tmips0" \
64 : : "r" (val)); \
65 __flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\
66 local_irq_restore(__flags); \
67 } else \
68 __write_64bit_c0_register($9, 7, (val)); \
69} while (0)
70
71static inline int hard_smp_processor_id(void)
72{
73 return __read_32bit_c0_register($15, 1) & 0x3ff;
74}
75
76#endif /*_ASM_NLM_MIPS_EXTS_H */